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Imported Upstream version 5.18.0.167

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Former-commit-id: 289509151e0fee68a1b591a20c9f109c3c789d3a
This commit is contained in:
Xamarin Public Jenkins (auto-signing)
2018-10-20 08:25:10 +00:00
parent e19d552987
commit b084638f15
28489 changed files with 184 additions and 3866856 deletions
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48
external/llvm/test/CodeGen/AMDGPU/subreg-intervals.mir vendored
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@@ -1,48 +0,0 @@
# RUN: llc -march=amdgcn -run-pass liveintervals -debug-only=regalloc -o /dev/null %s 2>&1 | FileCheck %s
# REQUIRES: asserts
# CHECK: INTERVALS
# CHECK: %0
# CHECK-LABEL: Machine code for function test0:
# CHECK: INTERVALS
# CHECK: %0
# CHECK-LABEL: Machine code for function test1:
--- |
define amdgpu_kernel void @test0() { ret void }
define amdgpu_kernel void @test1() { ret void }
...
---
name: test0
registers:
- { id: 0, class: sreg_64 }
body: |
bb.0:
S_NOP 0, implicit-def %0
S_NOP 0, implicit %0
S_NOP 0, implicit-def undef %0.sub0
S_NOP 0, implicit %0
...
---
name: test1
registers:
- { id: 0, class: sreg_64 }
body: |
bb.0:
S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc
S_BRANCH %bb.2
bb.1:
S_NOP 0, implicit-def undef %0.sub0
S_BRANCH %bb.3
bb.2:
S_NOP 0, implicit-def %0
S_BRANCH %bb.3
bb.3:
S_NOP 0
S_NOP 0, implicit %0
...