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Imported Upstream version 5.18.0.167

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Former-commit-id: 289509151e0fee68a1b591a20c9f109c3c789d3a
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Xamarin Public Jenkins (auto-signing)
2018-10-20 08:25:10 +00:00
parent e19d552987
commit b084638f15
28489 changed files with 184 additions and 3866856 deletions
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38
external/llvm/test/CodeGen/AMDGPU/fcmp.ll vendored
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@ -1,38 +0,0 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
; CHECK: {{^}}fcmp_sext:
; CHECK: SETE_DX10 T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
define amdgpu_kernel void @fcmp_sext(i32 addrspace(1)* %out, float addrspace(1)* %in) {
entry:
%0 = load float, float addrspace(1)* %in
%arrayidx1 = getelementptr inbounds float, float addrspace(1)* %in, i32 1
%1 = load float, float addrspace(1)* %arrayidx1
%cmp = fcmp oeq float %0, %1
%sext = sext i1 %cmp to i32
store i32 %sext, i32 addrspace(1)* %out
ret void
}
; This test checks that a setcc node with f32 operands is lowered to a
; SET*_DX10 instruction. Previously we were lowering this to:
; SET* + FP_TO_SINT
; CHECK: {{^}}fcmp_br:
; CHECK: SET{{[N]*}}E_DX10 * T{{[0-9]+\.[XYZW],}}
; CHECK-NEXT: {{[0-9]+\(5.0}}
define amdgpu_kernel void @fcmp_br(i32 addrspace(1)* %out, float %in) {
entry:
%0 = fcmp oeq float %in, 5.0
br i1 %0, label %IF, label %ENDIF
IF:
%1 = getelementptr i32, i32 addrspace(1)* %out, i32 1
store i32 0, i32 addrspace(1)* %1
br label %ENDIF
ENDIF:
store i32 0, i32 addrspace(1)* %out
ret void
}