Imported Upstream version 5.18.0.167

Former-commit-id: 289509151e0fee68a1b591a20c9f109c3c789d3a
2018-10-20 08:25:10 +00:00
parent e19d552987
commit b084638f15
28489 changed files with 184 additions and 3866856 deletions
--- a/external/llvm/test/CodeGen/AMDGPU/32-bit-local-address-space.ll
+++ b/external/llvm/test/CodeGen/AMDGPU/32-bit-local-address-space.ll
@ -1,139 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-
-; On Southern Islands GPUs the local address space(3) uses 32-bit pointers and
-; the global address space(1) uses 64-bit pointers.  These tests check to make sure
-; the correct pointer size is used for the local address space.
-
-; The e{{32|64}} suffix on the instructions refers to the encoding size and not
-; the size of the operands.  The operand size is denoted in the instruction name.
-; Instructions with B32, U32, and I32 in their name take 32-bit operands, while
-; instructions with B64, U64, and I64 take 64-bit operands.
-
-; FUNC-LABEL: {{^}}local_address_load:
-; SI: v_mov_b32_e{{32|64}} [[PTR:v[0-9]]]
-; SI: ds_read_b32 v{{[0-9]+}}, [[PTR]]
-define amdgpu_kernel void @local_address_load(i32 addrspace(1)* %out, i32 addrspace(3)* %in) {
-entry:
-  %0 = load i32, i32 addrspace(3)* %in
-  store i32 %0, i32 addrspace(1)* %out
-  ret void
-}
-
-; FUNC-LABEL: {{^}}local_address_gep:
-; SI: s_add_i32 [[SPTR:s[0-9]]]
-; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
-; SI: ds_read_b32 [[VPTR]]
-define amdgpu_kernel void @local_address_gep(i32 addrspace(1)* %out, i32 addrspace(3)* %in, i32 %offset) {
-entry:
-  %0 = getelementptr i32, i32 addrspace(3)* %in, i32 %offset
-  %1 = load i32, i32 addrspace(3)* %0
-  store i32 %1, i32 addrspace(1)* %out
-  ret void
-}
-
-; FUNC-LABEL: {{^}}local_address_gep_const_offset:
-; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], s{{[0-9]+}}
-; SI: ds_read_b32 v{{[0-9]+}}, [[VPTR]] offset:4
-define amdgpu_kernel void @local_address_gep_const_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %in) {
-entry:
-  %0 = getelementptr i32, i32 addrspace(3)* %in, i32 1
-  %1 = load i32, i32 addrspace(3)* %0
-  store i32 %1, i32 addrspace(1)* %out
-  ret void
-}
-
-; Offset too large, can't fold into 16-bit immediate offset.
-; FUNC-LABEL: {{^}}local_address_gep_large_const_offset:
-; SI: s_add_i32 [[SPTR:s[0-9]]], s{{[0-9]+}}, 0x10004
-; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
-; SI: ds_read_b32 [[VPTR]]
-define amdgpu_kernel void @local_address_gep_large_const_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %in) {
-entry:
-  %0 = getelementptr i32, i32 addrspace(3)* %in, i32 16385
-  %1 = load i32, i32 addrspace(3)* %0
-  store i32 %1, i32 addrspace(1)* %out
-  ret void
-}
-
-; FUNC-LABEL: {{^}}null_32bit_lds_ptr:
-; SI: v_cmp_ne_u32
-; SI-NOT: v_cmp_ne_u32
-; SI: v_cndmask_b32
-define amdgpu_kernel void @null_32bit_lds_ptr(i32 addrspace(1)* %out, i32 addrspace(3)* %lds) nounwind {
-  %cmp = icmp ne i32 addrspace(3)* %lds, null
-  %x = select i1 %cmp, i32 123, i32 456
-  store i32 %x, i32 addrspace(1)* %out
-  ret void
-}
-
-; FUNC-LABEL: {{^}}mul_32bit_ptr:
-; SI: s_mul_i32
-; SI-NEXT: s_add_i32
-; SI: ds_read_b32
-define amdgpu_kernel void @mul_32bit_ptr(float addrspace(1)* %out, [3 x float] addrspace(3)* %lds, i32 %tid) {
-  %ptr = getelementptr [3 x float], [3 x float] addrspace(3)* %lds, i32 %tid, i32 0
-  %val = load float, float addrspace(3)* %ptr
-  store float %val, float addrspace(1)* %out
-  ret void
-}
-
-@g_lds = addrspace(3) global float undef, align 4
-
-; FUNC-LABEL: {{^}}infer_ptr_alignment_global_offset:
-; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0
-; SI: ds_read_b32 v{{[0-9]+}}, [[REG]]
-define amdgpu_kernel void @infer_ptr_alignment_global_offset(float addrspace(1)* %out, i32 %tid) {
-  %val = load float, float addrspace(3)* @g_lds
-  store float %val, float addrspace(1)* %out
-  ret void
-}
-
-
-@ptr = addrspace(3) global i32 addrspace(3)* undef
-@dst = addrspace(3) global [16383 x i32] undef
-
-; FUNC-LABEL: {{^}}global_ptr:
-; SI: ds_write_b32
-define amdgpu_kernel void @global_ptr() nounwind {
-  store i32 addrspace(3)* getelementptr ([16383 x i32], [16383 x i32] addrspace(3)* @dst, i32 0, i32 16), i32 addrspace(3)* addrspace(3)* @ptr
-  ret void
-}
-
-; FUNC-LABEL: {{^}}local_address_store:
-; SI: ds_write_b32
-define amdgpu_kernel void @local_address_store(i32 addrspace(3)* %out, i32 %val) {
-  store i32 %val, i32 addrspace(3)* %out
-  ret void
-}
-
-; FUNC-LABEL: {{^}}local_address_gep_store:
-; SI: s_add_i32 [[SADDR:s[0-9]+]],
-; SI: v_mov_b32_e32 [[ADDR:v[0-9]+]], [[SADDR]]
-; SI: ds_write_b32 [[ADDR]], v{{[0-9]+}}
-define amdgpu_kernel void @local_address_gep_store(i32 addrspace(3)* %out, i32, i32 %val, i32 %offset) {
-  %gep = getelementptr i32, i32 addrspace(3)* %out, i32 %offset
-  store i32 %val, i32 addrspace(3)* %gep, align 4
-  ret void
-}
-
-; FUNC-LABEL: {{^}}local_address_gep_const_offset_store:
-; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], s{{[0-9]+}}
-; SI: v_mov_b32_e32 [[VAL:v[0-9]+]], s{{[0-9]+}}
-; SI: ds_write_b32 [[VPTR]], [[VAL]] offset:4
-define amdgpu_kernel void @local_address_gep_const_offset_store(i32 addrspace(3)* %out, i32 %val) {
-  %gep = getelementptr i32, i32 addrspace(3)* %out, i32 1
-  store i32 %val, i32 addrspace(3)* %gep, align 4
-  ret void
-}
-
-; Offset too large, can't fold into 16-bit immediate offset.
-; FUNC-LABEL: {{^}}local_address_gep_large_const_offset_store:
-; SI: s_add_i32 [[SPTR:s[0-9]]], s{{[0-9]+}}, 0x10004
-; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
-; SI: ds_write_b32 [[VPTR]], v{{[0-9]+$}}
-define amdgpu_kernel void @local_address_gep_large_const_offset_store(i32 addrspace(3)* %out, i32 %val) {
-  %gep = getelementptr i32, i32 addrspace(3)* %out, i32 16385
-  store i32 %val, i32 addrspace(3)* %gep, align 4
-  ret void
-}
--- a/external/llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll
+++ b/external/llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll
@ -1,13 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=fiji -O0 -stop-after=irtranslator -global-isel %s -o - 2>&1 | FileCheck %s
-; REQUIRES: global-isel
-; This file checks that the translation from llvm IR to generic MachineInstr
-; is correct.
-
-; Tests for add.
-; CHECK: name: addi32
-; CHECK: {{%[0-9]+}}:_(s32) = G_ADD
-define amdgpu_kernel void @addi32(i32 %arg1, i32 %arg2) {
-  %res = add i32 %arg1, %arg2
-  store i32 %res, i32 addrspace(1)* undef
-  ret void
-}
--- a/external/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir
+++ b/external/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir
@ -1,28 +0,0 @@
-# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
-# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
-
-# REQUIRES: global-isel
-
--- |
-  define amdgpu_kernel void @global_addrspace(i32 addrspace(1)* %global0) { ret void }
-...
---
-
-name:            global_addrspace
-legalized:       true
-regBankSelected: true
-
-# GCN: global_addrspace
-# GCN: [[PTR:%[0-9]+]]:vreg_64 = COPY %vgpr0_vgpr1
-# GCN: FLAT_LOAD_DWORD  [[PTR]], 0, 0, 0
-
-body: |
-  bb.0:
-    liveins:  %vgpr0_vgpr1
-
-    %0:vgpr(p1) = COPY %vgpr0_vgpr1
-    %1:vgpr(s32) = G_LOAD %0 :: (load 4 from %ir.global0)
-    %vgpr0 = COPY %1
-
-...
---
--- a/external/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir
+++ b/external/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir
@ -1,142 +0,0 @@
-# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN,SI,SICI,SIVI
-# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN,CI,SICI
-# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN,VI,SIVI
-
-# REQUIRES: global-isel
-
--- |
-  define amdgpu_kernel void @smrd_imm(i32 addrspace(2)* %const0) { ret void }
-...
---
-
-name:            smrd_imm
-legalized:       true
-regBankSelected: true
-
-# GCN: body:
-# GCN: [[PTR:%[0-9]+]]:sreg_64 = COPY %sgpr0_sgpr1
-
-# Immediate offset:
-# SICI: S_LOAD_DWORD_IMM [[PTR]], 1, 0
-# VI:   S_LOAD_DWORD_IMM [[PTR]], 4, 0
-
-# Max immediate offset for SI
-# SICI: S_LOAD_DWORD_IMM [[PTR]], 255, 0
-# VI:   S_LOAD_DWORD_IMM [[PTR]], 1020, 0
-
-# Immediate overflow for SI
-# SI: [[K1024:%[0-9]+]]:sreg_32 = S_MOV_B32 1024
-# SI: S_LOAD_DWORD_SGPR [[PTR]], [[K1024]], 0
-# CI: S_LOAD_DWORD_IMM_ci [[PTR]], 256, 0
-# VI: S_LOAD_DWORD_IMM [[PTR]], 1024, 0
-
-# Max immediate offset for VI
-# SI: [[K1048572:%[0-9]+]]:sreg_32 = S_MOV_B32 1048572
-# CI: S_LOAD_DWORD_IMM_ci [[PTR]], 262143
-# VI: S_LOAD_DWORD_IMM [[PTR]], 1048572
-
-#
-# Immediate overflow for VI
-# SIVI: [[K1048576:%[0-9]+]]:sreg_32 = S_MOV_B32 1048576
-# SIVI: S_LOAD_DWORD_SGPR [[PTR]], [[K1048576]], 0
-# CI: S_LOAD_DWORD_IMM_ci [[PTR]], 262144, 0
-
-# Max immediate for CI
-# SIVI: [[K_LO:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967292
-# SIVI: [[K_HI:%[0-9]+]]:sreg_32 = S_MOV_B32 3
-# SIVI: [[K:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[K_LO]], %subreg.sub0, [[K_HI]], %subreg.sub1
-# SIVI-DAG: [[K_SUB0:%[0-9]+]]:sgpr_32 = COPY [[K]].sub0
-# SIVI-DAG: [[PTR_LO:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub0
-# SIVI: [[ADD_PTR_LO:%[0-9]+]]:sreg_32 = S_ADD_U32 [[PTR_LO]], [[K_SUB0]]
-# SIVI-DAG: [[K_SUB1:%[0-9]+]]:sgpr_32 = COPY [[K]].sub1
-# SIVI-DAG: [[PTR_HI:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub1
-# SIVI: [[ADD_PTR_HI:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]]
-# SIVI: [[ADD_PTR:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[ADD_PTR_LO]], %subreg.sub0, [[ADD_PTR_HI]], %subreg.sub1
-# SIVI: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0
-# CI: S_LOAD_DWORD_IMM_ci [[PTR]], 4294967295, 0
-
-# Immediate overflow for CI
-# GCN: [[K_LO:%[0-9]+]]:sreg_32 = S_MOV_B32 0
-# GCN: [[K_HI:%[0-9]+]]:sreg_32 = S_MOV_B32 4
-# GCN: [[K:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[K_LO]], %subreg.sub0, [[K_HI]], %subreg.sub1
-# GCN-DAG: [[K_SUB0:%[0-9]+]]:sgpr_32 = COPY [[K]].sub0
-# GCN-DAG: [[PTR_LO:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub0
-# GCN: [[ADD_PTR_LO:%[0-9]+]]:sreg_32 = S_ADD_U32 [[PTR_LO]], [[K_SUB0]]
-# GCN-DAG: [[K_SUB1:%[0-9]+]]:sgpr_32 = COPY [[K]].sub1
-# GCN-DAG: [[PTR_HI:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub1
-# GCN: [[ADD_PTR_HI:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]]
-# GCN: [[ADD_PTR:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[ADD_PTR_LO]], %subreg.sub0, [[ADD_PTR_HI]], %subreg.sub1
-# GCN: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0
-
-# Max 32-bit byte offset
-# SIVI: [[K4294967292:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967292
-# SIVI: S_LOAD_DWORD_SGPR [[PTR]], [[K4294967292]], 0
-# CI: S_LOAD_DWORD_IMM_ci [[PTR]], 1073741823, 0
-
-# Overflow 32-bit byte offset
-# SIVI: [[K_LO:%[0-9]+]]:sreg_32 = S_MOV_B32 0
-# SIVI: [[K_HI:%[0-9]+]]:sreg_32 = S_MOV_B32 1
-# SIVI: [[K:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[K_LO]], %subreg.sub0, [[K_HI]], %subreg.sub1
-# SIVI-DAG: [[K_SUB0:%[0-9]+]]:sgpr_32 = COPY [[K]].sub0
-# SIVI-DAG: [[PTR_LO:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub0
-# SIVI: [[ADD_PTR_LO:%[0-9]+]]:sreg_32 = S_ADD_U32 [[PTR_LO]], [[K_SUB0]]
-# SIVI-DAG: [[K_SUB1:%[0-9]+]]:sgpr_32 = COPY [[K]].sub1
-# SIVI-DAG: [[PTR_HI:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub1
-# SIVI: [[ADD_PTR_HI:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]]
-# SIVI: [[ADD_PTR:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[ADD_PTR_LO]], %subreg.sub0, [[ADD_PTR_HI]], %subreg.sub1
-# SIVI: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0
-# CI: S_LOAD_DWORD_IMM_ci [[PTR]], 1073741824, 0
-
-body: |
-  bb.0:
-    liveins: %sgpr0_sgpr1
-
-    %0:sgpr(p2) = COPY %sgpr0_sgpr1
-
-    %1:sgpr(s64) = G_CONSTANT i64 4
-    %2:sgpr(p2) = G_GEP %0, %1
-    %3:sgpr(s32) = G_LOAD %2 :: (load 4 from %ir.const0)
-    %sgpr0 = COPY %3
-
-    %4:sgpr(s64) = G_CONSTANT i64 1020
-    %5:sgpr(p2) = G_GEP %0, %4
-    %6:sgpr(s32) = G_LOAD %5 :: (load 4 from %ir.const0)
-    %sgpr0 = COPY %6
-
-    %7:sgpr(s64) = G_CONSTANT i64 1024
-    %8:sgpr(p2) = G_GEP %0, %7
-    %9:sgpr(s32) = G_LOAD %8 :: (load 4 from %ir.const0)
-    %sgpr0 = COPY %9
-
-    %10:sgpr(s64) = G_CONSTANT i64 1048572
-    %11:sgpr(p2) = G_GEP %0, %10
-    %12:sgpr(s32) = G_LOAD %11 :: (load 4 from %ir.const0)
-    %sgpr0 = COPY %12
-
-    %13:sgpr(s64) = G_CONSTANT i64 1048576
-    %14:sgpr(p2) = G_GEP %0, %13
-    %15:sgpr(s32) = G_LOAD %14 :: (load 4 from %ir.const0)
-    %sgpr0 = COPY %15
-
-    %16:sgpr(s64) = G_CONSTANT i64 17179869180
-    %17:sgpr(p2) = G_GEP %0, %16
-    %18:sgpr(s32) = G_LOAD %17 :: (load 4 from %ir.const0)
-    %sgpr0 = COPY %18
-
-    %19:sgpr(s64) = G_CONSTANT i64 17179869184
-    %20:sgpr(p2) = G_GEP %0, %19
-    %21:sgpr(s32) = G_LOAD %20 :: (load 4 from %ir.const0)
-    %sgpr0 = COPY %21
-
-    %22:sgpr(s64) = G_CONSTANT i64 4294967292
-    %23:sgpr(p2) = G_GEP %0, %22
-    %24:sgpr(s32) = G_LOAD %23 :: (load 4 from %ir.const0)
-    %sgpr0 = COPY %24
-
-    %25:sgpr(s64) = G_CONSTANT i64 4294967296
-    %26:sgpr(p2) = G_GEP %0, %25
-    %27:sgpr(s32) = G_LOAD %26 :: (load 4 from %ir.const0)
-    %sgpr0 = COPY %27
-
-...
---
--- a/external/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-flat.mir
+++ b/external/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-flat.mir
@ -1,29 +0,0 @@
-# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
-# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
-
-# REQUIRES: global-isel
-
--- |
-  define amdgpu_kernel void @global_addrspace(i32 addrspace(1)* %global0) { ret void }
-...
---
-
-name:            global_addrspace
-legalized:       true
-regBankSelected: true
-
-# GCN: global_addrspace
-# GCN: [[PTR:%[0-9]+]]:vreg_64 = COPY %vgpr0_vgpr1
-# GCN: [[VAL:%[0-9]+]]:vgpr_32 = COPY %vgpr2
-# GCN: FLAT_STORE_DWORD [[PTR]], [[VAL]], 0, 0, 0
-
-body: |
-  bb.0:
-    liveins:  %vgpr0_vgpr1, %vgpr2
-
-    %0:vgpr(p1) = COPY %vgpr0_vgpr1
-    %1:vgpr(s32) = COPY %vgpr2
-    G_STORE %1, %0 :: (store 4 into %ir.global0)
-
-...
---
--- a/external/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll
+++ b/external/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll
@ -1,60 +0,0 @@
-; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=irtranslator -global-isel %s -o - | FileCheck %s
-
-
-; CHECK-LABEL: name: test_f32_inreg
-; CHECK: [[S0:%[0-9]+]]:_(s32) = COPY %sgpr0
-; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), %{{[0-9]+}}(s32), %{{[0-9]+}}(s32), [[S0]]
-define amdgpu_vs void @test_f32_inreg(float inreg %arg0) {
-  call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %arg0, float undef, float undef, float undef, i1 false, i1 false) #0
-  ret void
-}
-
-; CHECK-LABEL: name: test_f32
-; CHECK: [[V0:%[0-9]+]]:_(s32) = COPY %vgpr0
-; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), %{{[0-9]+}}(s32), %{{[0-9]+}}(s32), [[V0]]
-define amdgpu_vs void @test_f32(float %arg0) {
-  call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %arg0, float undef, float undef, float undef, i1 false, i1 false) #0
-  ret void
-}
-
-; CHECK-LABEL: name: test_ptr2_byval
-; CHECK: [[S01:%[0-9]+]]:_(p2) = COPY %sgpr0_sgpr1
-; CHECK: G_LOAD [[S01]]
-define amdgpu_vs void @test_ptr2_byval(i32 addrspace(2)* byval %arg0) {
-   %tmp0 = load volatile i32, i32 addrspace(2)* %arg0
-  ret void
-}
-
-; CHECK-LABEL: name: test_ptr2_inreg
-; CHECK: [[S01:%[0-9]+]]:_(p2) = COPY %sgpr0_sgpr1
-; CHECK: G_LOAD [[S01]]
-define amdgpu_vs void @test_ptr2_inreg(i32 addrspace(2)* inreg %arg0) {
-  %tmp0 = load volatile i32, i32 addrspace(2)* %arg0
-  ret void
-}
-
-; CHECK-LABEL: name: test_sgpr_alignment0
-; CHECK: [[S0:%[0-9]+]]:_(s32) = COPY %sgpr0
-; CHECK: [[S23:%[0-9]+]]:_(p2) = COPY %sgpr2_sgpr3
-; CHECK: G_LOAD [[S23]]
-; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), %{{[0-9]+}}(s32), %{{[0-9]+}}(s32), [[S0]]
-define amdgpu_vs void @test_sgpr_alignment0(float inreg %arg0, i32 addrspace(2)* inreg %arg1) {
-  %tmp0 = load volatile i32, i32 addrspace(2)* %arg1
-  call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %arg0, float undef, float undef, float undef, i1 false, i1 false) #0
-  ret void
-}
-
-; CHECK-LABEL: name: test_order
-; CHECK: [[S0:%[0-9]+]]:_(s32) = COPY %sgpr0
-; CHECK: [[S1:%[0-9]+]]:_(s32) = COPY %sgpr1
-; CHECK: [[V0:%[0-9]+]]:_(s32) = COPY %vgpr0
-; CHECK: [[V1:%[0-9]+]]:_(s32) = COPY %vgpr1
-; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), %{{[0-9]+}}(s32), %{{[0-9]+}}(s32), [[V0]](s32), [[S0]](s32), [[V1]](s32), [[S1]](s32)
-define amdgpu_vs void @test_order(float inreg %arg0, float inreg %arg1, float %arg2, float %arg3) {
-  call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %arg2, float %arg0, float %arg3, float %arg1, i1 false, i1 false) #0
-  ret void
-}
-
-declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1)  #0
-
-attributes #0 = { nounwind }
--- a/external/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir
+++ b/external/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir
@ -1,26 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
-
--- |
-  define void @test_add() { ret void }
-...
-
---
-name:            test_add
-registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-body: |
-  bb.0:
-    liveins: %vgpr0, %vgpr1
-
-    ; CHECK-LABEL: name: test_add
-    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %vgpr0
-    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %vgpr1
-    ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]]
-    %0(s32) = COPY %vgpr0
-    %1(s32) = COPY %vgpr1
-    %2(s32) = G_ADD %0, %1
-    %vgpr0 = COPY %2
-...
--- a/external/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
+++ b/external/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
@ -1,26 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
-
--- |
-  define void @test_and() { ret void }
-...
-
---
-name:            test_and
-registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-body: |
-  bb.0:
-    liveins: %vgpr0, %vgpr1
-
-    ; CHECK-LABEL: name: test_and
-    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %vgpr0
-    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %vgpr1
-    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[COPY1]]
-    %0(s32) = COPY %vgpr0
-    %1(s32) = COPY %vgpr1
-    %2(s32) = G_AND %0, %1
-    %vgpr0 = COPY %2
-...
--- a/external/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
+++ b/external/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
@ -1,26 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel %s -o - | FileCheck %s
-
--- |
-  define void @test_bitcast() { ret void }
-...
-
---
-name:            test_bitcast
-registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-body: |
-  bb.0:
-    liveins: %vgpr0
-
-    ; CHECK-LABEL: name: test_bitcast
-    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %vgpr0
-    ; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY]](s32)
-    ; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[BITCAST]](<2 x s16>)
-    %0(s32) = COPY %vgpr0
-    %1(<2 x s16>) = G_BITCAST %0
-    %2(s32) = G_BITCAST %1
-    %vgpr0 = COPY %2
-...
--- a/external/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir
+++ b/external/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir
@ -1,53 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
-
--- |
-  define void @test_constant() {
-  entry:
-    ret void
-  }
-
-  define void @test_fconstant() {
-  entry:
-    ret void
-  }
-
-  declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #1
-
-  attributes #1 = { nounwind }
-
-...
-
---
-name:            test_constant
-registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-body: |
-  bb.0.entry:
-
-    ; CHECK-LABEL: name: test_constant
-    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
-    ; CHECK: [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
-    ; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C1]](s1), [[C1]](s1)
-    %0(s32) = G_CONSTANT i32 5
-    %1(s1) = G_CONSTANT i1 0
-    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.f32), %0, %0, %0, %0, %0, %0, %1, %1;
-...
-
---
-name:            test_fconstant
-registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-body: |
-  bb.0.entry:
-
-    ; CHECK-LABEL: name: test_fconstant
-    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
-    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 7.500000e+00
-    %0(s32) = G_FCONSTANT float 1.0
-    %vgpr0 = COPY %0
-    %1(s32) = G_FCONSTANT float 7.5
-    %vgpr0 = COPY %1
-...
--- a/external/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
+++ b/external/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
@ -1,27 +0,0 @@
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -run-pass=legalizer -global-isel %s -o - | FileCheck %s
-
--- |
-  define void @test_fadd() {
-  entry:
-    ret void
-  }
-
-...
-
---
-name:            test_fadd
-registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-body: |
-  bb.0.entry:
-    liveins: %vgpr0, %vgpr1
-    ; CHECK-LABEL: name: test_fadd
-    ; CHECK: %2:_(s32) = G_FADD %0, %1
-
-    %0(s32) = COPY %vgpr0
-    %1(s32) = COPY %vgpr1
-    %2(s32) = G_FADD %0, %1
-    %vgpr0 = COPY %2
-...
--- a/external/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
+++ b/external/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
@ -1,26 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel %s -o - | FileCheck %s
-
--- |
-  define void @test_fmul() { ret void }
-...
-
---
-name:            test_fmul
-registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-body: |
-  bb.0:
-    liveins: %vgpr0, %vgpr1
-
-    ; CHECK-LABEL: name: test_fmul
-    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %vgpr0
-    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %vgpr1
-    ; CHECK: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[COPY1]]
-    %0(s32) = COPY %vgpr0
-    %1(s32) = COPY %vgpr1
-    %2(s32) = G_FMUL %0, %1
-    %vgpr0 = COPY %2
-...
--- a/external/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
+++ b/external/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
@ -1,31 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -march=amdgcn -mcpu=fiji  -run-pass=legalizer -global-isel %s -o - | FileCheck %s
-
--- |
-  define void @test_icmp() {
-  entry:
-    ret void
-  }
-...
-
---
-name:            test_icmp
-registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-body: |
-  bb.0.entry:
-    liveins: %vgpr0
-    ; CHECK-LABEL: name: test_icmp
-    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %vgpr0
-    ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
-    ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C]], [[COPY]]
-    ; CHECK: %vgpr0 = COPY [[SELECT]](s32)
-    %0(s32) = G_CONSTANT i32 0
-    %1(s32) = COPY %vgpr0
-    %2(s1) = G_ICMP intpred(ne), %0, %1
-    %3:_(s32) = G_SELECT %2(s1), %0(s32), %1(s32)
-    %vgpr0 = COPY %3
-...
--- a/external/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
+++ b/external/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
@ -1,25 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
-
--- |
-  define void @test_or() { ret void }
-...
---
-name:            test_or
-registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-body: |
-  bb.0:
-    liveins: %vgpr0, %vgpr1
-
-    ; CHECK-LABEL: name: test_or
-    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %vgpr0
-    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %vgpr1
-    ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[COPY1]]
-    %0(s32) = COPY %vgpr0
-    %1(s32) = COPY %vgpr1
-    %2(s32) = G_OR %0, %1
-    %vgpr0 = COPY %2
-...
--- a/external/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
+++ b/external/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
@ -1,36 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -march=amdgcn -mcpu=fiji  -run-pass=legalizer -global-isel %s -o - | FileCheck %s
-
--- |
-  define void @test_select() { ret void }
-...
-
---
-name:            test_select
-registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: _ }
-  - { id: 5, class: _ }
-body: |
-  bb.0:
-    liveins: %vgpr0
-    ; CHECK-LABEL: name: test_select
-    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %vgpr0
-    ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
-    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
-    ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C1]], [[C2]]
-    %0(s32) = G_CONSTANT i32 0
-    %1(s32) = COPY %vgpr0
-
-    %2(s1) = G_ICMP intpred(ne), %0, %1
-    %3(s32) = G_CONSTANT i32 1
-    %4(s32) = G_CONSTANT i32 2
-    %5(s32) = G_SELECT %2, %3, %4
-    %vgpr0 = COPY %5
-
-...
--- a/external/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
+++ b/external/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
@ -1,22 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
-
---
-name:            test_shl
-registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-body: |
-  bb.0.entry:
-    liveins: %vgpr0, %vgpr1
-
-    ; CHECK-LABEL: name: test_shl
-    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %vgpr0
-    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %vgpr1
-    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]]
-    %0(s32) = COPY %vgpr0
-    %1(s32) = COPY %vgpr1
-    %2(s32) = G_SHL %0, %1
-    %vgpr0 = COPY %2
-...
--- a/external/llvm/test/CodeGen/AMDGPU/GlobalISel/lit.local.cfg
+++ b/external/llvm/test/CodeGen/AMDGPU/GlobalISel/lit.local.cfg
@ -1,2 +0,0 @@
-if not 'global-isel' in config.root.available_features:
-    config.unsupported = True
--- a/external/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir
+++ b/external/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir
@ -1,69 +0,0 @@
-# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - | FileCheck %s
-
-# REQUIRES: global-isel
-
--- |
-  define amdgpu_kernel void @load_constant(i32 addrspace(2)* %ptr0) { ret void }
-  define amdgpu_kernel void @load_global_uniform(i32 addrspace(1)* %ptr1) {
-    %tmp0 = load i32, i32 addrspace(1)* %ptr1
-    ret void
-  }
-  define amdgpu_kernel void @load_global_non_uniform(i32 addrspace(1)* %ptr2) {
-    %tmp0 = call i32 @llvm.amdgcn.workitem.id.x() #0
-    %tmp1 = getelementptr i32, i32 addrspace(1)* %ptr2, i32 %tmp0
-    %tmp2 = load i32, i32 addrspace(1)* %tmp1
-    ret void
-  }
-  declare i32 @llvm.amdgcn.workitem.id.x() #0
-  attributes #0 = { nounwind readnone }
-...
-
---
-name : load_constant
-legalized: true
-
-# CHECK-LABEL: name: load_constant
-# CHECK: registers:
-# CHECK: - { id: 0, class: sgpr, preferred-register: '' }
-# CHECK: - { id: 1, class: sgpr, preferred-register: '' }
-
-body: |
-  bb.0:
-    liveins: %sgpr0_sgpr1
-    %0:_(p2) = COPY %sgpr0_sgpr1
-    %1:_(s32) = G_LOAD %0 :: (load 4 from %ir.ptr0)
-...
-
---
-name: load_global_uniform
-legalized: true
-
-# CHECK-LABEL: name: load_global_uniform
-# CHECK: registers:
-# CHECK: - { id: 0, class: sgpr, preferred-register: '' }
-# CHECK: - { id: 1, class: sgpr, preferred-register: '' }
-
-body: |
-  bb.0:
-    liveins: %sgpr0_sgpr1
-    %0:_(p1) = COPY %sgpr0_sgpr1
-    %1:_(s32) = G_LOAD %0 :: (load 4 from %ir.ptr1)
-...
-
---
-name: load_global_non_uniform
-legalized: true
-
-# CHECK-LABEL: name: load_global_non_uniform
-# CHECK: registers:
-# CHECK: - { id: 0, class: sgpr, preferred-register: '' }
-# CHECK: - { id: 1, class: vgpr, preferred-register: '' }
-# CHECK: - { id: 2, class: vgpr, preferred-register: '' }
-
-
-body: |
-  bb.0:
-    liveins: %sgpr0_sgpr1
-    %0:_(p1) = COPY %sgpr0_sgpr1
-    %1:_(s32) = G_LOAD %0 :: (load 4 from %ir.tmp1)
-...
--- a/external/llvm/test/CodeGen/AMDGPU/GlobalISel/shader-epilogs.ll
+++ b/external/llvm/test/CodeGen/AMDGPU/GlobalISel/shader-epilogs.ll
@ -1,11 +0,0 @@
-; RUN: llc < %s -march=amdgcn -mcpu=tonga -show-mc-encoding -verify-machineinstrs -global-isel | FileCheck --check-prefix=GCN %s
-
-; REQUIRES: global-isel
-
-; GCN-LABEL: vs_epilog
-; GCN: s_endpgm
-
-define amdgpu_vs void @vs_epilog() {
-main_body:
-  ret void
-}
--- a/external/llvm/test/CodeGen/AMDGPU/GlobalISel/smrd.ll
+++ b/external/llvm/test/CodeGen/AMDGPU/GlobalISel/smrd.ll
@ -1,89 +0,0 @@
-; FIXME: Need to add support for mubuf stores to enable this on SI.
-; XUN: llc < %s -march=amdgcn -mcpu=tahiti -show-mc-encoding -verify-machineinstrs -global-isel | FileCheck --check-prefix=SI --check-prefix=GCN --check-prefix=SIVI %s
-; RUN: llc < %s -march=amdgcn -mcpu=bonaire -show-mc-encoding -verify-machineinstrs -global-isel | FileCheck --check-prefix=CI --check-prefix=GCN %s
-; RUN: llc < %s -march=amdgcn -mcpu=tonga -show-mc-encoding -verify-machineinstrs -global-isel | FileCheck --check-prefix=VI --check-prefix=GCN --check-prefix=SIVI %s
-
-; REQUIRES: global-isel
-
-; SMRD load with an immediate offset.
-; GCN-LABEL: {{^}}smrd0:
-; SICI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x1 ; encoding: [0x01
-; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x4
-define amdgpu_kernel void @smrd0(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) {
-entry:
-  %0 = getelementptr i32, i32 addrspace(2)* %ptr, i64 1
-  %1 = load i32, i32 addrspace(2)* %0
-  store i32 %1, i32 addrspace(1)* %out
-  ret void
-}
-
-; SMRD load with the largest possible immediate offset.
-; GCN-LABEL: {{^}}smrd1:
-; SICI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff,0x{{[0-9]+[137]}}
-; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3fc
-define amdgpu_kernel void @smrd1(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) {
-entry:
-  %0 = getelementptr i32, i32 addrspace(2)* %ptr, i64 255
-  %1 = load i32, i32 addrspace(2)* %0
-  store i32 %1, i32 addrspace(1)* %out
-  ret void
-}
-
-; SMRD load with an offset greater than the largest possible immediate.
-; GCN-LABEL: {{^}}smrd2:
-; SI: s_movk_i32 s[[OFFSET:[0-9]]], 0x400
-; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]]
-; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x100
-; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x400
-; GCN: s_endpgm
-define amdgpu_kernel void @smrd2(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) {
-entry:
-  %0 = getelementptr i32, i32 addrspace(2)* %ptr, i64 256
-  %1 = load i32, i32 addrspace(2)* %0
-  store i32 %1, i32 addrspace(1)* %out
-  ret void
-}
-
-; SMRD load with a 64-bit offset
-; GCN-LABEL: {{^}}smrd3:
-; FIXME: There are too many copies here because we don't fold immediates
-;        through REG_SEQUENCE
-; XSI: s_load_dwordx2 s[{{[0-9]:[0-9]}}], s[{{[0-9]:[0-9]}}], 0xb ; encoding: [0x0b
-; TODO: Add VI checks
-; XGCN: s_endpgm
-define amdgpu_kernel void @smrd3(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) {
-entry:
-  %0 = getelementptr i32, i32 addrspace(2)* %ptr, i64 4294967296 ; 2 ^ 32
-  %1 = load i32, i32 addrspace(2)* %0
-  store i32 %1, i32 addrspace(1)* %out
-  ret void
-}
-
-; SMRD load with the largest possible immediate offset on VI
-; GCN-LABEL: {{^}}smrd4:
-; SI: s_mov_b32 [[OFFSET:s[0-9]+]], 0xffffc
-; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
-; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3ffff
-; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xffffc
-define amdgpu_kernel void @smrd4(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) {
-entry:
-  %0 = getelementptr i32, i32 addrspace(2)* %ptr, i64 262143
-  %1 = load i32, i32 addrspace(2)* %0
-  store i32 %1, i32 addrspace(1)* %out
-  ret void
-}
-
-; SMRD load with an offset greater than the largest possible immediate on VI
-; GCN-LABEL: {{^}}smrd5:
-; SIVI: s_mov_b32 [[OFFSET:s[0-9]+]], 0x100000
-; SIVI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
-; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x40000
-; GCN: s_endpgm
-define amdgpu_kernel void @smrd5(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) {
-entry:
-  %0 = getelementptr i32, i32 addrspace(2)* %ptr, i64 262144
-  %1 = load i32, i32 addrspace(2)* %0
-  store i32 %1, i32 addrspace(1)* %out
-  ret void
-}
-
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+++ b/Show More