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Imported Upstream version 5.18.0.167
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external/llvm/test/CodeGen/AArch64/bitfield.ll
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external/llvm/test/CodeGen/AArch64/bitfield.ll
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; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
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@var32 = global i32 0
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@var64 = global i64 0
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define void @test_extendb32(i8 %var) {
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; CHECK-LABEL: test_extendb32:
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%sxt32 = sext i8 %var to i32
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store volatile i32 %sxt32, i32* @var32
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; CHECK: sxtb {{w[0-9]+}}, {{w[0-9]+}}
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; N.b. this doesn't actually produce a bitfield instruction at the
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; moment, but it's still a good test to have and the semantics are
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; correct.
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%uxt32 = zext i8 %var to i32
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store volatile i32 %uxt32, i32* @var32
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; CHECK: and {{w[0-9]+}}, {{w[0-9]+}}, #0xff
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ret void
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}
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define void @test_extendb64(i8 %var) {
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; CHECK-LABEL: test_extendb64:
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%sxt64 = sext i8 %var to i64
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store volatile i64 %sxt64, i64* @var64
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; CHECK: sxtb {{x[0-9]+}}, {{w[0-9]+}}
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; N.b. this doesn't actually produce a bitfield instruction at the
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; moment, but it's still a good test to have and the semantics are
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; correct.
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%uxt64 = zext i8 %var to i64
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store volatile i64 %uxt64, i64* @var64
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; CHECK: and {{w[0-9]+}}, {{w[0-9]+}}, #0xff
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ret void
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}
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define void @test_extendh32(i16 %var) {
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; CHECK-LABEL: test_extendh32:
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%sxt32 = sext i16 %var to i32
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store volatile i32 %sxt32, i32* @var32
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; CHECK: sxth {{w[0-9]+}}, {{w[0-9]+}}
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; N.b. this doesn't actually produce a bitfield instruction at the
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; moment, but it's still a good test to have and the semantics are
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; correct.
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%uxt32 = zext i16 %var to i32
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store volatile i32 %uxt32, i32* @var32
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; CHECK: and {{w[0-9]+}}, {{w[0-9]+}}, #0xffff
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ret void
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}
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define void @test_extendh64(i16 %var) {
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; CHECK-LABEL: test_extendh64:
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%sxt64 = sext i16 %var to i64
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store volatile i64 %sxt64, i64* @var64
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; CHECK: sxth {{x[0-9]+}}, {{w[0-9]+}}
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; N.b. this doesn't actually produce a bitfield instruction at the
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; moment, but it's still a good test to have and the semantics are
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; correct.
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%uxt64 = zext i16 %var to i64
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store volatile i64 %uxt64, i64* @var64
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; CHECK: and {{w[0-9]+}}, {{w[0-9]+}}, #0xffff
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ret void
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}
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define void @test_extendw(i32 %var) {
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; CHECK-LABEL: test_extendw:
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%sxt64 = sext i32 %var to i64
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store volatile i64 %sxt64, i64* @var64
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; CHECK: sxtw {{x[0-9]+}}, {{w[0-9]+}}
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%uxt64 = zext i32 %var to i64
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store volatile i64 %uxt64, i64* @var64
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; CHECK: mov {{w[0-9]+}}, w0
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ret void
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}
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define void @test_shifts(i32 %val32, i64 %val64) {
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; CHECK-LABEL: test_shifts:
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%shift1 = ashr i32 %val32, 31
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store volatile i32 %shift1, i32* @var32
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; CHECK: asr {{w[0-9]+}}, {{w[0-9]+}}, #31
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%shift2 = lshr i32 %val32, 8
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store volatile i32 %shift2, i32* @var32
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; CHECK: lsr {{w[0-9]+}}, {{w[0-9]+}}, #8
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%shift3 = shl i32 %val32, 1
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store volatile i32 %shift3, i32* @var32
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; CHECK: lsl {{w[0-9]+}}, {{w[0-9]+}}, #1
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%shift4 = ashr i64 %val64, 31
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store volatile i64 %shift4, i64* @var64
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; CHECK: asr {{x[0-9]+}}, {{x[0-9]+}}, #31
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%shift5 = lshr i64 %val64, 8
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store volatile i64 %shift5, i64* @var64
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; CHECK: lsr {{x[0-9]+}}, {{x[0-9]+}}, #8
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%shift6 = shl i64 %val64, 63
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store volatile i64 %shift6, i64* @var64
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; CHECK: lsl {{x[0-9]+}}, {{x[0-9]+}}, #63
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%shift7 = ashr i64 %val64, 63
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store volatile i64 %shift7, i64* @var64
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; CHECK: asr {{x[0-9]+}}, {{x[0-9]+}}, #63
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%shift8 = lshr i64 %val64, 63
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store volatile i64 %shift8, i64* @var64
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; CHECK: lsr {{x[0-9]+}}, {{x[0-9]+}}, #63
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%shift9 = lshr i32 %val32, 31
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store volatile i32 %shift9, i32* @var32
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; CHECK: lsr {{w[0-9]+}}, {{w[0-9]+}}, #31
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%shift10 = shl i32 %val32, 31
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store volatile i32 %shift10, i32* @var32
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; CHECK: lsl {{w[0-9]+}}, {{w[0-9]+}}, #31
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ret void
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}
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; LLVM can produce in-register extensions taking place entirely with
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; 64-bit registers too.
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define void @test_sext_inreg_64(i64 %in) {
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; CHECK-LABEL: test_sext_inreg_64:
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; i1 doesn't have an official alias, but crops up and is handled by
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; the bitfield ops.
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%trunc_i1 = trunc i64 %in to i1
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%sext_i1 = sext i1 %trunc_i1 to i64
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store volatile i64 %sext_i1, i64* @var64
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; CHECK: sbfx {{x[0-9]+}}, {{x[0-9]+}}, #0, #1
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%trunc_i8 = trunc i64 %in to i8
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%sext_i8 = sext i8 %trunc_i8 to i64
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store volatile i64 %sext_i8, i64* @var64
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; CHECK: sxtb {{x[0-9]+}}, {{w[0-9]+}}
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%trunc_i16 = trunc i64 %in to i16
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%sext_i16 = sext i16 %trunc_i16 to i64
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store volatile i64 %sext_i16, i64* @var64
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; CHECK: sxth {{x[0-9]+}}, {{w[0-9]+}}
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%trunc_i32 = trunc i64 %in to i32
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%sext_i32 = sext i32 %trunc_i32 to i64
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store volatile i64 %sext_i32, i64* @var64
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; CHECK: sxtw {{x[0-9]+}}, {{w[0-9]+}}
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ret void
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}
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; These instructions don't actually select to official bitfield
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; operations, but it's important that we select them somehow:
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define void @test_zext_inreg_64(i64 %in) {
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; CHECK-LABEL: test_zext_inreg_64:
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%trunc_i8 = trunc i64 %in to i8
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%zext_i8 = zext i8 %trunc_i8 to i64
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store volatile i64 %zext_i8, i64* @var64
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; CHECK: and {{x[0-9]+}}, {{x[0-9]+}}, #0xff
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%trunc_i16 = trunc i64 %in to i16
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%zext_i16 = zext i16 %trunc_i16 to i64
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store volatile i64 %zext_i16, i64* @var64
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; CHECK: and {{x[0-9]+}}, {{x[0-9]+}}, #0xffff
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%trunc_i32 = trunc i64 %in to i32
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%zext_i32 = zext i32 %trunc_i32 to i64
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store volatile i64 %zext_i32, i64* @var64
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; CHECK: and {{x[0-9]+}}, {{x[0-9]+}}, #0xffffffff
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ret void
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}
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define i64 @test_sext_inreg_from_32(i32 %in) {
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; CHECK-LABEL: test_sext_inreg_from_32:
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%small = trunc i32 %in to i1
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%ext = sext i1 %small to i64
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; Different registers are of course, possible, though suboptimal. This is
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; making sure that a 64-bit "(sext_inreg (anyext GPR32), i1)" uses the 64-bit
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; sbfx rather than just 32-bits.
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; CHECK: sbfx x0, x0, #0, #1
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ret i64 %ext
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}
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define i32 @test_ubfx32(i32* %addr) {
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; CHECK-LABEL: test_ubfx32:
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; CHECK: ubfx {{w[0-9]+}}, {{w[0-9]+}}, #23, #3
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%fields = load i32, i32* %addr
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%shifted = lshr i32 %fields, 23
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%masked = and i32 %shifted, 7
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ret i32 %masked
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}
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define i64 @test_ubfx64(i64* %addr) {
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; CHECK-LABEL: test_ubfx64:
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; CHECK: ubfx {{x[0-9]+}}, {{x[0-9]+}}, #25, #10
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%fields = load i64, i64* %addr
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%shifted = lshr i64 %fields, 25
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%masked = and i64 %shifted, 1023
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ret i64 %masked
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}
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define i32 @test_sbfx32(i32* %addr) {
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; CHECK-LABEL: test_sbfx32:
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; CHECK: sbfx {{w[0-9]+}}, {{w[0-9]+}}, #6, #3
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%fields = load i32, i32* %addr
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%shifted = shl i32 %fields, 23
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%extended = ashr i32 %shifted, 29
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ret i32 %extended
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}
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define i64 @test_sbfx64(i64* %addr) {
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; CHECK-LABEL: test_sbfx64:
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; CHECK: sbfx {{x[0-9]+}}, {{x[0-9]+}}, #0, #63
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%fields = load i64, i64* %addr
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%shifted = shl i64 %fields, 1
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%extended = ashr i64 %shifted, 1
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ret i64 %extended
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}
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