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Imported Upstream version 5.18.0.167
Former-commit-id: 289509151e0fee68a1b591a20c9f109c3c789d3a
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@ -1,14 +0,0 @@
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; RUN: opt < %s -cost-model -analyze -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define void @exts() {
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; VSX is disabled, so this cost needs to include scalarization (because
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; <4 x double> is legalized to scalars).
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; CHECK: cost of 44 {{.*}} fcmp
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%v1 = fcmp ugt <4 x double> undef, undef
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ret void
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}
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@ -1,21 +0,0 @@
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; RUN: opt < %s -cost-model -analyze -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx | FileCheck %s
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define void @exts() {
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; CHECK: cost of 1 {{.*}} sext
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%v1 = sext i16 undef to i32
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; CHECK: cost of 1 {{.*}} sext
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%v2 = sext <2 x i16> undef to <2 x i32>
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; CHECK: cost of 1 {{.*}} sext
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%v3 = sext <4 x i16> undef to <4 x i32>
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; CHECK: cost of 3 {{.*}} sext
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%v4 = sext <8 x i16> undef to <8 x i32>
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ret void
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}
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@ -1,16 +0,0 @@
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; RUN: opt < %s -cost-model -analyze -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define i32 @insert(i32 %arg) {
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; CHECK: cost of 10 {{.*}} insertelement
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%x = insertelement <4 x i32> undef, i32 %arg, i32 0
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ret i32 undef
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}
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define i32 @extract(<4 x i32> %arg) {
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; CHECK: cost of 3 {{.*}} extractelement
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%x = extractelement <4 x i32> %arg, i32 0
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ret i32 %x
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}
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@ -1,3 +0,0 @@
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if not 'PowerPC' in config.root.targets:
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config.unsupported = True
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@ -1,45 +0,0 @@
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; RUN: opt < %s -cost-model -analyze -mtriple=powerpc64-unknown-linux-gnu -mcpu=g5 -disable-ppc-unaligned | FileCheck %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define i32 @stores(i32 %arg) {
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; CHECK: cost of 1 {{.*}} store
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store i8 undef, i8* undef, align 4
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; CHECK: cost of 1 {{.*}} store
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store i16 undef, i16* undef, align 4
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; CHECK: cost of 1 {{.*}} store
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store i32 undef, i32* undef, align 4
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; CHECK: cost of 2 {{.*}} store
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store i64 undef, i64* undef, align 4
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; CHECK: cost of 4 {{.*}} store
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store i128 undef, i128* undef, align 4
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ret i32 undef
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}
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define i32 @loads(i32 %arg) {
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; CHECK: cost of 1 {{.*}} load
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load i8, i8* undef, align 4
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; CHECK: cost of 1 {{.*}} load
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load i16, i16* undef, align 4
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; CHECK: cost of 1 {{.*}} load
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load i32, i32* undef, align 4
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; CHECK: cost of 2 {{.*}} load
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load i64, i64* undef, align 4
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; CHECK: cost of 4 {{.*}} load
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load i128, i128* undef, align 4
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; FIXME: There actually are sub-vector Altivec loads, and so we could handle
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; this with a small expense, but we don't currently.
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; CHECK: cost of 42 {{.*}} load
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load <4 x i16>, <4 x i16>* undef, align 2
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; CHECK: cost of 2 {{.*}} load
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load <4 x i32>, <4 x i32>* undef, align 4
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; CHECK: cost of 46 {{.*}} load
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load <3 x float>, <3 x float>* undef, align 1
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ret i32 undef
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}
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@ -1,11 +0,0 @@
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; RUN: opt < %s -cost-model -analyze -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define <4 x i32> @test1(<4 x i32> %arg) {
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; CHECK: cost of 1 {{.*}} call <4 x i32> @llvm.ctpop.v4i32
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%ctpop = call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %arg)
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ret <4 x i32> %ctpop
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}
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declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>)
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@ -1,404 +0,0 @@
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; RUN: opt < %s -cost-model -analyze | FileCheck %s
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define <16 x i8> @test_l_v16i8(<16 x i8>* %p) #0 {
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entry:
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%r = load <16 x i8>, <16 x i8>* %p, align 1
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ret <16 x i8> %r
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; CHECK-LABEL: test_l_v16i8
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; CHECK: cost of 2 for instruction: %r = load <16 x i8>, <16 x i8>* %p, align 1
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}
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define <32 x i8> @test_l_v32i8(<32 x i8>* %p) #0 {
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entry:
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%r = load <32 x i8>, <32 x i8>* %p, align 1
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ret <32 x i8> %r
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; CHECK-LABEL: test_l_v32i8
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; CHECK: cost of 4 for instruction: %r = load <32 x i8>, <32 x i8>* %p, align 1
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}
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define <8 x i16> @test_l_v8i16(<8 x i16>* %p) #0 {
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entry:
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%r = load <8 x i16>, <8 x i16>* %p, align 2
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ret <8 x i16> %r
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; CHECK-LABEL: test_l_v8i16
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; CHECK: cost of 2 for instruction: %r = load <8 x i16>, <8 x i16>* %p, align 2
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}
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define <16 x i16> @test_l_v16i16(<16 x i16>* %p) #0 {
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entry:
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%r = load <16 x i16>, <16 x i16>* %p, align 2
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ret <16 x i16> %r
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; CHECK-LABEL: test_l_v16i16
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; CHECK: cost of 4 for instruction: %r = load <16 x i16>, <16 x i16>* %p, align 2
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}
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define <4 x i32> @test_l_v4i32(<4 x i32>* %p) #0 {
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entry:
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%r = load <4 x i32>, <4 x i32>* %p, align 4
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ret <4 x i32> %r
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; CHECK-LABEL: test_l_v4i32
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; CHECK: cost of 2 for instruction: %r = load <4 x i32>, <4 x i32>* %p, align 4
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}
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define <8 x i32> @test_l_v8i32(<8 x i32>* %p) #0 {
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entry:
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%r = load <8 x i32>, <8 x i32>* %p, align 4
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ret <8 x i32> %r
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; CHECK-LABEL: test_l_v8i32
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; CHECK: cost of 4 for instruction: %r = load <8 x i32>, <8 x i32>* %p, align 4
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}
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define <2 x i64> @test_l_v2i64(<2 x i64>* %p) #0 {
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entry:
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%r = load <2 x i64>, <2 x i64>* %p, align 8
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ret <2 x i64> %r
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; CHECK-LABEL: test_l_v2i64
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; CHECK: cost of 1 for instruction: %r = load <2 x i64>, <2 x i64>* %p, align 8
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}
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define <4 x i64> @test_l_v4i64(<4 x i64>* %p) #0 {
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entry:
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%r = load <4 x i64>, <4 x i64>* %p, align 8
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ret <4 x i64> %r
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; CHECK-LABEL: test_l_v4i64
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; CHECK: cost of 2 for instruction: %r = load <4 x i64>, <4 x i64>* %p, align 8
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}
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define <4 x float> @test_l_v4float(<4 x float>* %p) #0 {
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entry:
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%r = load <4 x float>, <4 x float>* %p, align 4
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ret <4 x float> %r
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; CHECK-LABEL: test_l_v4float
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; CHECK: cost of 2 for instruction: %r = load <4 x float>, <4 x float>* %p, align 4
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}
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define <8 x float> @test_l_v8float(<8 x float>* %p) #0 {
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entry:
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%r = load <8 x float>, <8 x float>* %p, align 4
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ret <8 x float> %r
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; CHECK-LABEL: test_l_v8float
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; CHECK: cost of 4 for instruction: %r = load <8 x float>, <8 x float>* %p, align 4
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}
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define <2 x double> @test_l_v2double(<2 x double>* %p) #0 {
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entry:
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%r = load <2 x double>, <2 x double>* %p, align 8
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ret <2 x double> %r
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; CHECK-LABEL: test_l_v2double
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; CHECK: cost of 1 for instruction: %r = load <2 x double>, <2 x double>* %p, align 8
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}
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define <4 x double> @test_l_v4double(<4 x double>* %p) #0 {
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entry:
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%r = load <4 x double>, <4 x double>* %p, align 8
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ret <4 x double> %r
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; CHECK-LABEL: test_l_v4double
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; CHECK: cost of 2 for instruction: %r = load <4 x double>, <4 x double>* %p, align 8
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}
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define <16 x i8> @test_l_p8v16i8(<16 x i8>* %p) #2 {
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entry:
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%r = load <16 x i8>, <16 x i8>* %p, align 1
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ret <16 x i8> %r
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; CHECK-LABEL: test_l_p8v16i8
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; CHECK: cost of 1 for instruction: %r = load <16 x i8>, <16 x i8>* %p, align 1
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}
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define <32 x i8> @test_l_p8v32i8(<32 x i8>* %p) #2 {
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entry:
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%r = load <32 x i8>, <32 x i8>* %p, align 1
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ret <32 x i8> %r
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; CHECK-LABEL: test_l_p8v32i8
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; CHECK: cost of 2 for instruction: %r = load <32 x i8>, <32 x i8>* %p, align 1
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}
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define <8 x i16> @test_l_p8v8i16(<8 x i16>* %p) #2 {
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entry:
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%r = load <8 x i16>, <8 x i16>* %p, align 2
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ret <8 x i16> %r
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; CHECK-LABEL: test_l_p8v8i16
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; CHECK: cost of 1 for instruction: %r = load <8 x i16>, <8 x i16>* %p, align 2
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}
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define <16 x i16> @test_l_p8v16i16(<16 x i16>* %p) #2 {
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entry:
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%r = load <16 x i16>, <16 x i16>* %p, align 2
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ret <16 x i16> %r
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; CHECK-LABEL: test_l_p8v16i16
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; CHECK: cost of 2 for instruction: %r = load <16 x i16>, <16 x i16>* %p, align 2
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}
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define <4 x i32> @test_l_p8v4i32(<4 x i32>* %p) #2 {
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entry:
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%r = load <4 x i32>, <4 x i32>* %p, align 4
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ret <4 x i32> %r
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; CHECK-LABEL: test_l_p8v4i32
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; CHECK: cost of 1 for instruction: %r = load <4 x i32>, <4 x i32>* %p, align 4
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}
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define <8 x i32> @test_l_p8v8i32(<8 x i32>* %p) #2 {
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entry:
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%r = load <8 x i32>, <8 x i32>* %p, align 4
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ret <8 x i32> %r
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; CHECK-LABEL: test_l_p8v8i32
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; CHECK: cost of 2 for instruction: %r = load <8 x i32>, <8 x i32>* %p, align 4
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}
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define <2 x i64> @test_l_p8v2i64(<2 x i64>* %p) #2 {
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entry:
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%r = load <2 x i64>, <2 x i64>* %p, align 8
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ret <2 x i64> %r
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; CHECK-LABEL: test_l_p8v2i64
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; CHECK: cost of 1 for instruction: %r = load <2 x i64>, <2 x i64>* %p, align 8
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}
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define <4 x i64> @test_l_p8v4i64(<4 x i64>* %p) #2 {
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entry:
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%r = load <4 x i64>, <4 x i64>* %p, align 8
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ret <4 x i64> %r
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; CHECK-LABEL: test_l_p8v4i64
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; CHECK: cost of 2 for instruction: %r = load <4 x i64>, <4 x i64>* %p, align 8
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}
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define <4 x float> @test_l_p8v4float(<4 x float>* %p) #2 {
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entry:
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%r = load <4 x float>, <4 x float>* %p, align 4
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ret <4 x float> %r
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; CHECK-LABEL: test_l_p8v4float
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; CHECK: cost of 1 for instruction: %r = load <4 x float>, <4 x float>* %p, align 4
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}
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define <8 x float> @test_l_p8v8float(<8 x float>* %p) #2 {
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entry:
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%r = load <8 x float>, <8 x float>* %p, align 4
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ret <8 x float> %r
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; CHECK-LABEL: test_l_p8v8float
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; CHECK: cost of 2 for instruction: %r = load <8 x float>, <8 x float>* %p, align 4
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}
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define <2 x double> @test_l_p8v2double(<2 x double>* %p) #2 {
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entry:
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%r = load <2 x double>, <2 x double>* %p, align 8
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ret <2 x double> %r
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; CHECK-LABEL: test_l_p8v2double
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; CHECK: cost of 1 for instruction: %r = load <2 x double>, <2 x double>* %p, align 8
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}
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define <4 x double> @test_l_p8v4double(<4 x double>* %p) #2 {
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entry:
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%r = load <4 x double>, <4 x double>* %p, align 8
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ret <4 x double> %r
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; CHECK-LABEL: test_l_p8v4double
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; CHECK: cost of 2 for instruction: %r = load <4 x double>, <4 x double>* %p, align 8
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}
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define <4 x float> @test_l_qv4float(<4 x float>* %p) #1 {
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entry:
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%r = load <4 x float>, <4 x float>* %p, align 4
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ret <4 x float> %r
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; CHECK-LABEL: test_l_qv4float
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; CHECK: cost of 2 for instruction: %r = load <4 x float>, <4 x float>* %p, align 4
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}
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define <8 x float> @test_l_qv8float(<8 x float>* %p) #1 {
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entry:
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%r = load <8 x float>, <8 x float>* %p, align 4
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ret <8 x float> %r
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; CHECK-LABEL: test_l_qv8float
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; CHECK: cost of 4 for instruction: %r = load <8 x float>, <8 x float>* %p, align 4
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}
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define <4 x double> @test_l_qv4double(<4 x double>* %p) #1 {
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entry:
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%r = load <4 x double>, <4 x double>* %p, align 8
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ret <4 x double> %r
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; CHECK-LABEL: test_l_qv4double
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; CHECK: cost of 2 for instruction: %r = load <4 x double>, <4 x double>* %p, align 8
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}
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define <8 x double> @test_l_qv8double(<8 x double>* %p) #1 {
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entry:
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%r = load <8 x double>, <8 x double>* %p, align 8
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ret <8 x double> %r
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; CHECK-LABEL: test_l_qv8double
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; CHECK: cost of 4 for instruction: %r = load <8 x double>, <8 x double>* %p, align 8
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}
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define void @test_s_v16i8(<16 x i8>* %p, <16 x i8> %v) #0 {
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entry:
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store <16 x i8> %v, <16 x i8>* %p, align 1
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ret void
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; CHECK-LABEL: test_s_v16i8
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; CHECK: cost of 1 for instruction: store <16 x i8> %v, <16 x i8>* %p, align 1
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}
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define void @test_s_v32i8(<32 x i8>* %p, <32 x i8> %v) #0 {
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entry:
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store <32 x i8> %v, <32 x i8>* %p, align 1
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ret void
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; CHECK-LABEL: test_s_v32i8
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; CHECK: cost of 2 for instruction: store <32 x i8> %v, <32 x i8>* %p, align 1
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}
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define void @test_s_v8i16(<8 x i16>* %p, <8 x i16> %v) #0 {
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entry:
|
||||
store <8 x i16> %v, <8 x i16>* %p, align 2
|
||||
ret void
|
||||
|
||||
; CHECK-LABEL: test_s_v8i16
|
||||
; CHECK: cost of 1 for instruction: store <8 x i16> %v, <8 x i16>* %p, align 2
|
||||
}
|
||||
|
||||
define void @test_s_v16i16(<16 x i16>* %p, <16 x i16> %v) #0 {
|
||||
entry:
|
||||
store <16 x i16> %v, <16 x i16>* %p, align 2
|
||||
ret void
|
||||
|
||||
; CHECK-LABEL: test_s_v16i16
|
||||
; CHECK: cost of 2 for instruction: store <16 x i16> %v, <16 x i16>* %p, align 2
|
||||
}
|
||||
|
||||
define void @test_s_v4i32(<4 x i32>* %p, <4 x i32> %v) #0 {
|
||||
entry:
|
||||
store <4 x i32> %v, <4 x i32>* %p, align 4
|
||||
ret void
|
||||
|
||||
; CHECK-LABEL: test_s_v4i32
|
||||
; CHECK: cost of 1 for instruction: store <4 x i32> %v, <4 x i32>* %p, align 4
|
||||
}
|
||||
|
||||
define void @test_s_v8i32(<8 x i32>* %p, <8 x i32> %v) #0 {
|
||||
entry:
|
||||
store <8 x i32> %v, <8 x i32>* %p, align 4
|
||||
ret void
|
||||
|
||||
; CHECK-LABEL: test_s_v8i32
|
||||
; CHECK: cost of 2 for instruction: store <8 x i32> %v, <8 x i32>* %p, align 4
|
||||
}
|
||||
|
||||
define void @test_s_v2i64(<2 x i64>* %p, <2 x i64> %v) #0 {
|
||||
entry:
|
||||
store <2 x i64> %v, <2 x i64>* %p, align 8
|
||||
ret void
|
||||
|
||||
; CHECK-LABEL: test_s_v2i64
|
||||
; CHECK: cost of 1 for instruction: store <2 x i64> %v, <2 x i64>* %p, align 8
|
||||
}
|
||||
|
||||
define void @test_s_v4i64(<4 x i64>* %p, <4 x i64> %v) #0 {
|
||||
entry:
|
||||
store <4 x i64> %v, <4 x i64>* %p, align 8
|
||||
ret void
|
||||
|
||||
; CHECK-LABEL: test_s_v4i64
|
||||
; CHECK: cost of 2 for instruction: store <4 x i64> %v, <4 x i64>* %p, align 8
|
||||
}
|
||||
|
||||
define void @test_s_v4float(<4 x float>* %p, <4 x float> %v) #0 {
|
||||
entry:
|
||||
store <4 x float> %v, <4 x float>* %p, align 4
|
||||
ret void
|
||||
|
||||
; CHECK-LABEL: test_s_v4float
|
||||
; CHECK: cost of 1 for instruction: store <4 x float> %v, <4 x float>* %p, align 4
|
||||
}
|
||||
|
||||
define void @test_s_v8float(<8 x float>* %p, <8 x float> %v) #0 {
|
||||
entry:
|
||||
store <8 x float> %v, <8 x float>* %p, align 4
|
||||
ret void
|
||||
|
||||
; CHECK-LABEL: test_s_v8float
|
||||
; CHECK: cost of 2 for instruction: store <8 x float> %v, <8 x float>* %p, align 4
|
||||
}
|
||||
|
||||
define void @test_s_v2double(<2 x double>* %p, <2 x double> %v) #0 {
|
||||
entry:
|
||||
store <2 x double> %v, <2 x double>* %p, align 8
|
||||
ret void
|
||||
|
||||
; CHECK-LABEL: test_s_v2double
|
||||
; CHECK: cost of 1 for instruction: store <2 x double> %v, <2 x double>* %p, align 8
|
||||
}
|
||||
|
||||
define void @test_s_v4double(<4 x double>* %p, <4 x double> %v) #0 {
|
||||
entry:
|
||||
store <4 x double> %v, <4 x double>* %p, align 8
|
||||
ret void
|
||||
|
||||
; CHECK-LABEL: test_s_v4double
|
||||
; CHECK: cost of 2 for instruction: store <4 x double> %v, <4 x double>* %p, align 8
|
||||
}
|
||||
|
||||
define void @test_s_qv4float(<4 x float>* %p, <4 x float> %v) #1 {
|
||||
entry:
|
||||
store <4 x float> %v, <4 x float>* %p, align 4
|
||||
ret void
|
||||
|
||||
; CHECK-LABEL: test_s_qv4float
|
||||
; CHECK: cost of 7 for instruction: store <4 x float> %v, <4 x float>* %p, align 4
|
||||
}
|
||||
|
||||
define void @test_s_qv8float(<8 x float>* %p, <8 x float> %v) #1 {
|
||||
entry:
|
||||
store <8 x float> %v, <8 x float>* %p, align 4
|
||||
ret void
|
||||
|
||||
; CHECK-LABEL: test_s_qv8float
|
||||
; CHECK: cost of 15 for instruction: store <8 x float> %v, <8 x float>* %p, align 4
|
||||
}
|
||||
|
||||
define void @test_s_qv4double(<4 x double>* %p, <4 x double> %v) #1 {
|
||||
entry:
|
||||
store <4 x double> %v, <4 x double>* %p, align 8
|
||||
ret void
|
||||
|
||||
; CHECK-LABEL: test_s_qv4double
|
||||
; CHECK: cost of 7 for instruction: store <4 x double> %v, <4 x double>* %p, align 8
|
||||
}
|
||||
|
||||
define void @test_s_qv8double(<8 x double>* %p, <8 x double> %v) #1 {
|
||||
entry:
|
||||
store <8 x double> %v, <8 x double>* %p, align 8
|
||||
ret void
|
||||
|
||||
; CHECK-LABEL: test_s_qv8double
|
||||
; CHECK: cost of 15 for instruction: store <8 x double> %v, <8 x double>* %p, align 8
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind "target-cpu"="pwr7" }
|
||||
attributes #1 = { nounwind "target-cpu"="a2q" }
|
||||
attributes #2 = { nounwind "target-cpu"="pwr8" }
|
||||
|
||||
@ -1,26 +0,0 @@
|
||||
; RUN: opt < %s -cost-model -analyze -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=+vsx | FileCheck %s
|
||||
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
|
||||
target triple = "powerpc64-unknown-linux-gnu"
|
||||
|
||||
define i32 @test(i32 %arg) {
|
||||
|
||||
; CHECK: cost of 1 {{.*}} load
|
||||
load i8, i8* undef, align 1
|
||||
; CHECK: cost of 1 {{.*}} load
|
||||
load i16, i16* undef, align 1
|
||||
; CHECK: cost of 1 {{.*}} load
|
||||
load i32, i32* undef, align 1
|
||||
; CHECK: cost of 1 {{.*}} load
|
||||
load i64, i64* undef, align 1
|
||||
|
||||
; CHECK: cost of 1 {{.*}} store
|
||||
store i8 undef, i8* undef, align 1
|
||||
; CHECK: cost of 1 {{.*}} store
|
||||
store i16 undef, i16* undef, align 1
|
||||
; CHECK: cost of 1 {{.*}} store
|
||||
store i32 undef, i32* undef, align 1
|
||||
; CHECK: cost of 1 {{.*}} store
|
||||
store i64 undef, i64* undef, align 1
|
||||
|
||||
ret i32 undef
|
||||
}
|
||||
@ -1,19 +0,0 @@
|
||||
; RUN: opt < %s -cost-model -analyze -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=+vsx | FileCheck %s
|
||||
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
|
||||
target triple = "powerpc64-unknown-linux-gnu"
|
||||
|
||||
define i32 @loads(i32 %arg) {
|
||||
; CHECK: cost of 1 {{.*}} load
|
||||
load <4 x i8>, <4 x i8>* undef, align 1
|
||||
|
||||
; CHECK: cost of 1 {{.*}} load
|
||||
load <8 x i8>, <8 x i8>* undef, align 1
|
||||
|
||||
; CHECK: cost of 1 {{.*}} load
|
||||
load <2 x i16>, <2 x i16>* undef, align 2
|
||||
|
||||
; CHECK: cost of 1 {{.*}} load
|
||||
load <4 x i16>, <4 x i16>* undef, align 2
|
||||
|
||||
ret i32 undef
|
||||
}
|
||||
Reference in New Issue
Block a user