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//===-- WebAssemblyStoreResults.cpp - Optimize using store result values --===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// \brief This file implements an optimization pass using store result values.
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///
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/// WebAssembly's store instructions return the stored value. This is to enable
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/// an optimization wherein uses of the stored value can be replaced by uses of
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/// the store's result value, making the stored value register more likely to
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/// be single-use, thus more likely to be useful to register stackifying, and
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/// potentially also exposing the store to register stackifying. These both can
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/// reduce get_local/set_local traffic.
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///
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/// This pass also performs this optimization for memcpy, memmove, and memset
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/// calls, since the LLVM intrinsics for these return void so they can't use the
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/// returned attribute and consequently aren't handled by the OptimizeReturned
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/// pass.
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///
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
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#include "WebAssembly.h"
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#include "WebAssemblyMachineFunctionInfo.h"
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#include "WebAssemblySubtarget.h"
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#include "llvm/Analysis/TargetLibraryInfo.h"
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#include "llvm/CodeGen/LiveIntervals.h"
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#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "wasm-store-results"
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namespace {
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class WebAssemblyStoreResults final : public MachineFunctionPass {
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public:
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static char ID; // Pass identification, replacement for typeid
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WebAssemblyStoreResults() : MachineFunctionPass(ID) {}
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StringRef getPassName() const override { return "WebAssembly Store Results"; }
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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AU.addRequired<MachineBlockFrequencyInfo>();
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AU.addPreserved<MachineBlockFrequencyInfo>();
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AU.addRequired<MachineDominatorTree>();
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AU.addPreserved<MachineDominatorTree>();
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AU.addRequired<LiveIntervals>();
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AU.addPreserved<SlotIndexes>();
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AU.addPreserved<LiveIntervals>();
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AU.addRequired<TargetLibraryInfoWrapperPass>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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private:
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};
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} // end anonymous namespace
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char WebAssemblyStoreResults::ID = 0;
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FunctionPass *llvm::createWebAssemblyStoreResults() {
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return new WebAssemblyStoreResults();
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}
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// Replace uses of FromReg with ToReg if they are dominated by MI.
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static bool ReplaceDominatedUses(MachineBasicBlock &MBB, MachineInstr &MI,
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unsigned FromReg, unsigned ToReg,
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const MachineRegisterInfo &MRI,
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MachineDominatorTree &MDT,
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LiveIntervals &LIS) {
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bool Changed = false;
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LiveInterval *FromLI = &LIS.getInterval(FromReg);
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LiveInterval *ToLI = &LIS.getInterval(ToReg);
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SlotIndex FromIdx = LIS.getInstructionIndex(MI).getRegSlot();
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VNInfo *FromVNI = FromLI->getVNInfoAt(FromIdx);
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SmallVector<SlotIndex, 4> Indices;
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for (auto I = MRI.use_nodbg_begin(FromReg), E = MRI.use_nodbg_end(); I != E;) {
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MachineOperand &O = *I++;
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MachineInstr *Where = O.getParent();
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// Check that MI dominates the instruction in the normal way.
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if (&MI == Where || !MDT.dominates(&MI, Where))
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continue;
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// If this use gets a different value, skip it.
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SlotIndex WhereIdx = LIS.getInstructionIndex(*Where);
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VNInfo *WhereVNI = FromLI->getVNInfoAt(WhereIdx);
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if (WhereVNI && WhereVNI != FromVNI)
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continue;
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// Make sure ToReg isn't clobbered before it gets there.
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VNInfo *ToVNI = ToLI->getVNInfoAt(WhereIdx);
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if (ToVNI && ToVNI != FromVNI)
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continue;
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Changed = true;
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DEBUG(dbgs() << "Setting operand " << O << " in " << *Where << " from "
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<< MI << "\n");
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O.setReg(ToReg);
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// If the store's def was previously dead, it is no longer.
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if (!O.isUndef()) {
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MI.getOperand(0).setIsDead(false);
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Indices.push_back(WhereIdx.getRegSlot());
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}
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}
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if (Changed) {
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// Extend ToReg's liveness.
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LIS.extendToIndices(*ToLI, Indices);
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// Shrink FromReg's liveness.
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LIS.shrinkToUses(FromLI);
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// If we replaced all dominated uses, FromReg is now killed at MI.
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if (!FromLI->liveAt(FromIdx.getDeadSlot()))
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MI.addRegisterKilled(FromReg,
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MBB.getParent()->getSubtarget<WebAssemblySubtarget>()
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.getRegisterInfo());
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}
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return Changed;
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}
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static bool optimizeCall(MachineBasicBlock &MBB, MachineInstr &MI,
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const MachineRegisterInfo &MRI,
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MachineDominatorTree &MDT,
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LiveIntervals &LIS,
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const WebAssemblyTargetLowering &TLI,
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const TargetLibraryInfo &LibInfo) {
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MachineOperand &Op1 = MI.getOperand(1);
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if (!Op1.isSymbol())
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return false;
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StringRef Name(Op1.getSymbolName());
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bool callReturnsInput = Name == TLI.getLibcallName(RTLIB::MEMCPY) ||
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Name == TLI.getLibcallName(RTLIB::MEMMOVE) ||
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Name == TLI.getLibcallName(RTLIB::MEMSET);
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if (!callReturnsInput)
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return false;
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LibFunc Func;
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if (!LibInfo.getLibFunc(Name, Func))
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return false;
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unsigned FromReg = MI.getOperand(2).getReg();
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unsigned ToReg = MI.getOperand(0).getReg();
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if (MRI.getRegClass(FromReg) != MRI.getRegClass(ToReg))
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report_fatal_error("Store results: call to builtin function with wrong "
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"signature, from/to mismatch");
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return ReplaceDominatedUses(MBB, MI, FromReg, ToReg, MRI, MDT, LIS);
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}
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bool WebAssemblyStoreResults::runOnMachineFunction(MachineFunction &MF) {
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DEBUG({
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dbgs() << "********** Store Results **********\n"
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<< "********** Function: " << MF.getName() << '\n';
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});
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MachineRegisterInfo &MRI = MF.getRegInfo();
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MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
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const WebAssemblyTargetLowering &TLI =
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*MF.getSubtarget<WebAssemblySubtarget>().getTargetLowering();
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const auto &LibInfo = getAnalysis<TargetLibraryInfoWrapperPass>().getTLI();
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LiveIntervals &LIS = getAnalysis<LiveIntervals>();
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bool Changed = false;
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// We don't preserve SSA form.
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MRI.leaveSSA();
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assert(MRI.tracksLiveness() && "StoreResults expects liveness tracking");
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for (auto &MBB : MF) {
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DEBUG(dbgs() << "Basic Block: " << MBB.getName() << '\n');
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for (auto &MI : MBB)
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switch (MI.getOpcode()) {
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default:
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break;
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case WebAssembly::CALL_I32:
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case WebAssembly::CALL_I64:
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Changed |= optimizeCall(MBB, MI, MRI, MDT, LIS, TLI, LibInfo);
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break;
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}
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}
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return Changed;
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}
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