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Imported Upstream version 5.18.0.167

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Former-commit-id: 289509151e0fee68a1b591a20c9f109c3c789d3a
This commit is contained in:
Xamarin Public Jenkins (auto-signing)
2018-10-20 08:25:10 +00:00
parent e19d552987
commit b084638f15
28489 changed files with 184 additions and 3866856 deletions
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7
external/llvm/lib/Target/SystemZ/MCTargetDesc/CMakeLists.txt vendored
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@ -1,7 +0,0 @@
add_llvm_library(LLVMSystemZDesc
SystemZMCAsmBackend.cpp
SystemZMCAsmInfo.cpp
SystemZMCCodeEmitter.cpp
SystemZMCObjectWriter.cpp
SystemZMCTargetDesc.cpp
)

23
external/llvm/lib/Target/SystemZ/MCTargetDesc/LLVMBuild.txt vendored
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@ -1,23 +0,0 @@
;===- ./lib/Target/SystemZ/MCTargetDesc/LLVMBuild.txt ----------*- Conf -*--===;
;
; The LLVM Compiler Infrastructure
;
; This file is distributed under the University of Illinois Open Source
; License. See LICENSE.TXT for details.
;
;===------------------------------------------------------------------------===;
;
; This is an LLVMBuild description file for the components in this subdirectory.
;
; For more information on the LLVMBuild system, please see:
;
; http://llvm.org/docs/LLVMBuild.html
;
;===------------------------------------------------------------------------===;
[component_0]
type = Library
name = SystemZDesc
parent = SystemZ
required_libraries = MC Support SystemZAsmPrinter SystemZInfo
add_to_library_groups = SystemZ

132
external/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp vendored
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//===-- SystemZMCAsmBackend.cpp - SystemZ assembler backend ---------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
#include "MCTargetDesc/SystemZMCFixups.h"
#include "MCTargetDesc/SystemZMCTargetDesc.h"
#include "llvm/MC/MCAsmBackend.h"
#include "llvm/MC/MCELFObjectWriter.h"
#include "llvm/MC/MCFixupKindInfo.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCObjectWriter.h"
#include "llvm/MC/MCSubtargetInfo.h"
using namespace llvm;
// Value is a fully-resolved relocation value: Symbol + Addend [- Pivot].
// Return the bits that should be installed in a relocation field for
// fixup kind Kind.
static uint64_t extractBitsForFixup(MCFixupKind Kind, uint64_t Value) {
if (Kind < FirstTargetFixupKind)
return Value;
switch (unsigned(Kind)) {
case SystemZ::FK_390_PC12DBL:
case SystemZ::FK_390_PC16DBL:
case SystemZ::FK_390_PC24DBL:
case SystemZ::FK_390_PC32DBL:
return (int64_t)Value / 2;
case SystemZ::FK_390_TLS_CALL:
return 0;
}
llvm_unreachable("Unknown fixup kind!");
}
namespace {
class SystemZMCAsmBackend : public MCAsmBackend {
uint8_t OSABI;
public:
SystemZMCAsmBackend(uint8_t osABI)
: OSABI(osABI) {}
// Override MCAsmBackend
unsigned getNumFixupKinds() const override {
return SystemZ::NumTargetFixupKinds;
}
const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
const MCValue &Target, MutableArrayRef<char> Data,
uint64_t Value, bool IsResolved) const override;
bool mayNeedRelaxation(const MCInst &Inst) const override {
return false;
}
bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
const MCRelaxableFragment *Fragment,
const MCAsmLayout &Layout) const override {
return false;
}
void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
MCInst &Res) const override {
llvm_unreachable("SystemZ does do not have assembler relaxation");
}
bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
std::unique_ptr<MCObjectWriter>
createObjectWriter(raw_pwrite_stream &OS) const override {
return createSystemZObjectWriter(OS, OSABI);
}
};
} // end anonymous namespace
const MCFixupKindInfo &
SystemZMCAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
const static MCFixupKindInfo Infos[SystemZ::NumTargetFixupKinds] = {
{ "FK_390_PC12DBL", 4, 12, MCFixupKindInfo::FKF_IsPCRel },
{ "FK_390_PC16DBL", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
{ "FK_390_PC24DBL", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
{ "FK_390_PC32DBL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
{ "FK_390_TLS_CALL", 0, 0, 0 }
};
if (Kind < FirstTargetFixupKind)
return MCAsmBackend::getFixupKindInfo(Kind);
assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
"Invalid kind!");
return Infos[Kind - FirstTargetFixupKind];
}
void SystemZMCAsmBackend::applyFixup(const MCAssembler &Asm,
const MCFixup &Fixup,
const MCValue &Target,
MutableArrayRef<char> Data, uint64_t Value,
bool IsResolved) const {
MCFixupKind Kind = Fixup.getKind();
unsigned Offset = Fixup.getOffset();
unsigned BitSize = getFixupKindInfo(Kind).TargetSize;
unsigned Size = (BitSize + 7) / 8;
assert(Offset + Size <= Data.size() && "Invalid fixup offset!");
// Big-endian insertion of Size bytes.
Value = extractBitsForFixup(Kind, Value);
if (BitSize < 64)
Value &= ((uint64_t)1 << BitSize) - 1;
unsigned ShiftValue = (Size * 8) - 8;
for (unsigned I = 0; I != Size; ++I) {
Data[Offset + I] |= uint8_t(Value >> ShiftValue);
ShiftValue -= 8;
}
}
bool SystemZMCAsmBackend::writeNopData(uint64_t Count,
MCObjectWriter *OW) const {
for (uint64_t I = 0; I != Count; ++I)
OW->write8(7);
return true;
}
MCAsmBackend *llvm::createSystemZMCAsmBackend(const Target &T,
const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI,
const MCTargetOptions &Options) {
uint8_t OSABI =
MCELFObjectTargetWriter::getOSABI(STI.getTargetTriple().getOS());
return new SystemZMCAsmBackend(OSABI);
}

29
external/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.cpp vendored
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//===-- SystemZMCAsmInfo.cpp - SystemZ asm properties ---------------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
#include "SystemZMCAsmInfo.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCSectionELF.h"
using namespace llvm;
SystemZMCAsmInfo::SystemZMCAsmInfo(const Triple &TT) {
CodePointerSize = 8;
CalleeSaveStackSlotSize = 8;
IsLittleEndian = false;
CommentString = "#";
ZeroDirective = "\t.space\t";
Data64bitsDirective = "\t.quad\t";
UsesELFSectionDirectiveForBSS = true;
SupportsDebugInformation = true;
ExceptionsType = ExceptionHandling::DwarfCFI;
UseIntegratedAssembler = true;
}

26
external/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.h vendored
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//====-- SystemZMCAsmInfo.h - SystemZ asm properties -----------*- C++ -*--===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCASMINFO_H
#define LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCASMINFO_H
#include "llvm/MC/MCAsmInfoELF.h"
#include "llvm/Support/Compiler.h"
namespace llvm {
class Triple;
class SystemZMCAsmInfo : public MCAsmInfoELF {
public:
explicit SystemZMCAsmInfo(const Triple &TT);
};
} // end namespace llvm
#endif

307
external/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp vendored
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@ -1,307 +0,0 @@
//===-- SystemZMCCodeEmitter.cpp - Convert SystemZ code to machine code ---===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file implements the SystemZMCCodeEmitter class.
//
//===----------------------------------------------------------------------===//
#include "MCTargetDesc/SystemZMCFixups.h"
#include "MCTargetDesc/SystemZMCTargetDesc.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/MC/MCCodeEmitter.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCFixup.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include <cassert>
#include <cstdint>
using namespace llvm;
#define DEBUG_TYPE "mccodeemitter"
namespace {
class SystemZMCCodeEmitter : public MCCodeEmitter {
const MCInstrInfo &MCII;
MCContext &Ctx;
public:
SystemZMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
: MCII(mcii), Ctx(ctx) {
}
~SystemZMCCodeEmitter() override = default;
// OVerride MCCodeEmitter.
void encodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const override;
private:
// Automatically generated by TableGen.
uint64_t getBinaryCodeForInstr(const MCInst &MI,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
// Called by the TableGen code to get the binary encoding of operand
// MO in MI. Fixups is the list of fixups against MI.
uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
// Called by the TableGen code to get the binary encoding of an address.
// The index or length, if any, is encoded first, followed by the base,
// followed by the displacement. In a 20-bit displacement,
// the low 12 bits are encoded before the high 8 bits.
uint64_t getBDAddr12Encoding(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
uint64_t getBDAddr20Encoding(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
uint64_t getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
uint64_t getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
uint64_t getBDLAddr12Len4Encoding(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
uint64_t getBDLAddr12Len8Encoding(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
uint64_t getBDRAddr12Encoding(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
uint64_t getBDVAddr12Encoding(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
// Operand OpNum of MI needs a PC-relative fixup of kind Kind at
// Offset bytes from the start of MI. Add the fixup to Fixups
// and return the in-place addend, which since we're a RELA target
// is always 0. If AllowTLS is true and optional operand OpNum + 1
// is present, also emit a TLS call fixup for it.
uint64_t getPCRelEncoding(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups,
unsigned Kind, int64_t Offset,
bool AllowTLS) const;
uint64_t getPC16DBLEncoding(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
return getPCRelEncoding(MI, OpNum, Fixups,
SystemZ::FK_390_PC16DBL, 2, false);
}
uint64_t getPC32DBLEncoding(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
return getPCRelEncoding(MI, OpNum, Fixups,
SystemZ::FK_390_PC32DBL, 2, false);
}
uint64_t getPC16DBLTLSEncoding(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
return getPCRelEncoding(MI, OpNum, Fixups,
SystemZ::FK_390_PC16DBL, 2, true);
}
uint64_t getPC32DBLTLSEncoding(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
return getPCRelEncoding(MI, OpNum, Fixups,
SystemZ::FK_390_PC32DBL, 2, true);
}
uint64_t getPC12DBLBPPEncoding(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
return getPCRelEncoding(MI, OpNum, Fixups,
SystemZ::FK_390_PC12DBL, 1, false);
}
uint64_t getPC16DBLBPPEncoding(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
return getPCRelEncoding(MI, OpNum, Fixups,
SystemZ::FK_390_PC16DBL, 4, false);
}
uint64_t getPC24DBLBPPEncoding(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
return getPCRelEncoding(MI, OpNum, Fixups,
SystemZ::FK_390_PC24DBL, 3, false);
}
private:
uint64_t computeAvailableFeatures(const FeatureBitset &FB) const;
void verifyInstructionPredicates(const MCInst &MI,
uint64_t AvailableFeatures) const;
};
} // end anonymous namespace
void SystemZMCCodeEmitter::
encodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
verifyInstructionPredicates(MI,
computeAvailableFeatures(STI.getFeatureBits()));
uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
unsigned Size = MCII.get(MI.getOpcode()).getSize();
// Big-endian insertion of Size bytes.
unsigned ShiftValue = (Size * 8) - 8;
for (unsigned I = 0; I != Size; ++I) {
OS << uint8_t(Bits >> ShiftValue);
ShiftValue -= 8;
}
}
uint64_t SystemZMCCodeEmitter::
getMachineOpValue(const MCInst &MI, const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
if (MO.isReg())
return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
if (MO.isImm())
return static_cast<uint64_t>(MO.getImm());
llvm_unreachable("Unexpected operand type!");
}
uint64_t SystemZMCCodeEmitter::
getBDAddr12Encoding(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI);
uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI);
assert(isUInt<4>(Base) && isUInt<12>(Disp));
return (Base << 12) | Disp;
}
uint64_t SystemZMCCodeEmitter::
getBDAddr20Encoding(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI);
uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI);
assert(isUInt<4>(Base) && isInt<20>(Disp));
return (Base << 20) | ((Disp & 0xfff) << 8) | ((Disp & 0xff000) >> 12);
}
uint64_t SystemZMCCodeEmitter::
getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI);
uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI);
uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI);
assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Index));
return (Index << 16) | (Base << 12) | Disp;
}
uint64_t SystemZMCCodeEmitter::
getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI);
uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI);
uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI);
assert(isUInt<4>(Base) && isInt<20>(Disp) && isUInt<4>(Index));
return (Index << 24) | (Base << 20) | ((Disp & 0xfff) << 8)
| ((Disp & 0xff000) >> 12);
}
uint64_t SystemZMCCodeEmitter::
getBDLAddr12Len4Encoding(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI);
uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI);
uint64_t Len = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI) - 1;
assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Len));
return (Len << 16) | (Base << 12) | Disp;
}
uint64_t SystemZMCCodeEmitter::
getBDLAddr12Len8Encoding(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI);
uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI);
uint64_t Len = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI) - 1;
assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<8>(Len));
return (Len << 16) | (Base << 12) | Disp;
}
uint64_t SystemZMCCodeEmitter::
getBDRAddr12Encoding(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI);
uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI);
uint64_t Len = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI);
assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Len));
return (Len << 16) | (Base << 12) | Disp;
}
uint64_t SystemZMCCodeEmitter::
getBDVAddr12Encoding(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI);
uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI);
uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI);
assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<5>(Index));
return (Index << 16) | (Base << 12) | Disp;
}
uint64_t
SystemZMCCodeEmitter::getPCRelEncoding(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups,
unsigned Kind, int64_t Offset,
bool AllowTLS) const {
const MCOperand &MO = MI.getOperand(OpNum);
const MCExpr *Expr;
if (MO.isImm())
Expr = MCConstantExpr::create(MO.getImm() + Offset, Ctx);
else {
Expr = MO.getExpr();
if (Offset) {
// The operand value is relative to the start of MI, but the fixup
// is relative to the operand field itself, which is Offset bytes
// into MI. Add Offset to the relocation value to cancel out
// this difference.
const MCExpr *OffsetExpr = MCConstantExpr::create(Offset, Ctx);
Expr = MCBinaryExpr::createAdd(Expr, OffsetExpr, Ctx);
}
}
Fixups.push_back(MCFixup::create(Offset, Expr, (MCFixupKind)Kind));
// Output the fixup for the TLS marker if present.
if (AllowTLS && OpNum + 1 < MI.getNumOperands()) {
const MCOperand &MOTLS = MI.getOperand(OpNum + 1);
Fixups.push_back(MCFixup::create(0, MOTLS.getExpr(),
(MCFixupKind)SystemZ::FK_390_TLS_CALL));
}
return 0;
}
#define ENABLE_INSTR_PREDICATE_VERIFIER
#include "SystemZGenMCCodeEmitter.inc"
MCCodeEmitter *llvm::createSystemZMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx) {
return new SystemZMCCodeEmitter(MCII, Ctx);
}

32
external/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCFixups.h vendored
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//===-- SystemZMCFixups.h - SystemZ-specific fixup entries ------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCFIXUPS_H
#define LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCFIXUPS_H
#include "llvm/MC/MCFixup.h"
namespace llvm {
namespace SystemZ {
enum FixupKind {
// These correspond directly to R_390_* relocations.
FK_390_PC12DBL = FirstTargetFixupKind,
FK_390_PC16DBL,
FK_390_PC24DBL,
FK_390_PC32DBL,
FK_390_TLS_CALL,
// Marker
LastTargetFixupKind,
NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
};
} // end namespace SystemZ
} // end namespace llvm
#endif

168
external/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCObjectWriter.cpp vendored
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//===-- SystemZMCObjectWriter.cpp - SystemZ ELF writer --------------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
#include "MCTargetDesc/SystemZMCFixups.h"
#include "MCTargetDesc/SystemZMCTargetDesc.h"
#include "llvm/BinaryFormat/ELF.h"
#include "llvm/MC/MCELFObjectWriter.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCFixup.h"
#include "llvm/MC/MCObjectWriter.h"
#include "llvm/MC/MCValue.h"
#include "llvm/Support/ErrorHandling.h"
#include <cassert>
#include <cstdint>
using namespace llvm;
namespace {
class SystemZObjectWriter : public MCELFObjectTargetWriter {
public:
SystemZObjectWriter(uint8_t OSABI);
~SystemZObjectWriter() override = default;
protected:
// Override MCELFObjectTargetWriter.
unsigned getRelocType(MCContext &Ctx, const MCValue &Target,
const MCFixup &Fixup, bool IsPCRel) const override;
};
} // end anonymous namespace
SystemZObjectWriter::SystemZObjectWriter(uint8_t OSABI)
: MCELFObjectTargetWriter(/*Is64Bit=*/true, OSABI, ELF::EM_S390,
/*HasRelocationAddend=*/ true) {}
// Return the relocation type for an absolute value of MCFixupKind Kind.
static unsigned getAbsoluteReloc(unsigned Kind) {
switch (Kind) {
case FK_Data_1: return ELF::R_390_8;
case FK_Data_2: return ELF::R_390_16;
case FK_Data_4: return ELF::R_390_32;
case FK_Data_8: return ELF::R_390_64;
}
llvm_unreachable("Unsupported absolute address");
}
// Return the relocation type for a PC-relative value of MCFixupKind Kind.
static unsigned getPCRelReloc(unsigned Kind) {
switch (Kind) {
case FK_Data_2: return ELF::R_390_PC16;
case FK_Data_4: return ELF::R_390_PC32;
case FK_Data_8: return ELF::R_390_PC64;
case SystemZ::FK_390_PC12DBL: return ELF::R_390_PC12DBL;
case SystemZ::FK_390_PC16DBL: return ELF::R_390_PC16DBL;
case SystemZ::FK_390_PC24DBL: return ELF::R_390_PC24DBL;
case SystemZ::FK_390_PC32DBL: return ELF::R_390_PC32DBL;
}
llvm_unreachable("Unsupported PC-relative address");
}
// Return the R_390_TLS_LE* relocation type for MCFixupKind Kind.
static unsigned getTLSLEReloc(unsigned Kind) {
switch (Kind) {
case FK_Data_4: return ELF::R_390_TLS_LE32;
case FK_Data_8: return ELF::R_390_TLS_LE64;
}
llvm_unreachable("Unsupported absolute address");
}
// Return the R_390_TLS_LDO* relocation type for MCFixupKind Kind.
static unsigned getTLSLDOReloc(unsigned Kind) {
switch (Kind) {
case FK_Data_4: return ELF::R_390_TLS_LDO32;
case FK_Data_8: return ELF::R_390_TLS_LDO64;
}
llvm_unreachable("Unsupported absolute address");
}
// Return the R_390_TLS_LDM* relocation type for MCFixupKind Kind.
static unsigned getTLSLDMReloc(unsigned Kind) {
switch (Kind) {
case FK_Data_4: return ELF::R_390_TLS_LDM32;
case FK_Data_8: return ELF::R_390_TLS_LDM64;
case SystemZ::FK_390_TLS_CALL: return ELF::R_390_TLS_LDCALL;
}
llvm_unreachable("Unsupported absolute address");
}
// Return the R_390_TLS_GD* relocation type for MCFixupKind Kind.
static unsigned getTLSGDReloc(unsigned Kind) {
switch (Kind) {
case FK_Data_4: return ELF::R_390_TLS_GD32;
case FK_Data_8: return ELF::R_390_TLS_GD64;
case SystemZ::FK_390_TLS_CALL: return ELF::R_390_TLS_GDCALL;
}
llvm_unreachable("Unsupported absolute address");
}
// Return the PLT relocation counterpart of MCFixupKind Kind.
static unsigned getPLTReloc(unsigned Kind) {
switch (Kind) {
case SystemZ::FK_390_PC12DBL: return ELF::R_390_PLT12DBL;
case SystemZ::FK_390_PC16DBL: return ELF::R_390_PLT16DBL;
case SystemZ::FK_390_PC24DBL: return ELF::R_390_PLT24DBL;
case SystemZ::FK_390_PC32DBL: return ELF::R_390_PLT32DBL;
}
llvm_unreachable("Unsupported absolute address");
}
unsigned SystemZObjectWriter::getRelocType(MCContext &Ctx,
const MCValue &Target,
const MCFixup &Fixup,
bool IsPCRel) const {
MCSymbolRefExpr::VariantKind Modifier = Target.getAccessVariant();
unsigned Kind = Fixup.getKind();
switch (Modifier) {
case MCSymbolRefExpr::VK_None:
if (IsPCRel)
return getPCRelReloc(Kind);
return getAbsoluteReloc(Kind);
case MCSymbolRefExpr::VK_NTPOFF:
assert(!IsPCRel && "NTPOFF shouldn't be PC-relative");
return getTLSLEReloc(Kind);
case MCSymbolRefExpr::VK_INDNTPOFF:
if (IsPCRel && Kind == SystemZ::FK_390_PC32DBL)
return ELF::R_390_TLS_IEENT;
llvm_unreachable("Only PC-relative INDNTPOFF accesses are supported for now");
case MCSymbolRefExpr::VK_DTPOFF:
assert(!IsPCRel && "DTPOFF shouldn't be PC-relative");
return getTLSLDOReloc(Kind);
case MCSymbolRefExpr::VK_TLSLDM:
assert(!IsPCRel && "TLSLDM shouldn't be PC-relative");
return getTLSLDMReloc(Kind);
case MCSymbolRefExpr::VK_TLSGD:
assert(!IsPCRel && "TLSGD shouldn't be PC-relative");
return getTLSGDReloc(Kind);
case MCSymbolRefExpr::VK_GOT:
if (IsPCRel && Kind == SystemZ::FK_390_PC32DBL)
return ELF::R_390_GOTENT;
llvm_unreachable("Only PC-relative GOT accesses are supported for now");
case MCSymbolRefExpr::VK_PLT:
assert(IsPCRel && "@PLT shouldt be PC-relative");
return getPLTReloc(Kind);
default:
llvm_unreachable("Modifier not supported");
}
}
std::unique_ptr<MCObjectWriter>
llvm::createSystemZObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI) {
return createELFObjectWriter(llvm::make_unique<SystemZObjectWriter>(OSABI),
OS, /*IsLittleEndian=*/false);
}

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@ -1,212 +0,0 @@
//===-- SystemZMCTargetDesc.cpp - SystemZ target descriptions -------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
#include "SystemZMCTargetDesc.h"
#include "InstPrinter/SystemZInstPrinter.h"
#include "SystemZMCAsmInfo.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Support/TargetRegistry.h"
using namespace llvm;
#define GET_INSTRINFO_MC_DESC
#include "SystemZGenInstrInfo.inc"
#define GET_SUBTARGETINFO_MC_DESC
#include "SystemZGenSubtargetInfo.inc"
#define GET_REGINFO_MC_DESC
#include "SystemZGenRegisterInfo.inc"
const unsigned SystemZMC::GR32Regs[16] = {
SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L,
SystemZ::R4L, SystemZ::R5L, SystemZ::R6L, SystemZ::R7L,
SystemZ::R8L, SystemZ::R9L, SystemZ::R10L, SystemZ::R11L,
SystemZ::R12L, SystemZ::R13L, SystemZ::R14L, SystemZ::R15L
};
const unsigned SystemZMC::GRH32Regs[16] = {
SystemZ::R0H, SystemZ::R1H, SystemZ::R2H, SystemZ::R3H,
SystemZ::R4H, SystemZ::R5H, SystemZ::R6H, SystemZ::R7H,
SystemZ::R8H, SystemZ::R9H, SystemZ::R10H, SystemZ::R11H,
SystemZ::R12H, SystemZ::R13H, SystemZ::R14H, SystemZ::R15H
};
const unsigned SystemZMC::GR64Regs[16] = {
SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D,
SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D,
SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D,
SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D
};
const unsigned SystemZMC::GR128Regs[16] = {
SystemZ::R0Q, 0, SystemZ::R2Q, 0,
SystemZ::R4Q, 0, SystemZ::R6Q, 0,
SystemZ::R8Q, 0, SystemZ::R10Q, 0,
SystemZ::R12Q, 0, SystemZ::R14Q, 0
};
const unsigned SystemZMC::FP32Regs[16] = {
SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S,
SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S,
SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S,
SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S
};
const unsigned SystemZMC::FP64Regs[16] = {
SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D,
SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D,
SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D,
SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D
};
const unsigned SystemZMC::FP128Regs[16] = {
SystemZ::F0Q, SystemZ::F1Q, 0, 0,
SystemZ::F4Q, SystemZ::F5Q, 0, 0,
SystemZ::F8Q, SystemZ::F9Q, 0, 0,
SystemZ::F12Q, SystemZ::F13Q, 0, 0
};
const unsigned SystemZMC::VR32Regs[32] = {
SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S,
SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S,
SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S,
SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S,
SystemZ::F16S, SystemZ::F17S, SystemZ::F18S, SystemZ::F19S,
SystemZ::F20S, SystemZ::F21S, SystemZ::F22S, SystemZ::F23S,
SystemZ::F24S, SystemZ::F25S, SystemZ::F26S, SystemZ::F27S,
SystemZ::F28S, SystemZ::F29S, SystemZ::F30S, SystemZ::F31S
};
const unsigned SystemZMC::VR64Regs[32] = {
SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D,
SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D,
SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D,
SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D,
SystemZ::F16D, SystemZ::F17D, SystemZ::F18D, SystemZ::F19D,
SystemZ::F20D, SystemZ::F21D, SystemZ::F22D, SystemZ::F23D,
SystemZ::F24D, SystemZ::F25D, SystemZ::F26D, SystemZ::F27D,
SystemZ::F28D, SystemZ::F29D, SystemZ::F30D, SystemZ::F31D
};
const unsigned SystemZMC::VR128Regs[32] = {
SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3,
SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7,
SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11,
SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15,
SystemZ::V16, SystemZ::V17, SystemZ::V18, SystemZ::V19,
SystemZ::V20, SystemZ::V21, SystemZ::V22, SystemZ::V23,
SystemZ::V24, SystemZ::V25, SystemZ::V26, SystemZ::V27,
SystemZ::V28, SystemZ::V29, SystemZ::V30, SystemZ::V31
};
const unsigned SystemZMC::AR32Regs[16] = {
SystemZ::A0, SystemZ::A1, SystemZ::A2, SystemZ::A3,
SystemZ::A4, SystemZ::A5, SystemZ::A6, SystemZ::A7,
SystemZ::A8, SystemZ::A9, SystemZ::A10, SystemZ::A11,
SystemZ::A12, SystemZ::A13, SystemZ::A14, SystemZ::A15
};
const unsigned SystemZMC::CR64Regs[16] = {
SystemZ::C0, SystemZ::C1, SystemZ::C2, SystemZ::C3,
SystemZ::C4, SystemZ::C5, SystemZ::C6, SystemZ::C7,
SystemZ::C8, SystemZ::C9, SystemZ::C10, SystemZ::C11,
SystemZ::C12, SystemZ::C13, SystemZ::C14, SystemZ::C15
};
unsigned SystemZMC::getFirstReg(unsigned Reg) {
static unsigned Map[SystemZ::NUM_TARGET_REGS];
static bool Initialized = false;
if (!Initialized) {
for (unsigned I = 0; I < 16; ++I) {
Map[GR32Regs[I]] = I;
Map[GRH32Regs[I]] = I;
Map[GR64Regs[I]] = I;
Map[GR128Regs[I]] = I;
Map[FP128Regs[I]] = I;
Map[AR32Regs[I]] = I;
}
for (unsigned I = 0; I < 32; ++I) {
Map[VR32Regs[I]] = I;
Map[VR64Regs[I]] = I;
Map[VR128Regs[I]] = I;
}
}
assert(Reg < SystemZ::NUM_TARGET_REGS);
return Map[Reg];
}
static MCAsmInfo *createSystemZMCAsmInfo(const MCRegisterInfo &MRI,
const Triple &TT) {
MCAsmInfo *MAI = new SystemZMCAsmInfo(TT);
MCCFIInstruction Inst =
MCCFIInstruction::createDefCfa(nullptr,
MRI.getDwarfRegNum(SystemZ::R15D, true),
SystemZMC::CFAOffsetFromInitialSP);
MAI->addInitialFrameState(Inst);
return MAI;
}
static MCInstrInfo *createSystemZMCInstrInfo() {
MCInstrInfo *X = new MCInstrInfo();
InitSystemZMCInstrInfo(X);
return X;
}
static MCRegisterInfo *createSystemZMCRegisterInfo(const Triple &TT) {
MCRegisterInfo *X = new MCRegisterInfo();
InitSystemZMCRegisterInfo(X, SystemZ::R14D);
return X;
}
static MCSubtargetInfo *
createSystemZMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
return createSystemZMCSubtargetInfoImpl(TT, CPU, FS);
}
static MCInstPrinter *createSystemZMCInstPrinter(const Triple &T,
unsigned SyntaxVariant,
const MCAsmInfo &MAI,
const MCInstrInfo &MII,
const MCRegisterInfo &MRI) {
return new SystemZInstPrinter(MAI, MII, MRI);
}
extern "C" void LLVMInitializeSystemZTargetMC() {
// Register the MCAsmInfo.
TargetRegistry::RegisterMCAsmInfo(getTheSystemZTarget(),
createSystemZMCAsmInfo);
// Register the MCCodeEmitter.
TargetRegistry::RegisterMCCodeEmitter(getTheSystemZTarget(),
createSystemZMCCodeEmitter);
// Register the MCInstrInfo.
TargetRegistry::RegisterMCInstrInfo(getTheSystemZTarget(),
createSystemZMCInstrInfo);
// Register the MCRegisterInfo.
TargetRegistry::RegisterMCRegInfo(getTheSystemZTarget(),
createSystemZMCRegisterInfo);
// Register the MCSubtargetInfo.
TargetRegistry::RegisterMCSubtargetInfo(getTheSystemZTarget(),
createSystemZMCSubtargetInfo);
// Register the MCAsmBackend.
TargetRegistry::RegisterMCAsmBackend(getTheSystemZTarget(),
createSystemZMCAsmBackend);
// Register the MCInstPrinter.
TargetRegistry::RegisterMCInstPrinter(getTheSystemZTarget(),
createSystemZMCInstPrinter);
}

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//===-- SystemZMCTargetDesc.h - SystemZ target descriptions -----*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCTARGETDESC_H
#define LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCTARGETDESC_H
#include "llvm/Support/DataTypes.h"
#include <memory>
namespace llvm {
class MCAsmBackend;
class MCCodeEmitter;
class MCContext;
class MCInstrInfo;
class MCObjectWriter;
class MCRegisterInfo;
class MCSubtargetInfo;
class MCTargetOptions;
class StringRef;
class Target;
class Triple;
class raw_pwrite_stream;
class raw_ostream;
Target &getTheSystemZTarget();
namespace SystemZMC {
// How many bytes are in the ABI-defined, caller-allocated part of
// a stack frame.
const int64_t CallFrameSize = 160;
// The offset of the DWARF CFA from the incoming stack pointer.
const int64_t CFAOffsetFromInitialSP = CallFrameSize;
// Maps of asm register numbers to LLVM register numbers, with 0 indicating
// an invalid register. In principle we could use 32-bit and 64-bit register
// classes directly, provided that we relegated the GPR allocation order
// in SystemZRegisterInfo.td to an AltOrder and left the default order
// as %r0-%r15. It seems better to provide the same interface for
// all classes though.
extern const unsigned GR32Regs[16];
extern const unsigned GRH32Regs[16];
extern const unsigned GR64Regs[16];
extern const unsigned GR128Regs[16];
extern const unsigned FP32Regs[16];
extern const unsigned FP64Regs[16];
extern const unsigned FP128Regs[16];
extern const unsigned VR32Regs[32];
extern const unsigned VR64Regs[32];
extern const unsigned VR128Regs[32];
extern const unsigned AR32Regs[16];
extern const unsigned CR64Regs[16];
// Return the 0-based number of the first architectural register that
// contains the given LLVM register. E.g. R1D -> 1.
unsigned getFirstReg(unsigned Reg);
// Return the given register as a GR64.
inline unsigned getRegAsGR64(unsigned Reg) {
return GR64Regs[getFirstReg(Reg)];
}
// Return the given register as a low GR32.
inline unsigned getRegAsGR32(unsigned Reg) {
return GR32Regs[getFirstReg(Reg)];
}
// Return the given register as a high GR32.
inline unsigned getRegAsGRH32(unsigned Reg) {
return GRH32Regs[getFirstReg(Reg)];
}
// Return the given register as a VR128.
inline unsigned getRegAsVR128(unsigned Reg) {
return VR128Regs[getFirstReg(Reg)];
}
} // end namespace SystemZMC
MCCodeEmitter *createSystemZMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx);
MCAsmBackend *createSystemZMCAsmBackend(const Target &T,
const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI,
const MCTargetOptions &Options);
std::unique_ptr<MCObjectWriter> createSystemZObjectWriter(raw_pwrite_stream &OS,
uint8_t OSABI);
} // end namespace llvm
// Defines symbolic names for SystemZ registers.
// This defines a mapping from register name to register number.
#define GET_REGINFO_ENUM
#include "SystemZGenRegisterInfo.inc"
// Defines symbolic names for the SystemZ instructions.
#define GET_INSTRINFO_ENUM
#include "SystemZGenInstrInfo.inc"
#define GET_SUBTARGETINFO_ENUM
#include "SystemZGenSubtargetInfo.inc"
#endif