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//===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the PPCMCCodeEmitter class.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/PPCFixupKinds.h"
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#include "PPCInstrInfo.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCFixup.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/Endian.h"
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#include "llvm/Support/EndianStream.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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#include <cassert>
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#include <cstdint>
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using namespace llvm;
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#define DEBUG_TYPE "mccodeemitter"
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STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
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namespace {
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class PPCMCCodeEmitter : public MCCodeEmitter {
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const MCInstrInfo &MCII;
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const MCContext &CTX;
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bool IsLittleEndian;
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public:
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PPCMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
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: MCII(mcii), CTX(ctx),
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IsLittleEndian(ctx.getAsmInfo()->isLittleEndian()) {}
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PPCMCCodeEmitter(const PPCMCCodeEmitter &) = delete;
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void operator=(const PPCMCCodeEmitter &) = delete;
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~PPCMCCodeEmitter() override = default;
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unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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unsigned getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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unsigned getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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unsigned getImm16Encoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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unsigned getMemRIX16Encoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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unsigned getSPE8DisEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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unsigned getSPE4DisEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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unsigned getSPE2DisEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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unsigned getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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unsigned getTLSCallEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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/// getMachineOpValue - Return binary encoding of operand. If the machine
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/// operand requires relocation, record the relocation and return zero.
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unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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// getBinaryCodeForInstr - TableGen'erated function for getting the
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// binary encoding for an instruction.
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uint64_t getBinaryCodeForInstr(const MCInst &MI,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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void encodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const override {
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verifyInstructionPredicates(MI,
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computeAvailableFeatures(STI.getFeatureBits()));
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unsigned Opcode = MI.getOpcode();
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const MCInstrDesc &Desc = MCII.get(Opcode);
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uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
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// Output the constant in big/little endian byte order.
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unsigned Size = Desc.getSize();
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switch (Size) {
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case 0:
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break;
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case 4:
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if (IsLittleEndian) {
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support::endian::Writer<support::little>(OS).write<uint32_t>(Bits);
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} else {
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support::endian::Writer<support::big>(OS).write<uint32_t>(Bits);
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}
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break;
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case 8:
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// If we emit a pair of instructions, the first one is
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// always in the top 32 bits, even on little-endian.
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if (IsLittleEndian) {
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uint64_t Swapped = (Bits << 32) | (Bits >> 32);
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support::endian::Writer<support::little>(OS).write<uint64_t>(Swapped);
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} else {
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support::endian::Writer<support::big>(OS).write<uint64_t>(Bits);
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}
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break;
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default:
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llvm_unreachable("Invalid instruction size");
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}
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++MCNumEmitted; // Keep track of the # of mi's emitted.
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}
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private:
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uint64_t computeAvailableFeatures(const FeatureBitset &FB) const;
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void verifyInstructionPredicates(const MCInst &MI,
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uint64_t AvailableFeatures) const;
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};
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} // end anonymous namespace
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MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII,
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const MCRegisterInfo &MRI,
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MCContext &Ctx) {
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return new PPCMCCodeEmitter(MCII, Ctx);
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}
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unsigned PPCMCCodeEmitter::
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getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
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// Add a fixup for the branch target.
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Fixups.push_back(MCFixup::create(0, MO.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_br24));
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return 0;
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}
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unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
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// Add a fixup for the branch target.
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Fixups.push_back(MCFixup::create(0, MO.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_brcond14));
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return 0;
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}
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unsigned PPCMCCodeEmitter::
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getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
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// Add a fixup for the branch target.
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Fixups.push_back(MCFixup::create(0, MO.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_br24abs));
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return 0;
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}
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unsigned PPCMCCodeEmitter::
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getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
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// Add a fixup for the branch target.
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Fixups.push_back(MCFixup::create(0, MO.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_brcond14abs));
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return 0;
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}
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unsigned PPCMCCodeEmitter::getImm16Encoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
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// Add a fixup for the immediate field.
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Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_half16));
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return 0;
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}
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unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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// Encode (imm, reg) as a memri, which has the low 16-bits as the
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// displacement and the next 5 bits as the register #.
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assert(MI.getOperand(OpNo+1).isReg());
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unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 16;
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const MCOperand &MO = MI.getOperand(OpNo);
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if (MO.isImm())
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return (getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF) | RegBits;
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// Add a fixup for the displacement field.
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Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_half16));
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return RegBits;
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}
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unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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// Encode (imm, reg) as a memrix, which has the low 14-bits as the
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// displacement and the next 5 bits as the register #.
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assert(MI.getOperand(OpNo+1).isReg());
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unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 14;
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const MCOperand &MO = MI.getOperand(OpNo);
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if (MO.isImm())
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return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF) | RegBits;
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// Add a fixup for the displacement field.
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Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_half16ds));
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return RegBits;
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}
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unsigned PPCMCCodeEmitter::getMemRIX16Encoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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// Encode (imm, reg) as a memrix16, which has the low 12-bits as the
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// displacement and the next 5 bits as the register #.
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assert(MI.getOperand(OpNo+1).isReg());
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unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 12;
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const MCOperand &MO = MI.getOperand(OpNo);
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assert(MO.isImm() && !(MO.getImm() % 16) &&
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"Expecting an immediate that is a multiple of 16");
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return ((getMachineOpValue(MI, MO, Fixups, STI) >> 4) & 0xFFF) | RegBits;
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}
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unsigned PPCMCCodeEmitter::getSPE8DisEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI)
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const {
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// Encode (imm, reg) as a spe8dis, which has the low 5-bits of (imm / 8)
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// as the displacement and the next 5 bits as the register #.
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assert(MI.getOperand(OpNo+1).isReg());
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uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;
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const MCOperand &MO = MI.getOperand(OpNo);
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assert(MO.isImm());
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uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 3;
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return reverseBits(Imm | RegBits) >> 22;
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}
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unsigned PPCMCCodeEmitter::getSPE4DisEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI)
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const {
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// Encode (imm, reg) as a spe4dis, which has the low 5-bits of (imm / 4)
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// as the displacement and the next 5 bits as the register #.
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assert(MI.getOperand(OpNo+1).isReg());
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uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;
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const MCOperand &MO = MI.getOperand(OpNo);
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assert(MO.isImm());
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uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 2;
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return reverseBits(Imm | RegBits) >> 22;
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}
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unsigned PPCMCCodeEmitter::getSPE2DisEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI)
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const {
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// Encode (imm, reg) as a spe2dis, which has the low 5-bits of (imm / 2)
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// as the displacement and the next 5 bits as the register #.
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assert(MI.getOperand(OpNo+1).isReg());
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uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;
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const MCOperand &MO = MI.getOperand(OpNo);
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assert(MO.isImm());
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uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 1;
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return reverseBits(Imm | RegBits) >> 22;
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}
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unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups, STI);
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// Add a fixup for the TLS register, which simply provides a relocation
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// hint to the linker that this statement is part of a relocation sequence.
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// Return the thread-pointer register's encoding.
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Fixups.push_back(MCFixup::create(0, MO.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_nofixup));
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const Triple &TT = STI.getTargetTriple();
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bool isPPC64 = TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le;
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return CTX.getRegisterInfo()->getEncodingValue(isPPC64 ? PPC::X13 : PPC::R2);
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}
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unsigned PPCMCCodeEmitter::getTLSCallEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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// For special TLS calls, we need two fixups; one for the branch target
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// (__tls_get_addr), which we create via getDirectBrEncoding as usual,
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// and one for the TLSGD or TLSLD symbol, which is emitted here.
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const MCOperand &MO = MI.getOperand(OpNo+1);
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Fixups.push_back(MCFixup::create(0, MO.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_nofixup));
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return getDirectBrEncoding(MI, OpNo, Fixups, STI);
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}
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unsigned PPCMCCodeEmitter::
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get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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assert((MI.getOpcode() == PPC::MTOCRF || MI.getOpcode() == PPC::MTOCRF8 ||
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MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) &&
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(MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
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return 0x80 >> CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
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}
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unsigned PPCMCCodeEmitter::
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getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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if (MO.isReg()) {
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// MTOCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
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// The GPR operand should come through here though.
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assert((MI.getOpcode() != PPC::MTOCRF && MI.getOpcode() != PPC::MTOCRF8 &&
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MI.getOpcode() != PPC::MFOCRF && MI.getOpcode() != PPC::MFOCRF8) ||
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MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
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unsigned Reg = MO.getReg();
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unsigned Encode = CTX.getRegisterInfo()->getEncodingValue(Reg);
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if ((MCII.get(MI.getOpcode()).TSFlags & PPCII::UseVSXReg))
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if (PPCInstrInfo::isVRRegister(Reg))
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Encode += 32;
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return Encode;
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}
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assert(MO.isImm() &&
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"Relocation required in an instruction that we cannot encode!");
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return MO.getImm();
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}
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#define ENABLE_INSTR_PREDICATE_VERIFIER
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#include "PPCGenMCCodeEmitter.inc"
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Reference in New Issue
Block a user