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Imported Upstream version 5.18.0.167

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Former-commit-id: 289509151e0fee68a1b591a20c9f109c3c789d3a
This commit is contained in:
Xamarin Public Jenkins (auto-signing)
2018-10-20 08:25:10 +00:00
parent e19d552987
commit b084638f15
28489 changed files with 184 additions and 3866856 deletions
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3
external/llvm/lib/Target/Mips/AsmParser/CMakeLists.txt vendored
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@ -1,3 +0,0 @@
add_llvm_library(LLVMMipsAsmParser
MipsAsmParser.cpp
)

23
external/llvm/lib/Target/Mips/AsmParser/LLVMBuild.txt vendored
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@ -1,23 +0,0 @@
;===- ./lib/Target/Mips/AsmParser/LLVMBuild.txt ----------------*- Conf -*--===;
;
; The LLVM Compiler Infrastructure
;
; This file is distributed under the University of Illinois Open Source
; License. See LICENSE.TXT for details.
;
;===------------------------------------------------------------------------===;
;
; This is an LLVMBuild description file for the components in this subdirectory.
;
; For more information on the LLVMBuild system, please see:
;
; http://llvm.org/docs/LLVMBuild.html
;
;===------------------------------------------------------------------------===;
[component_0]
type = Library
name = MipsAsmParser
parent = Mips
required_libraries = MC MCParser MipsDesc MipsInfo Support
add_to_library_groups = Mips

1
external/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp.REMOVED.git-id vendored
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@ -1 +0,0 @@
f36a4317b1b9c3016e15d28a4e20eee96f1b70f5

58
external/llvm/lib/Target/Mips/CMakeLists.txt vendored
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@ -1,58 +0,0 @@
set(LLVM_TARGET_DEFINITIONS Mips.td)
tablegen(LLVM MipsGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM MipsGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM MipsGenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM MipsGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM MipsGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM MipsGenDAGISel.inc -gen-dag-isel)
tablegen(LLVM MipsGenFastISel.inc -gen-fast-isel)
tablegen(LLVM MipsGenCallingConv.inc -gen-callingconv)
tablegen(LLVM MipsGenSubtargetInfo.inc -gen-subtarget)
tablegen(LLVM MipsGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM MipsGenMCPseudoLowering.inc -gen-pseudo-lowering)
add_public_tablegen_target(MipsCommonTableGen)
add_llvm_target(MipsCodeGen
Mips16FrameLowering.cpp
Mips16HardFloat.cpp
Mips16HardFloatInfo.cpp
Mips16InstrInfo.cpp
Mips16ISelDAGToDAG.cpp
Mips16ISelLowering.cpp
Mips16RegisterInfo.cpp
MipsAnalyzeImmediate.cpp
MipsAsmPrinter.cpp
MipsCCState.cpp
MipsConstantIslandPass.cpp
MipsDelaySlotFiller.cpp
MipsFastISel.cpp
MipsHazardSchedule.cpp
MipsInstrInfo.cpp
MipsISelDAGToDAG.cpp
MipsISelLowering.cpp
MipsFrameLowering.cpp
MipsLongBranch.cpp
MipsMCInstLower.cpp
MipsMachineFunction.cpp
MipsModuleISelDAGToDAG.cpp
MipsOptimizePICCall.cpp
MipsOs16.cpp
MipsRegisterInfo.cpp
MipsSEFrameLowering.cpp
MipsSEInstrInfo.cpp
MipsSEISelDAGToDAG.cpp
MipsSEISelLowering.cpp
MipsSERegisterInfo.cpp
MipsSubtarget.cpp
MipsTargetMachine.cpp
MipsTargetObjectFile.cpp
MicroMipsSizeReduction.cpp
)
add_subdirectory(InstPrinter)
add_subdirectory(Disassembler)
add_subdirectory(TargetInfo)
add_subdirectory(MCTargetDesc)
add_subdirectory(AsmParser)

3
external/llvm/lib/Target/Mips/Disassembler/CMakeLists.txt vendored
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@ -1,3 +0,0 @@
add_llvm_library(LLVMMipsDisassembler
MipsDisassembler.cpp
)

23
external/llvm/lib/Target/Mips/Disassembler/LLVMBuild.txt vendored
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@ -1,23 +0,0 @@
;===- ./lib/Target/Mips/Disassembler/LLVMBuild.txt -------------*- Conf -*--===;
;
; The LLVM Compiler Infrastructure
;
; This file is distributed under the University of Illinois Open Source
; License. See LICENSE.TXT for details.
;
;===------------------------------------------------------------------------===;
;
; This is an LLVMBuild description file for the components in this subdirectory.
;
; For more information on the LLVMBuild system, please see:
;
; http://llvm.org/docs/LLVMBuild.html
;
;===------------------------------------------------------------------------===;
[component_0]
type = Library
name = MipsDisassembler
parent = Mips
required_libraries = MCDisassembler MipsInfo Support
add_to_library_groups = Mips

2594
external/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp vendored
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File diff suppressed because it is too large Load Diff

3
external/llvm/lib/Target/Mips/InstPrinter/CMakeLists.txt vendored
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@ -1,3 +0,0 @@
add_llvm_library(LLVMMipsAsmPrinter
MipsInstPrinter.cpp
)

23
external/llvm/lib/Target/Mips/InstPrinter/LLVMBuild.txt vendored
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@ -1,23 +0,0 @@
;===- ./lib/Target/Mips/InstPrinter/LLVMBuild.txt --------------*- Conf -*--===;
;
; The LLVM Compiler Infrastructure
;
; This file is distributed under the University of Illinois Open Source
; License. See LICENSE.TXT for details.
;
;===------------------------------------------------------------------------===;
;
; This is an LLVMBuild description file for the components in this subdirectory.
;
; For more information on the LLVMBuild system, please see:
;
; http://llvm.org/docs/LLVMBuild.html
;
;===------------------------------------------------------------------------===;
[component_0]
type = Library
name = MipsAsmPrinter
parent = Mips
required_libraries = MC Support
add_to_library_groups = Mips

293
external/llvm/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp vendored
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@ -1,293 +0,0 @@
//===-- MipsInstPrinter.cpp - Convert Mips MCInst to assembly syntax ------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This class prints an Mips MCInst to a .s file.
//
//===----------------------------------------------------------------------===//
#include "MipsInstPrinter.h"
#include "MCTargetDesc/MipsMCExpr.h"
#include "MipsInstrInfo.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
#define DEBUG_TYPE "asm-printer"
#define PRINT_ALIAS_INSTR
#include "MipsGenAsmWriter.inc"
template<unsigned R>
static bool isReg(const MCInst &MI, unsigned OpNo) {
assert(MI.getOperand(OpNo).isReg() && "Register operand expected.");
return MI.getOperand(OpNo).getReg() == R;
}
const char* Mips::MipsFCCToString(Mips::CondCode CC) {
switch (CC) {
case FCOND_F:
case FCOND_T: return "f";
case FCOND_UN:
case FCOND_OR: return "un";
case FCOND_OEQ:
case FCOND_UNE: return "eq";
case FCOND_UEQ:
case FCOND_ONE: return "ueq";
case FCOND_OLT:
case FCOND_UGE: return "olt";
case FCOND_ULT:
case FCOND_OGE: return "ult";
case FCOND_OLE:
case FCOND_UGT: return "ole";
case FCOND_ULE:
case FCOND_OGT: return "ule";
case FCOND_SF:
case FCOND_ST: return "sf";
case FCOND_NGLE:
case FCOND_GLE: return "ngle";
case FCOND_SEQ:
case FCOND_SNE: return "seq";
case FCOND_NGL:
case FCOND_GL: return "ngl";
case FCOND_LT:
case FCOND_NLT: return "lt";
case FCOND_NGE:
case FCOND_GE: return "nge";
case FCOND_LE:
case FCOND_NLE: return "le";
case FCOND_NGT:
case FCOND_GT: return "ngt";
}
llvm_unreachable("Impossible condition code!");
}
void MipsInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
OS << '$' << StringRef(getRegisterName(RegNo)).lower();
}
void MipsInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
StringRef Annot, const MCSubtargetInfo &STI) {
switch (MI->getOpcode()) {
default:
break;
case Mips::RDHWR:
case Mips::RDHWR64:
O << "\t.set\tpush\n";
O << "\t.set\tmips32r2\n";
break;
case Mips::Save16:
O << "\tsave\t";
printSaveRestore(MI, O);
O << " # 16 bit inst\n";
return;
case Mips::SaveX16:
O << "\tsave\t";
printSaveRestore(MI, O);
O << "\n";
return;
case Mips::Restore16:
O << "\trestore\t";
printSaveRestore(MI, O);
O << " # 16 bit inst\n";
return;
case Mips::RestoreX16:
O << "\trestore\t";
printSaveRestore(MI, O);
O << "\n";
return;
}
// Try to print any aliases first.
if (!printAliasInstr(MI, O) && !printAlias(*MI, O))
printInstruction(MI, O);
printAnnotation(O, Annot);
switch (MI->getOpcode()) {
default:
break;
case Mips::RDHWR:
case Mips::RDHWR64:
O << "\n\t.set\tpop";
}
}
void MipsInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
const MCOperand &Op = MI->getOperand(OpNo);
if (Op.isReg()) {
printRegName(O, Op.getReg());
return;
}
if (Op.isImm()) {
O << formatImm(Op.getImm());
return;
}
assert(Op.isExpr() && "unknown operand kind in printOperand");
Op.getExpr()->print(O, &MAI, true);
}
template <unsigned Bits, unsigned Offset>
void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) {
const MCOperand &MO = MI->getOperand(opNum);
if (MO.isImm()) {
uint64_t Imm = MO.getImm();
Imm -= Offset;
Imm &= (1 << Bits) - 1;
Imm += Offset;
O << formatImm(Imm);
return;
}
printOperand(MI, opNum, O);
}
void MipsInstPrinter::
printMemOperand(const MCInst *MI, int opNum, raw_ostream &O) {
// Load/Store memory operands -- imm($reg)
// If PIC target the target is loaded as the
// pattern lw $25,%call16($28)
// opNum can be invalid if instruction had reglist as operand.
// MemOperand is always last operand of instruction (base + offset).
switch (MI->getOpcode()) {
default:
break;
case Mips::SWM32_MM:
case Mips::LWM32_MM:
case Mips::SWM16_MM:
case Mips::SWM16_MMR6:
case Mips::LWM16_MM:
case Mips::LWM16_MMR6:
opNum = MI->getNumOperands() - 2;
break;
}
printOperand(MI, opNum+1, O);
O << "(";
printOperand(MI, opNum, O);
O << ")";
}
void MipsInstPrinter::
printMemOperandEA(const MCInst *MI, int opNum, raw_ostream &O) {
// when using stack locations for not load/store instructions
// print the same way as all normal 3 operand instructions.
printOperand(MI, opNum, O);
O << ", ";
printOperand(MI, opNum+1, O);
}
void MipsInstPrinter::
printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O) {
const MCOperand& MO = MI->getOperand(opNum);
O << MipsFCCToString((Mips::CondCode)MO.getImm());
}
void MipsInstPrinter::
printRegisterPair(const MCInst *MI, int opNum, raw_ostream &O) {
printRegName(O, MI->getOperand(opNum).getReg());
}
void MipsInstPrinter::
printSHFMask(const MCInst *MI, int opNum, raw_ostream &O) {
llvm_unreachable("TODO");
}
bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI,
unsigned OpNo, raw_ostream &OS) {
OS << "\t" << Str << "\t";
printOperand(&MI, OpNo, OS);
return true;
}
bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI,
unsigned OpNo0, unsigned OpNo1,
raw_ostream &OS) {
printAlias(Str, MI, OpNo0, OS);
OS << ", ";
printOperand(&MI, OpNo1, OS);
return true;
}
bool MipsInstPrinter::printAlias(const MCInst &MI, raw_ostream &OS) {
switch (MI.getOpcode()) {
case Mips::BEQ:
case Mips::BEQ_MM:
// beq $zero, $zero, $L2 => b $L2
// beq $r0, $zero, $L2 => beqz $r0, $L2
return (isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) &&
printAlias("b", MI, 2, OS)) ||
(isReg<Mips::ZERO>(MI, 1) && printAlias("beqz", MI, 0, 2, OS));
case Mips::BEQ64:
// beq $r0, $zero, $L2 => beqz $r0, $L2
return isReg<Mips::ZERO_64>(MI, 1) && printAlias("beqz", MI, 0, 2, OS);
case Mips::BNE:
case Mips::BNE_MM:
// bne $r0, $zero, $L2 => bnez $r0, $L2
return isReg<Mips::ZERO>(MI, 1) && printAlias("bnez", MI, 0, 2, OS);
case Mips::BNE64:
// bne $r0, $zero, $L2 => bnez $r0, $L2
return isReg<Mips::ZERO_64>(MI, 1) && printAlias("bnez", MI, 0, 2, OS);
case Mips::BGEZAL:
// bgezal $zero, $L1 => bal $L1
return isReg<Mips::ZERO>(MI, 0) && printAlias("bal", MI, 1, OS);
case Mips::BC1T:
// bc1t $fcc0, $L1 => bc1t $L1
return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1t", MI, 1, OS);
case Mips::BC1F:
// bc1f $fcc0, $L1 => bc1f $L1
return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1f", MI, 1, OS);
case Mips::JALR:
// jalr $ra, $r1 => jalr $r1
return isReg<Mips::RA>(MI, 0) && printAlias("jalr", MI, 1, OS);
case Mips::JALR64:
// jalr $ra, $r1 => jalr $r1
return isReg<Mips::RA_64>(MI, 0) && printAlias("jalr", MI, 1, OS);
case Mips::NOR:
case Mips::NOR_MM:
case Mips::NOR_MMR6:
// nor $r0, $r1, $zero => not $r0, $r1
return isReg<Mips::ZERO>(MI, 2) && printAlias("not", MI, 0, 1, OS);
case Mips::NOR64:
// nor $r0, $r1, $zero => not $r0, $r1
return isReg<Mips::ZERO_64>(MI, 2) && printAlias("not", MI, 0, 1, OS);
case Mips::OR:
// or $r0, $r1, $zero => move $r0, $r1
return isReg<Mips::ZERO>(MI, 2) && printAlias("move", MI, 0, 1, OS);
default: return false;
}
}
void MipsInstPrinter::printSaveRestore(const MCInst *MI, raw_ostream &O) {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
if (i != 0) O << ", ";
if (MI->getOperand(i).isReg())
printRegName(O, MI->getOperand(i).getReg());
else
printUImm<16>(MI, i, O);
}
}
void MipsInstPrinter::
printRegisterList(const MCInst *MI, int opNum, raw_ostream &O) {
// - 2 because register List is always first operand of instruction and it is
// always followed by memory operand (base + offset).
for (int i = opNum, e = MI->getNumOperands() - 2; i != e; ++i) {
if (i != opNum)
O << ", ";
printRegName(O, MI->getOperand(i).getReg());
}
}

114
external/llvm/lib/Target/Mips/InstPrinter/MipsInstPrinter.h vendored
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@ -1,114 +0,0 @@
//=== MipsInstPrinter.h - Convert Mips MCInst to assembly syntax -*- C++ -*-==//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This class prints a Mips MCInst to a .s file.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_MIPS_INSTPRINTER_MIPSINSTPRINTER_H
#define LLVM_LIB_TARGET_MIPS_INSTPRINTER_MIPSINSTPRINTER_H
#include "llvm/MC/MCInstPrinter.h"
namespace llvm {
// These enumeration declarations were originally in MipsInstrInfo.h but
// had to be moved here to avoid circular dependencies between
// LLVMMipsCodeGen and LLVMMipsAsmPrinter.
namespace Mips {
// Mips Branch Codes
enum FPBranchCode {
BRANCH_F,
BRANCH_T,
BRANCH_FL,
BRANCH_TL,
BRANCH_INVALID
};
// Mips Condition Codes
enum CondCode {
// To be used with float branch True
FCOND_F,
FCOND_UN,
FCOND_OEQ,
FCOND_UEQ,
FCOND_OLT,
FCOND_ULT,
FCOND_OLE,
FCOND_ULE,
FCOND_SF,
FCOND_NGLE,
FCOND_SEQ,
FCOND_NGL,
FCOND_LT,
FCOND_NGE,
FCOND_LE,
FCOND_NGT,
// To be used with float branch False
// This conditions have the same mnemonic as the
// above ones, but are used with a branch False;
FCOND_T,
FCOND_OR,
FCOND_UNE,
FCOND_ONE,
FCOND_UGE,
FCOND_OGE,
FCOND_UGT,
FCOND_OGT,
FCOND_ST,
FCOND_GLE,
FCOND_SNE,
FCOND_GL,
FCOND_NLT,
FCOND_GE,
FCOND_NLE,
FCOND_GT
};
const char *MipsFCCToString(Mips::CondCode CC);
} // end namespace Mips
class MipsInstPrinter : public MCInstPrinter {
public:
MipsInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
const MCRegisterInfo &MRI)
: MCInstPrinter(MAI, MII, MRI) {}
// Autogenerated by tblgen.
void printInstruction(const MCInst *MI, raw_ostream &O);
static const char *getRegisterName(unsigned RegNo);
void printRegName(raw_ostream &OS, unsigned RegNo) const override;
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
const MCSubtargetInfo &STI) override;
bool printAliasInstr(const MCInst *MI, raw_ostream &OS);
void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
unsigned PrintMethodIdx, raw_ostream &O);
private:
void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
template <unsigned Bits, unsigned Offset = 0>
void printUImm(const MCInst *MI, int opNum, raw_ostream &O);
void printMemOperand(const MCInst *MI, int opNum, raw_ostream &O);
void printMemOperandEA(const MCInst *MI, int opNum, raw_ostream &O);
void printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O);
void printRegisterPair(const MCInst *MI, int opNum, raw_ostream &O);
void printSHFMask(const MCInst *MI, int opNum, raw_ostream &O);
bool printAlias(const char *Str, const MCInst &MI, unsigned OpNo,
raw_ostream &OS);
bool printAlias(const char *Str, const MCInst &MI, unsigned OpNo0,
unsigned OpNo1, raw_ostream &OS);
bool printAlias(const MCInst &MI, raw_ostream &OS);
void printSaveRestore(const MCInst *MI, raw_ostream &O);
void printRegisterList(const MCInst *MI, int opNum, raw_ostream &O);
};
} // end namespace llvm
#endif

46
external/llvm/lib/Target/Mips/LLVMBuild.txt vendored
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;===- ./lib/Target/Mips/LLVMBuild.txt --------------------------*- Conf -*--===;
;
; The LLVM Compiler Infrastructure
;
; This file is distributed under the University of Illinois Open Source
; License. See LICENSE.TXT for details.
;
;===------------------------------------------------------------------------===;
;
; This is an LLVMBuild description file for the components in this subdirectory.
;
; For more information on the LLVMBuild system, please see:
;
; http://llvm.org/docs/LLVMBuild.html
;
;===------------------------------------------------------------------------===;
[common]
subdirectories = AsmParser Disassembler InstPrinter MCTargetDesc TargetInfo
[component_0]
type = TargetGroup
name = Mips
parent = Target
has_asmparser = 1
has_asmprinter = 1
has_disassembler = 1
has_jit = 1
[component_1]
type = Library
name = MipsCodeGen
parent = Mips
required_libraries =
Analysis
AsmPrinter
CodeGen
Core
MC
MipsAsmPrinter
MipsDesc
MipsInfo
SelectionDAG
Support
Target
add_to_library_groups = Mips

14
external/llvm/lib/Target/Mips/MCTargetDesc/CMakeLists.txt vendored
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@ -1,14 +0,0 @@
add_llvm_library(LLVMMipsDesc
MipsABIInfo.cpp
MipsABIFlagsSection.cpp
MipsAsmBackend.cpp
MipsELFObjectWriter.cpp
MipsELFStreamer.cpp
MipsMCAsmInfo.cpp
MipsMCCodeEmitter.cpp
MipsMCExpr.cpp
MipsMCTargetDesc.cpp
MipsNaClELFStreamer.cpp
MipsOptionRecord.cpp
MipsTargetStreamer.cpp
)

23
external/llvm/lib/Target/Mips/MCTargetDesc/LLVMBuild.txt vendored
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@ -1,23 +0,0 @@
;===- ./lib/Target/Mips/MCTargetDesc/LLVMBuild.txt -------------*- Conf -*--===;
;
; The LLVM Compiler Infrastructure
;
; This file is distributed under the University of Illinois Open Source
; License. See LICENSE.TXT for details.
;
;===------------------------------------------------------------------------===;
;
; This is an LLVMBuild description file for the components in this subdirectory.
;
; For more information on the LLVMBuild system, please see:
;
; http://llvm.org/docs/LLVMBuild.html
;
;===------------------------------------------------------------------------===;
[component_0]
type = Library
name = MipsDesc
parent = Mips
required_libraries = MC MipsAsmPrinter MipsInfo Support
add_to_library_groups = Mips

75
external/llvm/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.cpp vendored
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@ -1,75 +0,0 @@
//===- MipsABIFlagsSection.cpp - Mips ELF ABI Flags Section ---------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
#include "MCTargetDesc/MipsABIFlagsSection.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MipsABIFlags.h"
using namespace llvm;
uint8_t MipsABIFlagsSection::getFpABIValue() {
switch (FpABI) {
case FpABIKind::ANY:
return Mips::Val_GNU_MIPS_ABI_FP_ANY;
case FpABIKind::SOFT:
return Mips::Val_GNU_MIPS_ABI_FP_SOFT;
case FpABIKind::XX:
return Mips::Val_GNU_MIPS_ABI_FP_XX;
case FpABIKind::S32:
return Mips::Val_GNU_MIPS_ABI_FP_DOUBLE;
case FpABIKind::S64:
if (Is32BitABI)
return OddSPReg ? Mips::Val_GNU_MIPS_ABI_FP_64
: Mips::Val_GNU_MIPS_ABI_FP_64A;
return Mips::Val_GNU_MIPS_ABI_FP_DOUBLE;
}
llvm_unreachable("unexpected fp abi value");
}
StringRef MipsABIFlagsSection::getFpABIString(FpABIKind Value) {
switch (Value) {
case FpABIKind::XX:
return "xx";
case FpABIKind::S32:
return "32";
case FpABIKind::S64:
return "64";
default:
llvm_unreachable("unsupported fp abi value");
}
}
uint8_t MipsABIFlagsSection::getCPR1SizeValue() {
if (FpABI == FpABIKind::XX)
return (uint8_t)Mips::AFL_REG_32;
return (uint8_t)CPR1Size;
}
namespace llvm {
MCStreamer &operator<<(MCStreamer &OS, MipsABIFlagsSection &ABIFlagsSection) {
// Write out a Elf_Internal_ABIFlags_v0 struct
OS.EmitIntValue(ABIFlagsSection.getVersionValue(), 2); // version
OS.EmitIntValue(ABIFlagsSection.getISALevelValue(), 1); // isa_level
OS.EmitIntValue(ABIFlagsSection.getISARevisionValue(), 1); // isa_rev
OS.EmitIntValue(ABIFlagsSection.getGPRSizeValue(), 1); // gpr_size
OS.EmitIntValue(ABIFlagsSection.getCPR1SizeValue(), 1); // cpr1_size
OS.EmitIntValue(ABIFlagsSection.getCPR2SizeValue(), 1); // cpr2_size
OS.EmitIntValue(ABIFlagsSection.getFpABIValue(), 1); // fp_abi
OS.EmitIntValue(ABIFlagsSection.getISAExtensionValue(), 4); // isa_ext
OS.EmitIntValue(ABIFlagsSection.getASESetValue(), 4); // ases
OS.EmitIntValue(ABIFlagsSection.getFlags1Value(), 4); // flags1
OS.EmitIntValue(ABIFlagsSection.getFlags2Value(), 4); // flags2
return OS;
}
} // end namespace llvm

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//===- MipsABIFlagsSection.h - Mips ELF ABI Flags Section -------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSABIFLAGSSECTION_H
#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSABIFLAGSSECTION_H
#include "llvm/ADT/StringRef.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MipsABIFlags.h"
#include <cstdint>
namespace llvm {
class MCStreamer;
struct MipsABIFlagsSection {
// Internal representation of the fp_abi related values used in .module.
enum class FpABIKind { ANY, XX, S32, S64, SOFT };
// Version of flags structure.
uint16_t Version = 0;
// The level of the ISA: 1-5, 32, 64.
uint8_t ISALevel = 0;
// The revision of ISA: 0 for MIPS V and below, 1-n otherwise.
uint8_t ISARevision = 0;
// The size of general purpose registers.
Mips::AFL_REG GPRSize = Mips::AFL_REG_NONE;
// The size of co-processor 1 registers.
Mips::AFL_REG CPR1Size = Mips::AFL_REG_NONE;
// The size of co-processor 2 registers.
Mips::AFL_REG CPR2Size = Mips::AFL_REG_NONE;
// Processor-specific extension.
Mips::AFL_EXT ISAExtension = Mips::AFL_EXT_NONE;
// Mask of ASEs used.
uint32_t ASESet = 0;
bool OddSPReg = false;
bool Is32BitABI = false;
protected:
// The floating-point ABI.
FpABIKind FpABI = FpABIKind::ANY;
public:
MipsABIFlagsSection() = default;
uint16_t getVersionValue() { return (uint16_t)Version; }
uint8_t getISALevelValue() { return (uint8_t)ISALevel; }
uint8_t getISARevisionValue() { return (uint8_t)ISARevision; }
uint8_t getGPRSizeValue() { return (uint8_t)GPRSize; }
uint8_t getCPR1SizeValue();
uint8_t getCPR2SizeValue() { return (uint8_t)CPR2Size; }
uint8_t getFpABIValue();
uint32_t getISAExtensionValue() { return (uint32_t)ISAExtension; }
uint32_t getASESetValue() { return (uint32_t)ASESet; }
uint32_t getFlags1Value() {
uint32_t Value = 0;
if (OddSPReg)
Value |= (uint32_t)Mips::AFL_FLAGS1_ODDSPREG;
return Value;
}
uint32_t getFlags2Value() { return 0; }
FpABIKind getFpABI() { return FpABI; }
void setFpABI(FpABIKind Value, bool IsABI32Bit) {
FpABI = Value;
Is32BitABI = IsABI32Bit;
}
StringRef getFpABIString(FpABIKind Value);
template <class PredicateLibrary>
void setISALevelAndRevisionFromPredicates(const PredicateLibrary &P) {
if (P.hasMips64()) {
ISALevel = 64;
if (P.hasMips64r6())
ISARevision = 6;
else if (P.hasMips64r5())
ISARevision = 5;
else if (P.hasMips64r3())
ISARevision = 3;
else if (P.hasMips64r2())
ISARevision = 2;
else
ISARevision = 1;
} else if (P.hasMips32()) {
ISALevel = 32;
if (P.hasMips32r6())
ISARevision = 6;
else if (P.hasMips32r5())
ISARevision = 5;
else if (P.hasMips32r3())
ISARevision = 3;
else if (P.hasMips32r2())
ISARevision = 2;
else
ISARevision = 1;
} else {
ISARevision = 0;
if (P.hasMips5())
ISALevel = 5;
else if (P.hasMips4())
ISALevel = 4;
else if (P.hasMips3())
ISALevel = 3;
else if (P.hasMips2())
ISALevel = 2;
else if (P.hasMips1())
ISALevel = 1;
else
llvm_unreachable("Unknown ISA level!");
}
}
template <class PredicateLibrary>
void setGPRSizeFromPredicates(const PredicateLibrary &P) {
GPRSize = P.isGP64bit() ? Mips::AFL_REG_64 : Mips::AFL_REG_32;
}
template <class PredicateLibrary>
void setCPR1SizeFromPredicates(const PredicateLibrary &P) {
if (P.useSoftFloat())
CPR1Size = Mips::AFL_REG_NONE;
else if (P.hasMSA())
CPR1Size = Mips::AFL_REG_128;
else
CPR1Size = P.isFP64bit() ? Mips::AFL_REG_64 : Mips::AFL_REG_32;
}
template <class PredicateLibrary>
void setISAExtensionFromPredicates(const PredicateLibrary &P) {
if (P.hasCnMips())
ISAExtension = Mips::AFL_EXT_OCTEON;
else
ISAExtension = Mips::AFL_EXT_NONE;
}
template <class PredicateLibrary>
void setASESetFromPredicates(const PredicateLibrary &P) {
ASESet = 0;
if (P.hasDSP())
ASESet |= Mips::AFL_ASE_DSP;
if (P.hasDSPR2())
ASESet |= Mips::AFL_ASE_DSPR2;
if (P.hasMSA())
ASESet |= Mips::AFL_ASE_MSA;
if (P.inMicroMipsMode())
ASESet |= Mips::AFL_ASE_MICROMIPS;
if (P.inMips16Mode())
ASESet |= Mips::AFL_ASE_MIPS16;
if (P.hasMT())
ASESet |= Mips::AFL_ASE_MT;
}
template <class PredicateLibrary>
void setFpAbiFromPredicates(const PredicateLibrary &P) {
Is32BitABI = P.isABI_O32();
FpABI = FpABIKind::ANY;
if (P.useSoftFloat())
FpABI = FpABIKind::SOFT;
else if (P.isABI_N32() || P.isABI_N64())
FpABI = FpABIKind::S64;
else if (P.isABI_O32()) {
if (P.isABI_FPXX())
FpABI = FpABIKind::XX;
else if (P.isFP64bit())
FpABI = FpABIKind::S64;
else
FpABI = FpABIKind::S32;
}
}
template <class PredicateLibrary>
void setAllFromPredicates(const PredicateLibrary &P) {
setISALevelAndRevisionFromPredicates(P);
setGPRSizeFromPredicates(P);
setCPR1SizeFromPredicates(P);
setISAExtensionFromPredicates(P);
setASESetFromPredicates(P);
setFpAbiFromPredicates(P);
OddSPReg = P.useOddSPReg();
}
};
MCStreamer &operator<<(MCStreamer &OS, MipsABIFlagsSection &ABIFlagsSection);
} // end namespace llvm
#endif // LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSABIFLAGSSECTION_H

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//===---- MipsABIInfo.cpp - Information about MIPS ABI's ------------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
#include "MipsABIInfo.h"
#include "MipsRegisterInfo.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/MC/MCTargetOptions.h"
using namespace llvm;
namespace {
static const MCPhysReg O32IntRegs[4] = {Mips::A0, Mips::A1, Mips::A2, Mips::A3};
static const MCPhysReg Mips64IntRegs[8] = {
Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64};
}
ArrayRef<MCPhysReg> MipsABIInfo::GetByValArgRegs() const {
if (IsO32())
return makeArrayRef(O32IntRegs);
if (IsN32() || IsN64())
return makeArrayRef(Mips64IntRegs);
llvm_unreachable("Unhandled ABI");
}
ArrayRef<MCPhysReg> MipsABIInfo::GetVarArgRegs() const {
if (IsO32())
return makeArrayRef(O32IntRegs);
if (IsN32() || IsN64())
return makeArrayRef(Mips64IntRegs);
llvm_unreachable("Unhandled ABI");
}
unsigned MipsABIInfo::GetCalleeAllocdArgSizeInBytes(CallingConv::ID CC) const {
if (IsO32())
return CC != CallingConv::Fast ? 16 : 0;
if (IsN32() || IsN64())
return 0;
llvm_unreachable("Unhandled ABI");
}
MipsABIInfo MipsABIInfo::computeTargetABI(const Triple &TT, StringRef CPU,
const MCTargetOptions &Options) {
if (Options.getABIName().startswith("o32"))
return MipsABIInfo::O32();
if (Options.getABIName().startswith("n32"))
return MipsABIInfo::N32();
if (Options.getABIName().startswith("n64"))
return MipsABIInfo::N64();
assert(Options.getABIName().empty() && "Unknown ABI option for MIPS");
if (TT.getArch() == Triple::mips64 || TT.getArch() == Triple::mips64el)
return MipsABIInfo::N64();
return MipsABIInfo::O32();
}
unsigned MipsABIInfo::GetStackPtr() const {
return ArePtrs64bit() ? Mips::SP_64 : Mips::SP;
}
unsigned MipsABIInfo::GetFramePtr() const {
return ArePtrs64bit() ? Mips::FP_64 : Mips::FP;
}
unsigned MipsABIInfo::GetBasePtr() const {
return ArePtrs64bit() ? Mips::S7_64 : Mips::S7;
}
unsigned MipsABIInfo::GetGlobalPtr() const {
return ArePtrs64bit() ? Mips::GP_64 : Mips::GP;
}
unsigned MipsABIInfo::GetNullPtr() const {
return ArePtrs64bit() ? Mips::ZERO_64 : Mips::ZERO;
}
unsigned MipsABIInfo::GetZeroReg() const {
return AreGprs64bit() ? Mips::ZERO_64 : Mips::ZERO;
}
unsigned MipsABIInfo::GetPtrAdduOp() const {
return ArePtrs64bit() ? Mips::DADDu : Mips::ADDu;
}
unsigned MipsABIInfo::GetPtrAddiuOp() const {
return ArePtrs64bit() ? Mips::DADDiu : Mips::ADDiu;
}
unsigned MipsABIInfo::GetPtrSubuOp() const {
return ArePtrs64bit() ? Mips::DSUBu : Mips::SUBu;
}
unsigned MipsABIInfo::GetPtrAndOp() const {
return ArePtrs64bit() ? Mips::AND64 : Mips::AND;
}
unsigned MipsABIInfo::GetGPRMoveOp() const {
return ArePtrs64bit() ? Mips::OR64 : Mips::OR;
}
unsigned MipsABIInfo::GetEhDataReg(unsigned I) const {
static const unsigned EhDataReg[] = {
Mips::A0, Mips::A1, Mips::A2, Mips::A3
};
static const unsigned EhDataReg64[] = {
Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64
};
return IsN64() ? EhDataReg64[I] : EhDataReg[I];
}

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//===---- MipsABIInfo.h - Information about MIPS ABI's --------------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSABIINFO_H
#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSABIINFO_H
#include "llvm/ADT/Triple.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/MC/MCRegisterInfo.h"
namespace llvm {
template <typename T> class ArrayRef;
class MCTargetOptions;
class StringRef;
class TargetRegisterClass;
class MipsABIInfo {
public:
enum class ABI { Unknown, O32, N32, N64 };
protected:
ABI ThisABI;
public:
MipsABIInfo(ABI ThisABI) : ThisABI(ThisABI) {}
static MipsABIInfo Unknown() { return MipsABIInfo(ABI::Unknown); }
static MipsABIInfo O32() { return MipsABIInfo(ABI::O32); }
static MipsABIInfo N32() { return MipsABIInfo(ABI::N32); }
static MipsABIInfo N64() { return MipsABIInfo(ABI::N64); }
static MipsABIInfo computeTargetABI(const Triple &TT, StringRef CPU,
const MCTargetOptions &Options);
bool IsKnown() const { return ThisABI != ABI::Unknown; }
bool IsO32() const { return ThisABI == ABI::O32; }
bool IsN32() const { return ThisABI == ABI::N32; }
bool IsN64() const { return ThisABI == ABI::N64; }
ABI GetEnumValue() const { return ThisABI; }
/// The registers to use for byval arguments.
ArrayRef<MCPhysReg> GetByValArgRegs() const;
/// The registers to use for the variable argument list.
ArrayRef<MCPhysReg> GetVarArgRegs() const;
/// Obtain the size of the area allocated by the callee for arguments.
/// CallingConv::FastCall affects the value for O32.
unsigned GetCalleeAllocdArgSizeInBytes(CallingConv::ID CC) const;
/// Ordering of ABI's
/// MipsGenSubtargetInfo.inc will use this to resolve conflicts when given
/// multiple ABI options.
bool operator<(const MipsABIInfo Other) const {
return ThisABI < Other.GetEnumValue();
}
unsigned GetStackPtr() const;
unsigned GetFramePtr() const;
unsigned GetBasePtr() const;
unsigned GetGlobalPtr() const;
unsigned GetNullPtr() const;
unsigned GetZeroReg() const;
unsigned GetPtrAdduOp() const;
unsigned GetPtrAddiuOp() const;
unsigned GetPtrSubuOp() const;
unsigned GetPtrAndOp() const;
unsigned GetGPRMoveOp() const;
inline bool ArePtrs64bit() const { return IsN64(); }
inline bool AreGprs64bit() const { return IsN32() || IsN64(); }
unsigned GetEhDataReg(unsigned I) const;
};
}
#endif

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//===-- MipsAsmBackend.cpp - Mips Asm Backend ----------------------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file implements the MipsAsmBackend class.
//
//===----------------------------------------------------------------------===//
//
#include "MCTargetDesc/MipsAsmBackend.h"
#include "MCTargetDesc/MipsFixupKinds.h"
#include "MCTargetDesc/MipsMCExpr.h"
#include "MCTargetDesc/MipsMCTargetDesc.h"
#include "llvm/MC/MCAsmBackend.h"
#include "llvm/MC/MCAssembler.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCDirectives.h"
#include "llvm/MC/MCELFObjectWriter.h"
#include "llvm/MC/MCFixupKindInfo.h"
#include "llvm/MC/MCObjectWriter.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/MCTargetOptions.h"
#include "llvm/MC/MCValue.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/Format.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
// Prepare value for the target space for it
static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
MCContext &Ctx) {
unsigned Kind = Fixup.getKind();
// Add/subtract and shift
switch (Kind) {
default:
return 0;
case FK_Data_2:
case Mips::fixup_Mips_LO16:
case Mips::fixup_Mips_GPREL16:
case Mips::fixup_Mips_GPOFF_HI:
case Mips::fixup_Mips_GPOFF_LO:
case Mips::fixup_Mips_GOT_PAGE:
case Mips::fixup_Mips_GOT_OFST:
case Mips::fixup_Mips_GOT_DISP:
case Mips::fixup_Mips_GOT_LO16:
case Mips::fixup_Mips_CALL_LO16:
case Mips::fixup_MICROMIPS_LO16:
case Mips::fixup_MICROMIPS_GOT_PAGE:
case Mips::fixup_MICROMIPS_GOT_OFST:
case Mips::fixup_MICROMIPS_GOT_DISP:
case Mips::fixup_MIPS_PCLO16:
Value &= 0xffff;
break;
case FK_DTPRel_4:
case FK_DTPRel_8:
case FK_TPRel_4:
case FK_TPRel_8:
case FK_GPRel_4:
case FK_Data_4:
case FK_Data_8:
case Mips::fixup_Mips_SUB:
case Mips::fixup_MICROMIPS_SUB:
break;
case Mips::fixup_Mips_PC16:
// The displacement is then divided by 4 to give us an 18 bit
// address range. Forcing a signed division because Value can be negative.
Value = (int64_t)Value / 4;
// We now check if Value can be encoded as a 16-bit signed immediate.
if (!isInt<16>(Value)) {
Ctx.reportError(Fixup.getLoc(), "out of range PC16 fixup");
return 0;
}
break;
case Mips::fixup_MIPS_PC19_S2:
case Mips::fixup_MICROMIPS_PC19_S2:
// Forcing a signed division because Value can be negative.
Value = (int64_t)Value / 4;
// We now check if Value can be encoded as a 19-bit signed immediate.
if (!isInt<19>(Value)) {
Ctx.reportError(Fixup.getLoc(), "out of range PC19 fixup");
return 0;
}
break;
case Mips::fixup_Mips_26:
// So far we are only using this type for jumps.
// The displacement is then divided by 4 to give us an 28 bit
// address range.
Value >>= 2;
break;
case Mips::fixup_Mips_HI16:
case Mips::fixup_Mips_GOT:
case Mips::fixup_MICROMIPS_GOT16:
case Mips::fixup_Mips_GOT_HI16:
case Mips::fixup_Mips_CALL_HI16:
case Mips::fixup_MICROMIPS_HI16:
case Mips::fixup_MIPS_PCHI16:
// Get the 2nd 16-bits. Also add 1 if bit 15 is 1.
Value = ((Value + 0x8000) >> 16) & 0xffff;
break;
case Mips::fixup_Mips_HIGHER:
// Get the 3rd 16-bits.
Value = ((Value + 0x80008000LL) >> 32) & 0xffff;
break;
case Mips::fixup_Mips_HIGHEST:
// Get the 4th 16-bits.
Value = ((Value + 0x800080008000LL) >> 48) & 0xffff;
break;
case Mips::fixup_MICROMIPS_26_S1:
Value >>= 1;
break;
case Mips::fixup_MICROMIPS_PC7_S1:
Value -= 4;
// Forcing a signed division because Value can be negative.
Value = (int64_t) Value / 2;
// We now check if Value can be encoded as a 7-bit signed immediate.
if (!isInt<7>(Value)) {
Ctx.reportError(Fixup.getLoc(), "out of range PC7 fixup");
return 0;
}
break;
case Mips::fixup_MICROMIPS_PC10_S1:
Value -= 2;
// Forcing a signed division because Value can be negative.
Value = (int64_t) Value / 2;
// We now check if Value can be encoded as a 10-bit signed immediate.
if (!isInt<10>(Value)) {
Ctx.reportError(Fixup.getLoc(), "out of range PC10 fixup");
return 0;
}
break;
case Mips::fixup_MICROMIPS_PC16_S1:
Value -= 4;
// Forcing a signed division because Value can be negative.
Value = (int64_t)Value / 2;
// We now check if Value can be encoded as a 16-bit signed immediate.
if (!isInt<16>(Value)) {
Ctx.reportError(Fixup.getLoc(), "out of range PC16 fixup");
return 0;
}
break;
case Mips::fixup_MIPS_PC18_S3:
// Forcing a signed division because Value can be negative.
Value = (int64_t)Value / 8;
// We now check if Value can be encoded as a 18-bit signed immediate.
if (!isInt<18>(Value)) {
Ctx.reportError(Fixup.getLoc(), "out of range PC18 fixup");
return 0;
}
break;
case Mips::fixup_MICROMIPS_PC18_S3:
// Check alignment.
if ((Value & 7)) {
Ctx.reportError(Fixup.getLoc(), "out of range PC18 fixup");
}
// Forcing a signed division because Value can be negative.
Value = (int64_t)Value / 8;
// We now check if Value can be encoded as a 18-bit signed immediate.
if (!isInt<18>(Value)) {
Ctx.reportError(Fixup.getLoc(), "out of range PC18 fixup");
return 0;
}
break;
case Mips::fixup_MIPS_PC21_S2:
// Forcing a signed division because Value can be negative.
Value = (int64_t) Value / 4;
// We now check if Value can be encoded as a 21-bit signed immediate.
if (!isInt<21>(Value)) {
Ctx.reportError(Fixup.getLoc(), "out of range PC21 fixup");
return 0;
}
break;
case Mips::fixup_MIPS_PC26_S2:
// Forcing a signed division because Value can be negative.
Value = (int64_t) Value / 4;
// We now check if Value can be encoded as a 26-bit signed immediate.
if (!isInt<26>(Value)) {
Ctx.reportError(Fixup.getLoc(), "out of range PC26 fixup");
return 0;
}
break;
case Mips::fixup_MICROMIPS_PC26_S1:
// Forcing a signed division because Value can be negative.
Value = (int64_t)Value / 2;
// We now check if Value can be encoded as a 26-bit signed immediate.
if (!isInt<26>(Value)) {
Ctx.reportFatalError(Fixup.getLoc(), "out of range PC26 fixup");
return 0;
}
break;
case Mips::fixup_MICROMIPS_PC21_S1:
// Forcing a signed division because Value can be negative.
Value = (int64_t)Value / 2;
// We now check if Value can be encoded as a 21-bit signed immediate.
if (!isInt<21>(Value)) {
Ctx.reportError(Fixup.getLoc(), "out of range PC21 fixup");
return 0;
}
break;
}
return Value;
}
std::unique_ptr<MCObjectWriter>
MipsAsmBackend::createObjectWriter(raw_pwrite_stream &OS) const {
return createMipsELFObjectWriter(OS, TheTriple, IsN32);
}
// Little-endian fixup data byte ordering:
// mips32r2: a | b | x | x
// microMIPS: x | x | a | b
static bool needsMMLEByteOrder(unsigned Kind) {
return Kind != Mips::fixup_MICROMIPS_PC10_S1 &&
Kind >= Mips::fixup_MICROMIPS_26_S1 &&
Kind < Mips::LastTargetFixupKind;
}
// Calculate index for microMIPS specific little endian byte order
static unsigned calculateMMLEIndex(unsigned i) {
assert(i <= 3 && "Index out of range!");
return (1 - i / 2) * 2 + i % 2;
}
/// ApplyFixup - Apply the \p Value for given \p Fixup into the provided
/// data fragment, at the offset specified by the fixup and following the
/// fixup kind as appropriate.
void MipsAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
const MCValue &Target,
MutableArrayRef<char> Data, uint64_t Value,
bool IsResolved) const {
MCFixupKind Kind = Fixup.getKind();
MCContext &Ctx = Asm.getContext();
Value = adjustFixupValue(Fixup, Value, Ctx);
if (!Value)
return; // Doesn't change encoding.
// Where do we start in the object
unsigned Offset = Fixup.getOffset();
// Number of bytes we need to fixup
unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8;
// Used to point to big endian bytes
unsigned FullSize;
switch ((unsigned)Kind) {
case FK_Data_2:
case Mips::fixup_Mips_16:
case Mips::fixup_MICROMIPS_PC10_S1:
FullSize = 2;
break;
case FK_Data_8:
case Mips::fixup_Mips_64:
FullSize = 8;
break;
case FK_Data_4:
default:
FullSize = 4;
break;
}
// Grab current value, if any, from bits.
uint64_t CurVal = 0;
bool microMipsLEByteOrder = needsMMLEByteOrder((unsigned) Kind);
for (unsigned i = 0; i != NumBytes; ++i) {
unsigned Idx = IsLittle ? (microMipsLEByteOrder ? calculateMMLEIndex(i)
: i)
: (FullSize - 1 - i);
CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i*8);
}
uint64_t Mask = ((uint64_t)(-1) >>
(64 - getFixupKindInfo(Kind).TargetSize));
CurVal |= Value & Mask;
// Write out the fixed up bytes back to the code/data bits.
for (unsigned i = 0; i != NumBytes; ++i) {
unsigned Idx = IsLittle ? (microMipsLEByteOrder ? calculateMMLEIndex(i)
: i)
: (FullSize - 1 - i);
Data[Offset + Idx] = (uint8_t)((CurVal >> (i*8)) & 0xff);
}
}
Optional<MCFixupKind> MipsAsmBackend::getFixupKind(StringRef Name) const {
return StringSwitch<Optional<MCFixupKind>>(Name)
.Case("R_MIPS_NONE", (MCFixupKind)Mips::fixup_Mips_NONE)
.Case("R_MIPS_32", FK_Data_4)
.Default(MCAsmBackend::getFixupKind(Name));
}
const MCFixupKindInfo &MipsAsmBackend::
getFixupKindInfo(MCFixupKind Kind) const {
const static MCFixupKindInfo LittleEndianInfos[Mips::NumTargetFixupKinds] = {
// This table *must* be in same the order of fixup_* kinds in
// MipsFixupKinds.h.
//
// name offset bits flags
{ "fixup_Mips_NONE", 0, 0, 0 },
{ "fixup_Mips_16", 0, 16, 0 },
{ "fixup_Mips_32", 0, 32, 0 },
{ "fixup_Mips_REL32", 0, 32, 0 },
{ "fixup_Mips_26", 0, 26, 0 },
{ "fixup_Mips_HI16", 0, 16, 0 },
{ "fixup_Mips_LO16", 0, 16, 0 },
{ "fixup_Mips_GPREL16", 0, 16, 0 },
{ "fixup_Mips_LITERAL", 0, 16, 0 },
{ "fixup_Mips_GOT", 0, 16, 0 },
{ "fixup_Mips_PC16", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_Mips_CALL16", 0, 16, 0 },
{ "fixup_Mips_GPREL32", 0, 32, 0 },
{ "fixup_Mips_SHIFT5", 6, 5, 0 },
{ "fixup_Mips_SHIFT6", 6, 5, 0 },
{ "fixup_Mips_64", 0, 64, 0 },
{ "fixup_Mips_TLSGD", 0, 16, 0 },
{ "fixup_Mips_GOTTPREL", 0, 16, 0 },
{ "fixup_Mips_TPREL_HI", 0, 16, 0 },
{ "fixup_Mips_TPREL_LO", 0, 16, 0 },
{ "fixup_Mips_TLSLDM", 0, 16, 0 },
{ "fixup_Mips_DTPREL_HI", 0, 16, 0 },
{ "fixup_Mips_DTPREL_LO", 0, 16, 0 },
{ "fixup_Mips_Branch_PCRel", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_Mips_GPOFF_HI", 0, 16, 0 },
{ "fixup_Mips_GPOFF_LO", 0, 16, 0 },
{ "fixup_Mips_GOT_PAGE", 0, 16, 0 },
{ "fixup_Mips_GOT_OFST", 0, 16, 0 },
{ "fixup_Mips_GOT_DISP", 0, 16, 0 },
{ "fixup_Mips_HIGHER", 0, 16, 0 },
{ "fixup_Mips_HIGHEST", 0, 16, 0 },
{ "fixup_Mips_GOT_HI16", 0, 16, 0 },
{ "fixup_Mips_GOT_LO16", 0, 16, 0 },
{ "fixup_Mips_CALL_HI16", 0, 16, 0 },
{ "fixup_Mips_CALL_LO16", 0, 16, 0 },
{ "fixup_Mips_PC18_S3", 0, 18, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MIPS_PC19_S2", 0, 19, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MIPS_PC21_S2", 0, 21, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MIPS_PC26_S2", 0, 26, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MIPS_PCHI16", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MIPS_PCLO16", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MICROMIPS_26_S1", 0, 26, 0 },
{ "fixup_MICROMIPS_HI16", 0, 16, 0 },
{ "fixup_MICROMIPS_LO16", 0, 16, 0 },
{ "fixup_MICROMIPS_GOT16", 0, 16, 0 },
{ "fixup_MICROMIPS_PC7_S1", 0, 7, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MICROMIPS_PC10_S1", 0, 10, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MICROMIPS_PC16_S1", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MICROMIPS_PC26_S1", 0, 26, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MICROMIPS_PC19_S2", 0, 19, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MICROMIPS_PC18_S3", 0, 18, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MICROMIPS_PC21_S1", 0, 21, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MICROMIPS_CALL16", 0, 16, 0 },
{ "fixup_MICROMIPS_GOT_DISP", 0, 16, 0 },
{ "fixup_MICROMIPS_GOT_PAGE", 0, 16, 0 },
{ "fixup_MICROMIPS_GOT_OFST", 0, 16, 0 },
{ "fixup_MICROMIPS_TLS_GD", 0, 16, 0 },
{ "fixup_MICROMIPS_TLS_LDM", 0, 16, 0 },
{ "fixup_MICROMIPS_TLS_DTPREL_HI16", 0, 16, 0 },
{ "fixup_MICROMIPS_TLS_DTPREL_LO16", 0, 16, 0 },
{ "fixup_MICROMIPS_GOTTPREL", 0, 16, 0 },
{ "fixup_MICROMIPS_TLS_TPREL_HI16", 0, 16, 0 },
{ "fixup_MICROMIPS_TLS_TPREL_LO16", 0, 16, 0 },
{ "fixup_Mips_SUB", 0, 64, 0 },
{ "fixup_MICROMIPS_SUB", 0, 64, 0 }
};
const static MCFixupKindInfo BigEndianInfos[Mips::NumTargetFixupKinds] = {
// This table *must* be in same the order of fixup_* kinds in
// MipsFixupKinds.h.
//
// name offset bits flags
{ "fixup_Mips_NONE", 0, 0, 0 },
{ "fixup_Mips_16", 16, 16, 0 },
{ "fixup_Mips_32", 0, 32, 0 },
{ "fixup_Mips_REL32", 0, 32, 0 },
{ "fixup_Mips_26", 6, 26, 0 },
{ "fixup_Mips_HI16", 16, 16, 0 },
{ "fixup_Mips_LO16", 16, 16, 0 },
{ "fixup_Mips_GPREL16", 16, 16, 0 },
{ "fixup_Mips_LITERAL", 16, 16, 0 },
{ "fixup_Mips_GOT", 16, 16, 0 },
{ "fixup_Mips_PC16", 16, 16, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_Mips_CALL16", 16, 16, 0 },
{ "fixup_Mips_GPREL32", 0, 32, 0 },
{ "fixup_Mips_SHIFT5", 21, 5, 0 },
{ "fixup_Mips_SHIFT6", 21, 5, 0 },
{ "fixup_Mips_64", 0, 64, 0 },
{ "fixup_Mips_TLSGD", 16, 16, 0 },
{ "fixup_Mips_GOTTPREL", 16, 16, 0 },
{ "fixup_Mips_TPREL_HI", 16, 16, 0 },
{ "fixup_Mips_TPREL_LO", 16, 16, 0 },
{ "fixup_Mips_TLSLDM", 16, 16, 0 },
{ "fixup_Mips_DTPREL_HI", 16, 16, 0 },
{ "fixup_Mips_DTPREL_LO", 16, 16, 0 },
{ "fixup_Mips_Branch_PCRel",16, 16, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_Mips_GPOFF_HI", 16, 16, 0 },
{ "fixup_Mips_GPOFF_LO", 16, 16, 0 },
{ "fixup_Mips_GOT_PAGE", 16, 16, 0 },
{ "fixup_Mips_GOT_OFST", 16, 16, 0 },
{ "fixup_Mips_GOT_DISP", 16, 16, 0 },
{ "fixup_Mips_HIGHER", 16, 16, 0 },
{ "fixup_Mips_HIGHEST", 16, 16, 0 },
{ "fixup_Mips_GOT_HI16", 16, 16, 0 },
{ "fixup_Mips_GOT_LO16", 16, 16, 0 },
{ "fixup_Mips_CALL_HI16", 16, 16, 0 },
{ "fixup_Mips_CALL_LO16", 16, 16, 0 },
{ "fixup_Mips_PC18_S3", 14, 18, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MIPS_PC19_S2", 13, 19, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MIPS_PC21_S2", 11, 21, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MIPS_PC26_S2", 6, 26, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MIPS_PCHI16", 16, 16, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MIPS_PCLO16", 16, 16, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MICROMIPS_26_S1", 6, 26, 0 },
{ "fixup_MICROMIPS_HI16", 16, 16, 0 },
{ "fixup_MICROMIPS_LO16", 16, 16, 0 },
{ "fixup_MICROMIPS_GOT16", 16, 16, 0 },
{ "fixup_MICROMIPS_PC7_S1", 9, 7, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MICROMIPS_PC10_S1", 6, 10, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MICROMIPS_PC16_S1",16, 16, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MICROMIPS_PC26_S1", 6, 26, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MICROMIPS_PC19_S2",13, 19, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MICROMIPS_PC18_S3",14, 18, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MICROMIPS_PC21_S1",11, 21, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MICROMIPS_CALL16", 16, 16, 0 },
{ "fixup_MICROMIPS_GOT_DISP", 16, 16, 0 },
{ "fixup_MICROMIPS_GOT_PAGE", 16, 16, 0 },
{ "fixup_MICROMIPS_GOT_OFST", 16, 16, 0 },
{ "fixup_MICROMIPS_TLS_GD", 16, 16, 0 },
{ "fixup_MICROMIPS_TLS_LDM", 16, 16, 0 },
{ "fixup_MICROMIPS_TLS_DTPREL_HI16", 16, 16, 0 },
{ "fixup_MICROMIPS_TLS_DTPREL_LO16", 16, 16, 0 },
{ "fixup_MICROMIPS_GOTTPREL", 16, 16, 0 },
{ "fixup_MICROMIPS_TLS_TPREL_HI16", 16, 16, 0 },
{ "fixup_MICROMIPS_TLS_TPREL_LO16", 16, 16, 0 },
{ "fixup_Mips_SUB", 0, 64, 0 },
{ "fixup_MICROMIPS_SUB", 0, 64, 0 }
};
if (Kind < FirstTargetFixupKind)
return MCAsmBackend::getFixupKindInfo(Kind);
assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
"Invalid kind!");
if (IsLittle)
return LittleEndianInfos[Kind - FirstTargetFixupKind];
return BigEndianInfos[Kind - FirstTargetFixupKind];
}
/// WriteNopData - Write an (optimal) nop sequence of Count bytes
/// to the given output. If the target cannot generate such a sequence,
/// it should return an error.
///
/// \return - True on success.
bool MipsAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
// Check for a less than instruction size number of bytes
// FIXME: 16 bit instructions are not handled yet here.
// We shouldn't be using a hard coded number for instruction size.
// If the count is not 4-byte aligned, we must be writing data into the text
// section (otherwise we have unaligned instructions, and thus have far
// bigger problems), so just write zeros instead.
OW->WriteZeros(Count);
return true;
}
MCAsmBackend *llvm::createMipsAsmBackend(const Target &T,
const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI,
const MCTargetOptions &Options) {
return new MipsAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(),
Options.ABIName == "n32");
}

92
external/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h vendored
View File

@ -1,92 +0,0 @@
//===-- MipsAsmBackend.h - Mips Asm Backend ------------------------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file defines the MipsAsmBackend class.
//
//===----------------------------------------------------------------------===//
//
#ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSASMBACKEND_H
#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSASMBACKEND_H
#include "MCTargetDesc/MipsFixupKinds.h"
#include "llvm/ADT/Triple.h"
#include "llvm/MC/MCAsmBackend.h"
namespace llvm {
class MCAssembler;
struct MCFixupKindInfo;
class MCObjectWriter;
class MCRegisterInfo;
class Target;
class MipsAsmBackend : public MCAsmBackend {
Triple TheTriple;
bool IsLittle; // Big or little endian
bool IsN32;
public:
MipsAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT,
StringRef CPU, bool N32)
: TheTriple(TT), IsLittle(TT.isLittleEndian()), IsN32(N32) {}
std::unique_ptr<MCObjectWriter>
createObjectWriter(raw_pwrite_stream &OS) const override;
void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
const MCValue &Target, MutableArrayRef<char> Data,
uint64_t Value, bool IsResolved) const override;
Optional<MCFixupKind> getFixupKind(StringRef Name) const override;
const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
unsigned getNumFixupKinds() const override {
return Mips::NumTargetFixupKinds;
}
/// @name Target Relaxation Interfaces
/// @{
/// MayNeedRelaxation - Check whether the given instruction may need
/// relaxation.
///
/// \param Inst - The instruction to test.
bool mayNeedRelaxation(const MCInst &Inst) const override {
return false;
}
/// fixupNeedsRelaxation - Target specific predicate for whether a given
/// fixup requires the associated instruction to be relaxed.
bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
const MCRelaxableFragment *DF,
const MCAsmLayout &Layout) const override {
// FIXME.
llvm_unreachable("RelaxInstruction() unimplemented");
return false;
}
/// RelaxInstruction - Relax the instruction in the given fragment
/// to the next wider instruction.
///
/// \param Inst - The instruction to relax, which may be the same
/// as the output.
/// \param [out] Res On return, the relaxed instruction.
void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
MCInst &Res) const override {}
/// @}
bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
}; // class MipsAsmBackend
} // namespace
#endif

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