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//===- HexagonGenExtract.cpp ----------------------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/ADT/APInt.h"
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#include "llvm/ADT/GraphTraits.h"
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#include "llvm/IR/BasicBlock.h"
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#include "llvm/IR/CFG.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/Dominators.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/IRBuilder.h"
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#include "llvm/IR/Instruction.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/IR/PatternMatch.h"
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#include "llvm/IR/Type.h"
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#include "llvm/IR/Value.h"
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#include "llvm/Pass.h"
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#include "llvm/Support/CommandLine.h"
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#include <algorithm>
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#include <cstdint>
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#include <iterator>
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using namespace llvm;
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static cl::opt<unsigned> ExtractCutoff("extract-cutoff", cl::init(~0U),
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cl::Hidden, cl::desc("Cutoff for generating \"extract\""
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" instructions"));
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// This prevents generating extract instructions that have the offset of 0.
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// One of the reasons for "extract" is to put a sequence of bits in a regis-
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// ter, starting at offset 0 (so that these bits can then be used by an
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// "insert"). If the bits are already at offset 0, it is better not to gene-
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// rate "extract", since logical bit operations can be merged into compound
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// instructions (as opposed to "extract").
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static cl::opt<bool> NoSR0("extract-nosr0", cl::init(true), cl::Hidden,
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cl::desc("No extract instruction with offset 0"));
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static cl::opt<bool> NeedAnd("extract-needand", cl::init(true), cl::Hidden,
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cl::desc("Require & in extract patterns"));
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namespace llvm {
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void initializeHexagonGenExtractPass(PassRegistry&);
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FunctionPass *createHexagonGenExtract();
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} // end namespace llvm
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namespace {
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class HexagonGenExtract : public FunctionPass {
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public:
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static char ID;
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HexagonGenExtract() : FunctionPass(ID) {
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initializeHexagonGenExtractPass(*PassRegistry::getPassRegistry());
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}
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StringRef getPassName() const override {
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return "Hexagon generate \"extract\" instructions";
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}
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bool runOnFunction(Function &F) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.addRequired<DominatorTreeWrapperPass>();
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AU.addPreserved<DominatorTreeWrapperPass>();
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FunctionPass::getAnalysisUsage(AU);
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}
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private:
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bool visitBlock(BasicBlock *B);
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bool convert(Instruction *In);
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unsigned ExtractCount = 0;
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DominatorTree *DT;
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};
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} // end anonymous namespace
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char HexagonGenExtract::ID = 0;
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INITIALIZE_PASS_BEGIN(HexagonGenExtract, "hextract", "Hexagon generate "
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"\"extract\" instructions", false, false)
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INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
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INITIALIZE_PASS_END(HexagonGenExtract, "hextract", "Hexagon generate "
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"\"extract\" instructions", false, false)
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bool HexagonGenExtract::convert(Instruction *In) {
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using namespace PatternMatch;
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Value *BF = nullptr;
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ConstantInt *CSL = nullptr, *CSR = nullptr, *CM = nullptr;
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BasicBlock *BB = In->getParent();
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LLVMContext &Ctx = BB->getContext();
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bool LogicalSR;
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// (and (shl (lshr x, #sr), #sl), #m)
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LogicalSR = true;
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bool Match = match(In, m_And(m_Shl(m_LShr(m_Value(BF), m_ConstantInt(CSR)),
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m_ConstantInt(CSL)),
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m_ConstantInt(CM)));
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if (!Match) {
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// (and (shl (ashr x, #sr), #sl), #m)
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LogicalSR = false;
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Match = match(In, m_And(m_Shl(m_AShr(m_Value(BF), m_ConstantInt(CSR)),
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m_ConstantInt(CSL)),
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m_ConstantInt(CM)));
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}
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if (!Match) {
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// (and (shl x, #sl), #m)
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LogicalSR = true;
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CSR = ConstantInt::get(Type::getInt32Ty(Ctx), 0);
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Match = match(In, m_And(m_Shl(m_Value(BF), m_ConstantInt(CSL)),
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m_ConstantInt(CM)));
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if (Match && NoSR0)
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return false;
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}
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if (!Match) {
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// (and (lshr x, #sr), #m)
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LogicalSR = true;
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CSL = ConstantInt::get(Type::getInt32Ty(Ctx), 0);
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Match = match(In, m_And(m_LShr(m_Value(BF), m_ConstantInt(CSR)),
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m_ConstantInt(CM)));
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}
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if (!Match) {
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// (and (ashr x, #sr), #m)
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LogicalSR = false;
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CSL = ConstantInt::get(Type::getInt32Ty(Ctx), 0);
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Match = match(In, m_And(m_AShr(m_Value(BF), m_ConstantInt(CSR)),
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m_ConstantInt(CM)));
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}
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if (!Match) {
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CM = nullptr;
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// (shl (lshr x, #sr), #sl)
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LogicalSR = true;
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Match = match(In, m_Shl(m_LShr(m_Value(BF), m_ConstantInt(CSR)),
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m_ConstantInt(CSL)));
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}
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if (!Match) {
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CM = nullptr;
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// (shl (ashr x, #sr), #sl)
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LogicalSR = false;
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Match = match(In, m_Shl(m_AShr(m_Value(BF), m_ConstantInt(CSR)),
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m_ConstantInt(CSL)));
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}
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if (!Match)
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return false;
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Type *Ty = BF->getType();
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if (!Ty->isIntegerTy())
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return false;
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unsigned BW = Ty->getPrimitiveSizeInBits();
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if (BW != 32 && BW != 64)
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return false;
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uint32_t SR = CSR->getZExtValue();
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uint32_t SL = CSL->getZExtValue();
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if (!CM) {
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// If there was no and, and the shift left did not remove all potential
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// sign bits created by the shift right, then extractu cannot reproduce
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// this value.
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if (!LogicalSR && (SR > SL))
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return false;
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APInt A = APInt(BW, ~0ULL).lshr(SR).shl(SL);
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CM = ConstantInt::get(Ctx, A);
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}
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// CM is the shifted-left mask. Shift it back right to remove the zero
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// bits on least-significant positions.
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APInt M = CM->getValue().lshr(SL);
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uint32_t T = M.countTrailingOnes();
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// During the shifts some of the bits will be lost. Calculate how many
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// of the original value will remain after shift right and then left.
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uint32_t U = BW - std::max(SL, SR);
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// The width of the extracted field is the minimum of the original bits
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// that remain after the shifts and the number of contiguous 1s in the mask.
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uint32_t W = std::min(U, T);
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if (W == 0)
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return false;
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// Check if the extracted bits are contained within the mask that it is
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// and-ed with. The extract operation will copy these bits, and so the
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// mask cannot any holes in it that would clear any of the bits of the
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// extracted field.
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if (!LogicalSR) {
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// If the shift right was arithmetic, it could have included some 1 bits.
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// It is still ok to generate extract, but only if the mask eliminates
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// those bits (i.e. M does not have any bits set beyond U).
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APInt C = APInt::getHighBitsSet(BW, BW-U);
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if (M.intersects(C) || !M.isMask(W))
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return false;
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} else {
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// Check if M starts with a contiguous sequence of W times 1 bits. Get
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// the low U bits of M (which eliminates the 0 bits shifted in on the
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// left), and check if the result is APInt's "mask":
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if (!M.getLoBits(U).isMask(W))
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return false;
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}
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IRBuilder<> IRB(In);
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Intrinsic::ID IntId = (BW == 32) ? Intrinsic::hexagon_S2_extractu
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: Intrinsic::hexagon_S2_extractup;
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Module *Mod = BB->getParent()->getParent();
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Value *ExtF = Intrinsic::getDeclaration(Mod, IntId);
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Value *NewIn = IRB.CreateCall(ExtF, {BF, IRB.getInt32(W), IRB.getInt32(SR)});
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if (SL != 0)
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NewIn = IRB.CreateShl(NewIn, SL, CSL->getName());
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In->replaceAllUsesWith(NewIn);
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return true;
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}
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bool HexagonGenExtract::visitBlock(BasicBlock *B) {
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// Depth-first, bottom-up traversal.
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for (auto *DTN : children<DomTreeNode*>(DT->getNode(B)))
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visitBlock(DTN->getBlock());
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// Allow limiting the number of generated extracts for debugging purposes.
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bool HasCutoff = ExtractCutoff.getPosition();
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unsigned Cutoff = ExtractCutoff;
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bool Changed = false;
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BasicBlock::iterator I = std::prev(B->end()), NextI, Begin = B->begin();
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while (true) {
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if (HasCutoff && (ExtractCount >= Cutoff))
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return Changed;
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bool Last = (I == Begin);
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if (!Last)
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NextI = std::prev(I);
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Instruction *In = &*I;
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bool Done = convert(In);
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if (HasCutoff && Done)
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ExtractCount++;
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Changed |= Done;
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if (Last)
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break;
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I = NextI;
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}
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return Changed;
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}
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bool HexagonGenExtract::runOnFunction(Function &F) {
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if (skipFunction(F))
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return false;
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DT = &getAnalysis<DominatorTreeWrapperPass>().getDomTree();
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bool Changed;
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// Traverse the function bottom-up, to see super-expressions before their
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// sub-expressions.
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BasicBlock *Entry = GraphTraits<Function*>::getEntryNode(&F);
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Changed = visitBlock(Entry);
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return Changed;
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}
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FunctionPass *llvm::createHexagonGenExtract() {
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return new HexagonGenExtract();
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}
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