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Imported Upstream version 5.18.0.167
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//===-- BPFMCCodeEmitter.cpp - Convert BPF code to machine code -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the BPFMCCodeEmitter class.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/BPFMCTargetDesc.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCFixup.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/Endian.h"
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#include "llvm/Support/EndianStream.h"
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#include <cassert>
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#include <cstdint>
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using namespace llvm;
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#define DEBUG_TYPE "mccodeemitter"
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namespace {
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class BPFMCCodeEmitter : public MCCodeEmitter {
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const MCInstrInfo &MCII;
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const MCRegisterInfo &MRI;
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bool IsLittleEndian;
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public:
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BPFMCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri,
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bool IsLittleEndian)
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: MCII(mcii), MRI(mri), IsLittleEndian(IsLittleEndian) {}
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BPFMCCodeEmitter(const BPFMCCodeEmitter &) = delete;
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void operator=(const BPFMCCodeEmitter &) = delete;
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~BPFMCCodeEmitter() override = default;
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// getBinaryCodeForInstr - TableGen'erated function for getting the
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// binary encoding for an instruction.
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uint64_t getBinaryCodeForInstr(const MCInst &MI,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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// getMachineOpValue - Return binary encoding of operand. If the machin
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// operand requires relocation, record the relocation and return zero.
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unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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uint64_t getMemoryOpValue(const MCInst &MI, unsigned Op,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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void encodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const override;
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private:
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uint64_t computeAvailableFeatures(const FeatureBitset &FB) const;
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void verifyInstructionPredicates(const MCInst &MI,
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uint64_t AvailableFeatures) const;
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};
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} // end anonymous namespace
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MCCodeEmitter *llvm::createBPFMCCodeEmitter(const MCInstrInfo &MCII,
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const MCRegisterInfo &MRI,
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MCContext &Ctx) {
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return new BPFMCCodeEmitter(MCII, MRI, true);
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}
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MCCodeEmitter *llvm::createBPFbeMCCodeEmitter(const MCInstrInfo &MCII,
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const MCRegisterInfo &MRI,
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MCContext &Ctx) {
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return new BPFMCCodeEmitter(MCII, MRI, false);
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}
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unsigned BPFMCCodeEmitter::getMachineOpValue(const MCInst &MI,
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const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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if (MO.isReg())
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return MRI.getEncodingValue(MO.getReg());
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if (MO.isImm())
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return static_cast<unsigned>(MO.getImm());
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assert(MO.isExpr());
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const MCExpr *Expr = MO.getExpr();
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assert(Expr->getKind() == MCExpr::SymbolRef);
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if (MI.getOpcode() == BPF::JAL)
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// func call name
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Fixups.push_back(MCFixup::create(0, Expr, FK_PCRel_4));
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else if (MI.getOpcode() == BPF::LD_imm64)
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Fixups.push_back(MCFixup::create(0, Expr, FK_SecRel_8));
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else
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// bb label
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Fixups.push_back(MCFixup::create(0, Expr, FK_PCRel_2));
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return 0;
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}
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static uint8_t SwapBits(uint8_t Val)
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{
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return (Val & 0x0F) << 4 | (Val & 0xF0) >> 4;
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}
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void BPFMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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verifyInstructionPredicates(MI,
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computeAvailableFeatures(STI.getFeatureBits()));
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unsigned Opcode = MI.getOpcode();
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support::endian::Writer<support::little> LE(OS);
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support::endian::Writer<support::big> BE(OS);
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if (Opcode == BPF::LD_imm64 || Opcode == BPF::LD_pseudo) {
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uint64_t Value = getBinaryCodeForInstr(MI, Fixups, STI);
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LE.write<uint8_t>(Value >> 56);
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if (IsLittleEndian)
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LE.write<uint8_t>((Value >> 48) & 0xff);
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else
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LE.write<uint8_t>(SwapBits((Value >> 48) & 0xff));
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LE.write<uint16_t>(0);
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if (IsLittleEndian)
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LE.write<uint32_t>(Value & 0xffffFFFF);
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else
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BE.write<uint32_t>(Value & 0xffffFFFF);
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const MCOperand &MO = MI.getOperand(1);
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uint64_t Imm = MO.isImm() ? MO.getImm() : 0;
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LE.write<uint8_t>(0);
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LE.write<uint8_t>(0);
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LE.write<uint16_t>(0);
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if (IsLittleEndian)
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LE.write<uint32_t>(Imm >> 32);
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else
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BE.write<uint32_t>(Imm >> 32);
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} else {
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// Get instruction encoding and emit it
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uint64_t Value = getBinaryCodeForInstr(MI, Fixups, STI);
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LE.write<uint8_t>(Value >> 56);
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if (IsLittleEndian) {
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LE.write<uint8_t>((Value >> 48) & 0xff);
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LE.write<uint16_t>((Value >> 32) & 0xffff);
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LE.write<uint32_t>(Value & 0xffffFFFF);
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} else {
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LE.write<uint8_t>(SwapBits((Value >> 48) & 0xff));
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BE.write<uint16_t>((Value >> 32) & 0xffff);
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BE.write<uint32_t>(Value & 0xffffFFFF);
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}
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}
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}
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// Encode BPF Memory Operand
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uint64_t BPFMCCodeEmitter::getMemoryOpValue(const MCInst &MI, unsigned Op,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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uint64_t Encoding;
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const MCOperand Op1 = MI.getOperand(1);
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assert(Op1.isReg() && "First operand is not register.");
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Encoding = MRI.getEncodingValue(Op1.getReg());
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Encoding <<= 16;
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MCOperand Op2 = MI.getOperand(2);
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assert(Op2.isImm() && "Second operand is not immediate.");
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Encoding |= Op2.getImm() & 0xffff;
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return Encoding;
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}
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#define ENABLE_INSTR_PREDICATE_VERIFIER
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#include "BPFGenMCCodeEmitter.inc"
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