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Imported Upstream version 5.18.0.167
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//===-- ARMBaseInfo.cpp - ARM Base encoding information------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides basic encoding and assembly information for ARM.
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//
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//===----------------------------------------------------------------------===//
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#include "ARMBaseInfo.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/SmallVector.h"
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using namespace llvm;
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namespace llvm {
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namespace ARMSysReg {
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// lookup system register using 12-bit SYSm value.
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// Note: the search is uniqued using M1 mask
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const MClassSysReg *lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm) {
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return lookupMClassSysRegByM1Encoding12(SYSm);
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}
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// returns APSR with _<bits> qualifier.
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// Note: ARMv7-M deprecates using MSR APSR without a _<bits> qualifier
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const MClassSysReg *lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm) {
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return lookupMClassSysRegByM2M3Encoding8((1<<9)|(SYSm & 0xFF));
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}
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// lookup system registers using 8-bit SYSm value
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const MClassSysReg *lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm) {
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return ARMSysReg::lookupMClassSysRegByM2M3Encoding8((1<<8)|(SYSm & 0xFF));
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}
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#define GET_MCLASSSYSREG_IMPL
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#include "ARMGenSystemRegister.inc"
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} // end namespace ARMSysReg
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namespace ARMBankedReg {
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#define GET_BANKEDREG_IMPL
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#include "ARMGenSystemRegister.inc"
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} // end namespce ARMSysReg
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} // end namespace llvm
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161
external/llvm/lib/Target/ARM/Utils/ARMBaseInfo.h
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161
external/llvm/lib/Target/ARM/Utils/ARMBaseInfo.h
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//===-- ARMBaseInfo.h - Top level definitions for ARM ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains small standalone helper functions and enum definitions for
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// the ARM target useful for the compiler back-end and the MC libraries.
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// As such, it deliberately does not include references to LLVM core
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// code gen types, passes, etc..
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_ARM_UTILS_ARMBASEINFO_H
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#define LLVM_LIB_TARGET_ARM_UTILS_ARMBASEINFO_H
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/MC/SubtargetFeature.h"
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#include "MCTargetDesc/ARMMCTargetDesc.h"
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namespace llvm {
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// Enums corresponding to ARM condition codes
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namespace ARMCC {
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// The CondCodes constants map directly to the 4-bit encoding of the
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// condition field for predicated instructions.
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enum CondCodes { // Meaning (integer) Meaning (floating-point)
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EQ, // Equal Equal
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NE, // Not equal Not equal, or unordered
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HS, // Carry set >, ==, or unordered
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LO, // Carry clear Less than
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MI, // Minus, negative Less than
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PL, // Plus, positive or zero >, ==, or unordered
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VS, // Overflow Unordered
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VC, // No overflow Not unordered
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HI, // Unsigned higher Greater than, or unordered
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LS, // Unsigned lower or same Less than or equal
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GE, // Greater than or equal Greater than or equal
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LT, // Less than Less than, or unordered
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GT, // Greater than Greater than
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LE, // Less than or equal <, ==, or unordered
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AL // Always (unconditional) Always (unconditional)
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};
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inline static CondCodes getOppositeCondition(CondCodes CC) {
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switch (CC) {
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default: llvm_unreachable("Unknown condition code");
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case EQ: return NE;
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case NE: return EQ;
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case HS: return LO;
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case LO: return HS;
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case MI: return PL;
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case PL: return MI;
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case VS: return VC;
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case VC: return VS;
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case HI: return LS;
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case LS: return HI;
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case GE: return LT;
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case LT: return GE;
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case GT: return LE;
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case LE: return GT;
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}
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}
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} // end namespace ARMCC
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inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
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switch (CC) {
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case ARMCC::EQ: return "eq";
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case ARMCC::NE: return "ne";
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case ARMCC::HS: return "hs";
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case ARMCC::LO: return "lo";
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case ARMCC::MI: return "mi";
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case ARMCC::PL: return "pl";
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case ARMCC::VS: return "vs";
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case ARMCC::VC: return "vc";
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case ARMCC::HI: return "hi";
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case ARMCC::LS: return "ls";
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case ARMCC::GE: return "ge";
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case ARMCC::LT: return "lt";
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case ARMCC::GT: return "gt";
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case ARMCC::LE: return "le";
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case ARMCC::AL: return "al";
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}
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llvm_unreachable("Unknown condition code");
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}
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inline static unsigned ARMCondCodeFromString(StringRef CC) {
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return StringSwitch<unsigned>(CC.lower())
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.Case("eq", ARMCC::EQ)
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.Case("ne", ARMCC::NE)
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.Case("hs", ARMCC::HS)
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.Case("cs", ARMCC::HS)
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.Case("lo", ARMCC::LO)
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.Case("cc", ARMCC::LO)
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.Case("mi", ARMCC::MI)
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.Case("pl", ARMCC::PL)
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.Case("vs", ARMCC::VS)
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.Case("vc", ARMCC::VC)
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.Case("hi", ARMCC::HI)
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.Case("ls", ARMCC::LS)
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.Case("ge", ARMCC::GE)
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.Case("lt", ARMCC::LT)
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.Case("gt", ARMCC::GT)
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.Case("le", ARMCC::LE)
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.Case("al", ARMCC::AL)
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.Default(~0U);
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}
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// System Registers
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namespace ARMSysReg {
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struct MClassSysReg {
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const char *Name;
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uint16_t M1Encoding12;
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uint16_t M2M3Encoding8;
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uint16_t Encoding;
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FeatureBitset FeaturesRequired;
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// return true if FeaturesRequired are all present in ActiveFeatures
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bool hasRequiredFeatures(FeatureBitset ActiveFeatures) const {
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return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
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}
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// returns true if TestFeatures are all present in FeaturesRequired
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bool isInRequiredFeatures(FeatureBitset TestFeatures) const {
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return (FeaturesRequired & TestFeatures) == TestFeatures;
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}
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};
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#define GET_MCLASSSYSREG_DECL
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#include "ARMGenSystemRegister.inc"
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// lookup system register using 12-bit SYSm value.
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// Note: the search is uniqued using M1 mask
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const MClassSysReg *lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm);
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// returns APSR with _<bits> qualifier.
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// Note: ARMv7-M deprecates using MSR APSR without a _<bits> qualifier
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const MClassSysReg *lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm);
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// lookup system registers using 8-bit SYSm value
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const MClassSysReg *lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm);
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} // end namespace ARMSysReg
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// Banked Registers
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namespace ARMBankedReg {
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struct BankedReg {
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const char *Name;
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uint16_t Encoding;
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};
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#define GET_BANKEDREG_DECL
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#include "ARMGenSystemRegister.inc"
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} // end namespace ARMBankedReg
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_ARM_UTILS_ARMBASEINFO_H
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@ -1,3 +0,0 @@
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add_llvm_library(LLVMARMUtils
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ARMBaseInfo.cpp
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)
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24
external/llvm/lib/Target/ARM/Utils/LLVMBuild.txt
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external/llvm/lib/Target/ARM/Utils/LLVMBuild.txt
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;===- ./lib/Target/ARM/Utils/LLVMBuild.txt ----------------*- Conf -*--===;
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;
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; The LLVM Compiler Infrastructure
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;
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; This file is distributed under the University of Illinois Open Source
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; License. See LICENSE.TXT for details.
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;
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;===------------------------------------------------------------------------===;
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;
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; This is an LLVMBuild description file for the components in this subdirectory.
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;
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; For more information on the LLVMBuild system, please see:
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;
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; http://llvm.org/docs/LLVMBuild.html
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;
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;===------------------------------------------------------------------------===;
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[component_0]
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type = Library
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name = ARMUtils
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parent = ARM
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required_libraries = Support
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add_to_library_groups = ARM
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