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external/llvm/lib/Target/ARC/ARCISelDAGToDAG.cpp
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external/llvm/lib/Target/ARC/ARCISelDAGToDAG.cpp
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//===- ARCISelDAGToDAG.cpp - ARC dag to dag inst selector -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the ARC target.
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//
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//===----------------------------------------------------------------------===//
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#include "ARC.h"
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#include "ARCTargetMachine.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/CodeGen/TargetLowering.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/IR/LLVMContext.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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/// ARCDAGToDAGISel - ARC specific code to select ARC machine
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/// instructions for SelectionDAG operations.
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namespace {
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class ARCDAGToDAGISel : public SelectionDAGISel {
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public:
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ARCDAGToDAGISel(ARCTargetMachine &TM, CodeGenOpt::Level OptLevel)
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: SelectionDAGISel(TM, OptLevel) {}
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void Select(SDNode *N) override;
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// Complex Pattern Selectors.
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bool SelectFrameADDR_ri(SDValue Addr, SDValue &Base, SDValue &Offset);
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bool SelectAddrModeS9(SDValue Addr, SDValue &Base, SDValue &Offset);
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bool SelectAddrModeImm(SDValue Addr, SDValue &Base, SDValue &Offset);
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bool SelectAddrModeFar(SDValue Addr, SDValue &Base, SDValue &Offset);
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bool SelectCMOVPred(SDValue N, SDValue &Pred, SDValue &Reg) {
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const ConstantSDNode *CN = cast<ConstantSDNode>(N);
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Pred = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(N), MVT::i32);
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Reg = CurDAG->getRegister(ARC::STATUS32, MVT::i32);
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return true;
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}
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StringRef getPassName() const override {
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return "ARC DAG->DAG Pattern Instruction Selection";
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}
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// Include the pieces autogenerated from the target description.
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#include "ARCGenDAGISel.inc"
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};
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} // end anonymous namespace
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/// This pass converts a legalized DAG into a ARC-specific DAG, ready for
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/// instruction scheduling.
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FunctionPass *llvm::createARCISelDag(ARCTargetMachine &TM,
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CodeGenOpt::Level OptLevel) {
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return new ARCDAGToDAGISel(TM, OptLevel);
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}
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bool ARCDAGToDAGISel::SelectAddrModeImm(SDValue Addr, SDValue &Base,
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SDValue &Offset) {
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if (Addr.getOpcode() == ARCISD::GAWRAPPER) {
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Base = Addr.getOperand(0);
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Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
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return true;
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}
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return false;
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}
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bool ARCDAGToDAGISel::SelectAddrModeS9(SDValue Addr, SDValue &Base,
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SDValue &Offset) {
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if (Addr.getOpcode() == ARCISD::GAWRAPPER) {
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return false;
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}
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if (Addr.getOpcode() != ISD::ADD && Addr.getOpcode() != ISD::SUB &&
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!CurDAG->isBaseWithConstantOffset(Addr)) {
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if (Addr.getOpcode() == ISD::FrameIndex) {
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// Match frame index.
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int FI = cast<FrameIndexSDNode>(Addr)->getIndex();
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Base = CurDAG->getTargetFrameIndex(
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FI, TLI->getPointerTy(CurDAG->getDataLayout()));
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} else {
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Base = Addr;
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}
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Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
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return true;
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}
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if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
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int32_t RHSC = RHS->getSExtValue();
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if (Addr.getOpcode() == ISD::SUB)
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RHSC = -RHSC;
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// Do we need more than 9 bits to encode?
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if (!isInt<9>(RHSC))
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return false;
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Base = Addr.getOperand(0);
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if (Base.getOpcode() == ISD::FrameIndex) {
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int FI = cast<FrameIndexSDNode>(Base)->getIndex();
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Base = CurDAG->getTargetFrameIndex(
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FI, TLI->getPointerTy(CurDAG->getDataLayout()));
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}
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Offset = CurDAG->getTargetConstant(RHSC, SDLoc(Addr), MVT::i32);
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return true;
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}
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Base = Addr;
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Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
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return true;
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}
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bool ARCDAGToDAGISel::SelectAddrModeFar(SDValue Addr, SDValue &Base,
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SDValue &Offset) {
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if (SelectAddrModeS9(Addr, Base, Offset))
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return false;
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if (Addr.getOpcode() == ARCISD::GAWRAPPER) {
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return false;
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}
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if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
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int32_t RHSC = RHS->getSExtValue();
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if (Addr.getOpcode() == ISD::SUB)
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RHSC = -RHSC;
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Base = Addr.getOperand(0);
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Offset = CurDAG->getTargetConstant(RHSC, SDLoc(Addr), MVT::i32);
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return true;
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}
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return false;
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}
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// Is this a legal frame index addressing expression.
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bool ARCDAGToDAGISel::SelectFrameADDR_ri(SDValue Addr, SDValue &Base,
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SDValue &Offset) {
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FrameIndexSDNode *FIN = nullptr;
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if ((FIN = dyn_cast<FrameIndexSDNode>(Addr))) {
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
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Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
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return true;
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}
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if (Addr.getOpcode() == ISD::ADD) {
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ConstantSDNode *CN = nullptr;
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if ((FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) &&
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(CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) &&
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(CN->getSExtValue() % 4 == 0 && CN->getSExtValue() >= 0)) {
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// Constant positive word offset from frame index
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
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Offset =
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CurDAG->getTargetConstant(CN->getSExtValue(), SDLoc(Addr), MVT::i32);
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return true;
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}
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}
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return false;
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}
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void ARCDAGToDAGISel::Select(SDNode *N) {
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switch (N->getOpcode()) {
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case ISD::Constant: {
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uint64_t CVal = cast<ConstantSDNode>(N)->getZExtValue();
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ReplaceNode(N, CurDAG->getMachineNode(
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isInt<12>(CVal) ? ARC::MOV_rs12 : ARC::MOV_rlimm,
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SDLoc(N), MVT::i32,
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CurDAG->getTargetConstant(CVal, SDLoc(N), MVT::i32)));
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return;
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}
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}
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SelectCode(N);
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}
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