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//===-- R600ClauseMergePass - Merge consecutive CF_ALU -------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// R600EmitClauseMarker pass emits CFAlu instruction in a conservative maneer.
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/// This pass is merging consecutive CFAlus where applicable.
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/// It needs to be called after IfCvt for best results.
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "AMDGPUSubtarget.h"
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#include "R600Defines.h"
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#include "R600InstrInfo.h"
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#include "R600MachineFunctionInfo.h"
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#include "R600RegisterInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "r600mergeclause"
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namespace {
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static bool isCFAlu(const MachineInstr &MI) {
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switch (MI.getOpcode()) {
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case AMDGPU::CF_ALU:
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case AMDGPU::CF_ALU_PUSH_BEFORE:
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return true;
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default:
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return false;
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}
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}
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class R600ClauseMergePass : public MachineFunctionPass {
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private:
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const R600InstrInfo *TII;
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unsigned getCFAluSize(const MachineInstr &MI) const;
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bool isCFAluEnabled(const MachineInstr &MI) const;
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/// IfCvt pass can generate "disabled" ALU clause marker that need to be
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/// removed and their content affected to the previous alu clause.
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/// This function parse instructions after CFAlu until it find a disabled
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/// CFAlu and merge the content, or an enabled CFAlu.
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void cleanPotentialDisabledCFAlu(MachineInstr &CFAlu) const;
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/// Check whether LatrCFAlu can be merged into RootCFAlu and do it if
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/// it is the case.
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bool mergeIfPossible(MachineInstr &RootCFAlu,
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const MachineInstr &LatrCFAlu) const;
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public:
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static char ID;
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R600ClauseMergePass() : MachineFunctionPass(ID) { }
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bool runOnMachineFunction(MachineFunction &MF) override;
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StringRef getPassName() const override;
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};
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} // end anonymous namespace
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INITIALIZE_PASS_BEGIN(R600ClauseMergePass, DEBUG_TYPE,
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"R600 Clause Merge", false, false)
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INITIALIZE_PASS_END(R600ClauseMergePass, DEBUG_TYPE,
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"R600 Clause Merge", false, false)
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char R600ClauseMergePass::ID = 0;
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char &llvm::R600ClauseMergePassID = R600ClauseMergePass::ID;
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unsigned R600ClauseMergePass::getCFAluSize(const MachineInstr &MI) const {
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assert(isCFAlu(MI));
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return MI
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.getOperand(TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::COUNT))
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.getImm();
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}
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bool R600ClauseMergePass::isCFAluEnabled(const MachineInstr &MI) const {
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assert(isCFAlu(MI));
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return MI
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.getOperand(TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::Enabled))
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.getImm();
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}
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void R600ClauseMergePass::cleanPotentialDisabledCFAlu(
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MachineInstr &CFAlu) const {
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int CntIdx = TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::COUNT);
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MachineBasicBlock::iterator I = CFAlu, E = CFAlu.getParent()->end();
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I++;
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do {
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while (I != E && !isCFAlu(*I))
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I++;
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if (I == E)
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return;
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MachineInstr &MI = *I++;
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if (isCFAluEnabled(MI))
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break;
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CFAlu.getOperand(CntIdx).setImm(getCFAluSize(CFAlu) + getCFAluSize(MI));
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MI.eraseFromParent();
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} while (I != E);
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}
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bool R600ClauseMergePass::mergeIfPossible(MachineInstr &RootCFAlu,
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const MachineInstr &LatrCFAlu) const {
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assert(isCFAlu(RootCFAlu) && isCFAlu(LatrCFAlu));
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int CntIdx = TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::COUNT);
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unsigned RootInstCount = getCFAluSize(RootCFAlu),
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LaterInstCount = getCFAluSize(LatrCFAlu);
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unsigned CumuledInsts = RootInstCount + LaterInstCount;
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if (CumuledInsts >= TII->getMaxAlusPerClause()) {
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DEBUG(dbgs() << "Excess inst counts\n");
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return false;
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}
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if (RootCFAlu.getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE)
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return false;
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// Is KCache Bank 0 compatible ?
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int Mode0Idx =
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TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_MODE0);
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int KBank0Idx =
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TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_BANK0);
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int KBank0LineIdx =
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TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_ADDR0);
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if (LatrCFAlu.getOperand(Mode0Idx).getImm() &&
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RootCFAlu.getOperand(Mode0Idx).getImm() &&
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(LatrCFAlu.getOperand(KBank0Idx).getImm() !=
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RootCFAlu.getOperand(KBank0Idx).getImm() ||
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LatrCFAlu.getOperand(KBank0LineIdx).getImm() !=
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RootCFAlu.getOperand(KBank0LineIdx).getImm())) {
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DEBUG(dbgs() << "Wrong KC0\n");
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return false;
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}
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// Is KCache Bank 1 compatible ?
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int Mode1Idx =
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TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_MODE1);
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int KBank1Idx =
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TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_BANK1);
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int KBank1LineIdx =
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TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_ADDR1);
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if (LatrCFAlu.getOperand(Mode1Idx).getImm() &&
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RootCFAlu.getOperand(Mode1Idx).getImm() &&
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(LatrCFAlu.getOperand(KBank1Idx).getImm() !=
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RootCFAlu.getOperand(KBank1Idx).getImm() ||
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LatrCFAlu.getOperand(KBank1LineIdx).getImm() !=
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RootCFAlu.getOperand(KBank1LineIdx).getImm())) {
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DEBUG(dbgs() << "Wrong KC0\n");
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return false;
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}
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if (LatrCFAlu.getOperand(Mode0Idx).getImm()) {
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RootCFAlu.getOperand(Mode0Idx).setImm(
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LatrCFAlu.getOperand(Mode0Idx).getImm());
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RootCFAlu.getOperand(KBank0Idx).setImm(
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LatrCFAlu.getOperand(KBank0Idx).getImm());
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RootCFAlu.getOperand(KBank0LineIdx)
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.setImm(LatrCFAlu.getOperand(KBank0LineIdx).getImm());
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}
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if (LatrCFAlu.getOperand(Mode1Idx).getImm()) {
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RootCFAlu.getOperand(Mode1Idx).setImm(
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LatrCFAlu.getOperand(Mode1Idx).getImm());
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RootCFAlu.getOperand(KBank1Idx).setImm(
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LatrCFAlu.getOperand(KBank1Idx).getImm());
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RootCFAlu.getOperand(KBank1LineIdx)
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.setImm(LatrCFAlu.getOperand(KBank1LineIdx).getImm());
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}
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RootCFAlu.getOperand(CntIdx).setImm(CumuledInsts);
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RootCFAlu.setDesc(TII->get(LatrCFAlu.getOpcode()));
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return true;
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}
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bool R600ClauseMergePass::runOnMachineFunction(MachineFunction &MF) {
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if (skipFunction(MF.getFunction()))
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return false;
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const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>();
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TII = ST.getInstrInfo();
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for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
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BB != BB_E; ++BB) {
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MachineBasicBlock &MBB = *BB;
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MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
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MachineBasicBlock::iterator LatestCFAlu = E;
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while (I != E) {
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MachineInstr &MI = *I++;
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if ((!TII->canBeConsideredALU(MI) && !isCFAlu(MI)) ||
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TII->mustBeLastInClause(MI.getOpcode()))
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LatestCFAlu = E;
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if (!isCFAlu(MI))
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continue;
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cleanPotentialDisabledCFAlu(MI);
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if (LatestCFAlu != E && mergeIfPossible(*LatestCFAlu, MI)) {
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MI.eraseFromParent();
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} else {
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assert(MI.getOperand(8).getImm() && "CF ALU instruction disabled");
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LatestCFAlu = MI;
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}
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}
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}
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return false;
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}
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StringRef R600ClauseMergePass::getPassName() const {
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return "R600 Merge Clause Markers Pass";
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}
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llvm::FunctionPass *llvm::createR600ClauseMergePass() {
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return new R600ClauseMergePass();
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}
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