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Imported Upstream version 5.18.0.167
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//=== AArch64CallingConv.h - Custom Calling Convention Routines -*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the custom routines for the AArch64 Calling Convention
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// that aren't done by tablegen.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64CALLINGCONVENTION_H
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#define LLVM_LIB_TARGET_AARCH64_AARCH64CALLINGCONVENTION_H
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#include "AArch64.h"
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#include "AArch64InstrInfo.h"
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#include "AArch64Subtarget.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/IR/CallingConv.h"
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namespace {
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using namespace llvm;
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static const MCPhysReg XRegList[] = {AArch64::X0, AArch64::X1, AArch64::X2,
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AArch64::X3, AArch64::X4, AArch64::X5,
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AArch64::X6, AArch64::X7};
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static const MCPhysReg HRegList[] = {AArch64::H0, AArch64::H1, AArch64::H2,
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AArch64::H3, AArch64::H4, AArch64::H5,
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AArch64::H6, AArch64::H7};
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static const MCPhysReg SRegList[] = {AArch64::S0, AArch64::S1, AArch64::S2,
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AArch64::S3, AArch64::S4, AArch64::S5,
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AArch64::S6, AArch64::S7};
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static const MCPhysReg DRegList[] = {AArch64::D0, AArch64::D1, AArch64::D2,
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AArch64::D3, AArch64::D4, AArch64::D5,
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AArch64::D6, AArch64::D7};
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static const MCPhysReg QRegList[] = {AArch64::Q0, AArch64::Q1, AArch64::Q2,
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AArch64::Q3, AArch64::Q4, AArch64::Q5,
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AArch64::Q6, AArch64::Q7};
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static bool finishStackBlock(SmallVectorImpl<CCValAssign> &PendingMembers,
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MVT LocVT, ISD::ArgFlagsTy &ArgFlags,
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CCState &State, unsigned SlotAlign) {
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unsigned Size = LocVT.getSizeInBits() / 8;
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unsigned StackAlign =
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State.getMachineFunction().getDataLayout().getStackAlignment();
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unsigned Align = std::min(ArgFlags.getOrigAlign(), StackAlign);
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for (auto &It : PendingMembers) {
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It.convertToMem(State.AllocateStack(Size, std::max(Align, SlotAlign)));
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State.addLoc(It);
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SlotAlign = 1;
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}
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// All pending members have now been allocated
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PendingMembers.clear();
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return true;
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}
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/// The Darwin variadic PCS places anonymous arguments in 8-byte stack slots. An
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/// [N x Ty] type must still be contiguous in memory though.
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static bool CC_AArch64_Custom_Stack_Block(
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unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo,
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ISD::ArgFlagsTy &ArgFlags, CCState &State) {
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SmallVectorImpl<CCValAssign> &PendingMembers = State.getPendingLocs();
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// Add the argument to the list to be allocated once we know the size of the
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// block.
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PendingMembers.push_back(
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CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo));
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if (!ArgFlags.isInConsecutiveRegsLast())
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return true;
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return finishStackBlock(PendingMembers, LocVT, ArgFlags, State, 8);
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}
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/// Given an [N x Ty] block, it should be passed in a consecutive sequence of
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/// registers. If no such sequence is available, mark the rest of the registers
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/// of that type as used and place the argument on the stack.
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static bool CC_AArch64_Custom_Block(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
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CCValAssign::LocInfo &LocInfo,
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ISD::ArgFlagsTy &ArgFlags, CCState &State) {
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// Try to allocate a contiguous block of registers, each of the correct
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// size to hold one member.
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ArrayRef<MCPhysReg> RegList;
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if (LocVT.SimpleTy == MVT::i64)
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RegList = XRegList;
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else if (LocVT.SimpleTy == MVT::f16)
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RegList = HRegList;
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else if (LocVT.SimpleTy == MVT::f32 || LocVT.is32BitVector())
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RegList = SRegList;
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else if (LocVT.SimpleTy == MVT::f64 || LocVT.is64BitVector())
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RegList = DRegList;
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else if (LocVT.SimpleTy == MVT::f128 || LocVT.is128BitVector())
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RegList = QRegList;
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else {
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// Not an array we want to split up after all.
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return false;
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}
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SmallVectorImpl<CCValAssign> &PendingMembers = State.getPendingLocs();
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// Add the argument to the list to be allocated once we know the size of the
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// block.
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PendingMembers.push_back(
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CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo));
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if (!ArgFlags.isInConsecutiveRegsLast())
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return true;
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unsigned RegResult = State.AllocateRegBlock(RegList, PendingMembers.size());
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if (RegResult) {
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for (auto &It : PendingMembers) {
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It.convertToReg(RegResult);
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State.addLoc(It);
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++RegResult;
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}
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PendingMembers.clear();
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return true;
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}
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// Mark all regs in the class as unavailable
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for (auto Reg : RegList)
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State.AllocateReg(Reg);
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const AArch64Subtarget &Subtarget = static_cast<const AArch64Subtarget &>(
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State.getMachineFunction().getSubtarget());
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unsigned SlotAlign = Subtarget.isTargetDarwin() ? 1 : 8;
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return finishStackBlock(PendingMembers, LocVT, ArgFlags, State, SlotAlign);
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}
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}
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#endif
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