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Imported Upstream version 5.18.0.167
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//===--- AArch64CallLowering.cpp - Call lowering --------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file implements the lowering of LLVM calls to machine code calls for
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/// GlobalISel.
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///
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//===----------------------------------------------------------------------===//
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#include "AArch64CallLowering.h"
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#include "AArch64ISelLowering.h"
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#include "AArch64MachineFunctionInfo.h"
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#include "AArch64Subtarget.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/Analysis.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/GlobalISel/Utils.h"
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#include "llvm/CodeGen/LowLevelType.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/MachineValueType.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/IR/Argument.h"
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/Type.h"
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#include "llvm/IR/Value.h"
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#include <algorithm>
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#include <cassert>
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#include <cstdint>
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#include <iterator>
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using namespace llvm;
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AArch64CallLowering::AArch64CallLowering(const AArch64TargetLowering &TLI)
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: CallLowering(&TLI) {}
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namespace {
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struct IncomingArgHandler : public CallLowering::ValueHandler {
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IncomingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
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CCAssignFn *AssignFn)
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: ValueHandler(MIRBuilder, MRI, AssignFn), StackUsed(0) {}
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unsigned getStackAddress(uint64_t Size, int64_t Offset,
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MachinePointerInfo &MPO) override {
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auto &MFI = MIRBuilder.getMF().getFrameInfo();
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int FI = MFI.CreateFixedObject(Size, Offset, true);
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MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
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unsigned AddrReg = MRI.createGenericVirtualRegister(LLT::pointer(0, 64));
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MIRBuilder.buildFrameIndex(AddrReg, FI);
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StackUsed = std::max(StackUsed, Size + Offset);
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return AddrReg;
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}
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void assignValueToReg(unsigned ValVReg, unsigned PhysReg,
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CCValAssign &VA) override {
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markPhysRegUsed(PhysReg);
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switch (VA.getLocInfo()) {
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default:
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MIRBuilder.buildCopy(ValVReg, PhysReg);
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break;
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case CCValAssign::LocInfo::SExt:
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case CCValAssign::LocInfo::ZExt:
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case CCValAssign::LocInfo::AExt: {
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auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg);
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MIRBuilder.buildTrunc(ValVReg, Copy);
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break;
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}
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}
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}
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void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size,
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MachinePointerInfo &MPO, CCValAssign &VA) override {
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auto MMO = MIRBuilder.getMF().getMachineMemOperand(
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MPO, MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant, Size,
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0);
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MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
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}
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/// How the physical register gets marked varies between formal
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/// parameters (it's a basic-block live-in), and a call instruction
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/// (it's an implicit-def of the BL).
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virtual void markPhysRegUsed(unsigned PhysReg) = 0;
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uint64_t StackUsed;
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};
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struct FormalArgHandler : public IncomingArgHandler {
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FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
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CCAssignFn *AssignFn)
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: IncomingArgHandler(MIRBuilder, MRI, AssignFn) {}
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void markPhysRegUsed(unsigned PhysReg) override {
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MIRBuilder.getMBB().addLiveIn(PhysReg);
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}
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};
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struct CallReturnHandler : public IncomingArgHandler {
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CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
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MachineInstrBuilder MIB, CCAssignFn *AssignFn)
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: IncomingArgHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
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void markPhysRegUsed(unsigned PhysReg) override {
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MIB.addDef(PhysReg, RegState::Implicit);
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}
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MachineInstrBuilder MIB;
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};
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struct OutgoingArgHandler : public CallLowering::ValueHandler {
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OutgoingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
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MachineInstrBuilder MIB, CCAssignFn *AssignFn,
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CCAssignFn *AssignFnVarArg)
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: ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB),
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AssignFnVarArg(AssignFnVarArg), StackSize(0) {}
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unsigned getStackAddress(uint64_t Size, int64_t Offset,
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MachinePointerInfo &MPO) override {
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LLT p0 = LLT::pointer(0, 64);
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LLT s64 = LLT::scalar(64);
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unsigned SPReg = MRI.createGenericVirtualRegister(p0);
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MIRBuilder.buildCopy(SPReg, AArch64::SP);
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unsigned OffsetReg = MRI.createGenericVirtualRegister(s64);
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MIRBuilder.buildConstant(OffsetReg, Offset);
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unsigned AddrReg = MRI.createGenericVirtualRegister(p0);
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MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg);
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MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
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return AddrReg;
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}
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void assignValueToReg(unsigned ValVReg, unsigned PhysReg,
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CCValAssign &VA) override {
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MIB.addUse(PhysReg, RegState::Implicit);
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unsigned ExtReg = extendRegister(ValVReg, VA);
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MIRBuilder.buildCopy(PhysReg, ExtReg);
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}
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void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size,
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MachinePointerInfo &MPO, CCValAssign &VA) override {
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auto MMO = MIRBuilder.getMF().getMachineMemOperand(
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MPO, MachineMemOperand::MOStore, Size, 0);
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MIRBuilder.buildStore(ValVReg, Addr, *MMO);
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}
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bool assignArg(unsigned ValNo, MVT ValVT, MVT LocVT,
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CCValAssign::LocInfo LocInfo,
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const CallLowering::ArgInfo &Info,
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CCState &State) override {
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bool Res;
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if (Info.IsFixed)
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Res = AssignFn(ValNo, ValVT, LocVT, LocInfo, Info.Flags, State);
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else
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Res = AssignFnVarArg(ValNo, ValVT, LocVT, LocInfo, Info.Flags, State);
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StackSize = State.getNextStackOffset();
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return Res;
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}
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MachineInstrBuilder MIB;
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CCAssignFn *AssignFnVarArg;
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uint64_t StackSize;
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};
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} // namespace
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void AArch64CallLowering::splitToValueTypes(
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const ArgInfo &OrigArg, SmallVectorImpl<ArgInfo> &SplitArgs,
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const DataLayout &DL, MachineRegisterInfo &MRI, CallingConv::ID CallConv,
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const SplitArgTy &PerformArgSplit) const {
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const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
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LLVMContext &Ctx = OrigArg.Ty->getContext();
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SmallVector<EVT, 4> SplitVTs;
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SmallVector<uint64_t, 4> Offsets;
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ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitVTs, &Offsets, 0);
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if (SplitVTs.size() == 1) {
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// No splitting to do, but we want to replace the original type (e.g. [1 x
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// double] -> double).
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SplitArgs.emplace_back(OrigArg.Reg, SplitVTs[0].getTypeForEVT(Ctx),
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OrigArg.Flags, OrigArg.IsFixed);
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return;
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}
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unsigned FirstRegIdx = SplitArgs.size();
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bool NeedsRegBlock = TLI.functionArgumentNeedsConsecutiveRegisters(
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OrigArg.Ty, CallConv, false);
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for (auto SplitVT : SplitVTs) {
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Type *SplitTy = SplitVT.getTypeForEVT(Ctx);
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SplitArgs.push_back(
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ArgInfo{MRI.createGenericVirtualRegister(getLLTForType(*SplitTy, DL)),
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SplitTy, OrigArg.Flags, OrigArg.IsFixed});
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if (NeedsRegBlock)
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SplitArgs.back().Flags.setInConsecutiveRegs();
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}
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SplitArgs.back().Flags.setInConsecutiveRegsLast();
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for (unsigned i = 0; i < Offsets.size(); ++i)
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PerformArgSplit(SplitArgs[FirstRegIdx + i].Reg, Offsets[i] * 8);
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}
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bool AArch64CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
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const Value *Val, unsigned VReg) const {
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MachineFunction &MF = MIRBuilder.getMF();
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const Function &F = MF.getFunction();
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auto MIB = MIRBuilder.buildInstrNoInsert(AArch64::RET_ReallyLR);
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assert(((Val && VReg) || (!Val && !VReg)) && "Return value without a vreg");
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bool Success = true;
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if (VReg) {
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const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
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CCAssignFn *AssignFn = TLI.CCAssignFnForReturn(F.getCallingConv());
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MachineRegisterInfo &MRI = MF.getRegInfo();
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auto &DL = F.getParent()->getDataLayout();
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ArgInfo OrigArg{VReg, Val->getType()};
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setArgFlags(OrigArg, AttributeList::ReturnIndex, DL, F);
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SmallVector<ArgInfo, 8> SplitArgs;
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splitToValueTypes(OrigArg, SplitArgs, DL, MRI, F.getCallingConv(),
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[&](unsigned Reg, uint64_t Offset) {
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MIRBuilder.buildExtract(Reg, VReg, Offset);
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});
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OutgoingArgHandler Handler(MIRBuilder, MRI, MIB, AssignFn, AssignFn);
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Success = handleAssignments(MIRBuilder, SplitArgs, Handler);
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}
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MIRBuilder.insertInstr(MIB);
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return Success;
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}
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bool AArch64CallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
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const Function &F,
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ArrayRef<unsigned> VRegs) const {
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MachineFunction &MF = MIRBuilder.getMF();
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MachineBasicBlock &MBB = MIRBuilder.getMBB();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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auto &DL = F.getParent()->getDataLayout();
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SmallVector<ArgInfo, 8> SplitArgs;
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unsigned i = 0;
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for (auto &Arg : F.args()) {
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if (DL.getTypeStoreSize(Arg.getType()) == 0)
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continue;
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ArgInfo OrigArg{VRegs[i], Arg.getType()};
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setArgFlags(OrigArg, i + AttributeList::FirstArgIndex, DL, F);
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bool Split = false;
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LLT Ty = MRI.getType(VRegs[i]);
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unsigned Dst = VRegs[i];
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splitToValueTypes(OrigArg, SplitArgs, DL, MRI, F.getCallingConv(),
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[&](unsigned Reg, uint64_t Offset) {
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if (!Split) {
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Split = true;
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Dst = MRI.createGenericVirtualRegister(Ty);
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MIRBuilder.buildUndef(Dst);
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}
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unsigned Tmp = MRI.createGenericVirtualRegister(Ty);
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MIRBuilder.buildInsert(Tmp, Dst, Reg, Offset);
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Dst = Tmp;
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});
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if (Dst != VRegs[i])
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MIRBuilder.buildCopy(VRegs[i], Dst);
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++i;
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}
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if (!MBB.empty())
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MIRBuilder.setInstr(*MBB.begin());
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const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
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CCAssignFn *AssignFn =
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TLI.CCAssignFnForCall(F.getCallingConv(), /*IsVarArg=*/false);
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FormalArgHandler Handler(MIRBuilder, MRI, AssignFn);
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if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
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return false;
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if (F.isVarArg()) {
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if (!MF.getSubtarget<AArch64Subtarget>().isTargetDarwin()) {
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// FIXME: we need to reimplement saveVarArgsRegisters from
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// AArch64ISelLowering.
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return false;
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}
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// We currently pass all varargs at 8-byte alignment.
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uint64_t StackOffset = alignTo(Handler.StackUsed, 8);
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auto &MFI = MIRBuilder.getMF().getFrameInfo();
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AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
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FuncInfo->setVarArgsStackIndex(MFI.CreateFixedObject(4, StackOffset, true));
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}
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// Move back to the end of the basic block.
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MIRBuilder.setMBB(MBB);
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return true;
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}
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bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
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CallingConv::ID CallConv,
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const MachineOperand &Callee,
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const ArgInfo &OrigRet,
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ArrayRef<ArgInfo> OrigArgs) const {
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MachineFunction &MF = MIRBuilder.getMF();
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const Function &F = MF.getFunction();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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auto &DL = F.getParent()->getDataLayout();
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SmallVector<ArgInfo, 8> SplitArgs;
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for (auto &OrigArg : OrigArgs) {
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splitToValueTypes(OrigArg, SplitArgs, DL, MRI, CallConv,
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[&](unsigned Reg, uint64_t Offset) {
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MIRBuilder.buildExtract(Reg, OrigArg.Reg, Offset);
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});
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}
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// Find out which ABI gets to decide where things go.
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const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
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CCAssignFn *AssignFnFixed =
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TLI.CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
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CCAssignFn *AssignFnVarArg =
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TLI.CCAssignFnForCall(CallConv, /*IsVarArg=*/true);
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auto CallSeqStart = MIRBuilder.buildInstr(AArch64::ADJCALLSTACKDOWN);
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// Create a temporarily-floating call instruction so we can add the implicit
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// uses of arg registers.
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auto MIB = MIRBuilder.buildInstrNoInsert(Callee.isReg() ? AArch64::BLR
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: AArch64::BL);
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MIB.add(Callee);
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// Tell the call which registers are clobbered.
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auto TRI = MF.getSubtarget().getRegisterInfo();
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MIB.addRegMask(TRI->getCallPreservedMask(MF, F.getCallingConv()));
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// Do the actual argument marshalling.
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SmallVector<unsigned, 8> PhysRegs;
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OutgoingArgHandler Handler(MIRBuilder, MRI, MIB, AssignFnFixed,
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AssignFnVarArg);
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if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
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return false;
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// Now we can add the actual call instruction to the correct basic block.
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MIRBuilder.insertInstr(MIB);
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// If Callee is a reg, since it is used by a target specific
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// instruction, it must have a register class matching the
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// constraint of that instruction.
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if (Callee.isReg())
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MIB->getOperand(0).setReg(constrainOperandRegClass(
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MF, *TRI, MRI, *MF.getSubtarget().getInstrInfo(),
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*MF.getSubtarget().getRegBankInfo(), *MIB, MIB->getDesc(),
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Callee.getReg(), 0));
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// Finally we can copy the returned value back into its virtual-register. In
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// symmetry with the arugments, the physical register must be an
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// implicit-define of the call instruction.
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CCAssignFn *RetAssignFn = TLI.CCAssignFnForReturn(F.getCallingConv());
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if (OrigRet.Reg) {
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SplitArgs.clear();
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SmallVector<uint64_t, 8> RegOffsets;
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SmallVector<unsigned, 8> SplitRegs;
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splitToValueTypes(OrigRet, SplitArgs, DL, MRI, F.getCallingConv(),
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[&](unsigned Reg, uint64_t Offset) {
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RegOffsets.push_back(Offset);
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SplitRegs.push_back(Reg);
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});
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CallReturnHandler Handler(MIRBuilder, MRI, MIB, RetAssignFn);
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if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
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return false;
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if (!RegOffsets.empty())
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MIRBuilder.buildSequence(OrigRet.Reg, SplitRegs, RegOffsets);
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}
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CallSeqStart.addImm(Handler.StackSize).addImm(0);
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MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP)
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.addImm(Handler.StackSize)
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.addImm(0);
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return true;
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}
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