Imported Upstream version 5.18.0.167

Former-commit-id: 289509151e0fee68a1b591a20c9f109c3c789d3a

external/llvm/lib/CodeGen/GlobalISel/CMakeLists.txt

@@ -1,19 +0,0 @@
-add_llvm_library(LLVMGlobalISel
-        CallLowering.cpp
-        GlobalISel.cpp
-        IRTranslator.cpp
-        InstructionSelect.cpp
-        InstructionSelector.cpp
-        LegalizerHelper.cpp
-        Legalizer.cpp
-        LegalizerInfo.cpp
-        Localizer.cpp
-        MachineIRBuilder.cpp
-        RegBankSelect.cpp
-        RegisterBank.cpp
-        RegisterBankInfo.cpp
-        Utils.cpp
-
-        DEPENDS
-        intrinsics_gen
-  )

external/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp

@@ -1,180 +0,0 @@
-//===-- lib/CodeGen/GlobalISel/CallLowering.cpp - Call lowering -----------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-///
-/// \file
-/// This file implements some simple delegations needed for call lowering.
-///
-//===----------------------------------------------------------------------===//
-
-#include "llvm/CodeGen/GlobalISel/CallLowering.h"
-#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
-#include "llvm/CodeGen/MachineOperand.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/TargetLowering.h"
-#include "llvm/IR/DataLayout.h"
-#include "llvm/IR/Instructions.h"
-#include "llvm/IR/Module.h"
-
-using namespace llvm;
-
-bool CallLowering::lowerCall(
-    MachineIRBuilder &MIRBuilder, ImmutableCallSite CS, unsigned ResReg,
-    ArrayRef<unsigned> ArgRegs, std::function<unsigned()> GetCalleeReg) const {
-  auto &DL = CS.getParent()->getParent()->getParent()->getDataLayout();
-
-  // First step is to marshall all the function's parameters into the correct
-  // physregs and memory locations. Gather the sequence of argument types that
-  // we'll pass to the assigner function.
-  SmallVector<ArgInfo, 8> OrigArgs;
-  unsigned i = 0;
-  unsigned NumFixedArgs = CS.getFunctionType()->getNumParams();
-  for (auto &Arg : CS.args()) {
-    ArgInfo OrigArg{ArgRegs[i], Arg->getType(), ISD::ArgFlagsTy{},
-                    i < NumFixedArgs};
-    setArgFlags(OrigArg, i + AttributeList::FirstArgIndex, DL, CS);
-    OrigArgs.push_back(OrigArg);
-    ++i;
-  }
-
-  MachineOperand Callee = MachineOperand::CreateImm(0);
-  if (const Function *F = CS.getCalledFunction())
-    Callee = MachineOperand::CreateGA(F, 0);
-  else
-    Callee = MachineOperand::CreateReg(GetCalleeReg(), false);
-
-  ArgInfo OrigRet{ResReg, CS.getType(), ISD::ArgFlagsTy{}};
-  if (!OrigRet.Ty->isVoidTy())
-    setArgFlags(OrigRet, AttributeList::ReturnIndex, DL, CS);
-
-  return lowerCall(MIRBuilder, CS.getCallingConv(), Callee, OrigRet, OrigArgs);
-}
-
-template <typename FuncInfoTy>
-void CallLowering::setArgFlags(CallLowering::ArgInfo &Arg, unsigned OpIdx,
-                               const DataLayout &DL,
-                               const FuncInfoTy &FuncInfo) const {
-  const AttributeList &Attrs = FuncInfo.getAttributes();
-  if (Attrs.hasAttribute(OpIdx, Attribute::ZExt))
-    Arg.Flags.setZExt();
-  if (Attrs.hasAttribute(OpIdx, Attribute::SExt))
-    Arg.Flags.setSExt();
-  if (Attrs.hasAttribute(OpIdx, Attribute::InReg))
-    Arg.Flags.setInReg();
-  if (Attrs.hasAttribute(OpIdx, Attribute::StructRet))
-    Arg.Flags.setSRet();
-  if (Attrs.hasAttribute(OpIdx, Attribute::SwiftSelf))
-    Arg.Flags.setSwiftSelf();
-  if (Attrs.hasAttribute(OpIdx, Attribute::SwiftError))
-    Arg.Flags.setSwiftError();
-  if (Attrs.hasAttribute(OpIdx, Attribute::ByVal))
-    Arg.Flags.setByVal();
-  if (Attrs.hasAttribute(OpIdx, Attribute::InAlloca))
-    Arg.Flags.setInAlloca();
-
-  if (Arg.Flags.isByVal() || Arg.Flags.isInAlloca()) {
-    Type *ElementTy = cast<PointerType>(Arg.Ty)->getElementType();
-    Arg.Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
-    // For ByVal, alignment should be passed from FE.  BE will guess if
-    // this info is not there but there are cases it cannot get right.
-    unsigned FrameAlign;
-    if (FuncInfo.getParamAlignment(OpIdx - 2))
-      FrameAlign = FuncInfo.getParamAlignment(OpIdx - 2);
-    else
-      FrameAlign = getTLI()->getByValTypeAlignment(ElementTy, DL);
-    Arg.Flags.setByValAlign(FrameAlign);
-  }
-  if (Attrs.hasAttribute(OpIdx, Attribute::Nest))
-    Arg.Flags.setNest();
-  Arg.Flags.setOrigAlign(DL.getABITypeAlignment(Arg.Ty));
-}
-
-template void
-CallLowering::setArgFlags<Function>(CallLowering::ArgInfo &Arg, unsigned OpIdx,
-                                    const DataLayout &DL,
-                                    const Function &FuncInfo) const;
-
-template void
-CallLowering::setArgFlags<CallInst>(CallLowering::ArgInfo &Arg, unsigned OpIdx,
-                                    const DataLayout &DL,
-                                    const CallInst &FuncInfo) const;
-
-bool CallLowering::handleAssignments(MachineIRBuilder &MIRBuilder,
-                                     ArrayRef<ArgInfo> Args,
-                                     ValueHandler &Handler) const {
-  MachineFunction &MF = MIRBuilder.getMF();
-  const Function &F = MF.getFunction();
-  const DataLayout &DL = F.getParent()->getDataLayout();
-
-  SmallVector<CCValAssign, 16> ArgLocs;
-  CCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs, F.getContext());
-
-  unsigned NumArgs = Args.size();
-  for (unsigned i = 0; i != NumArgs; ++i) {
-    MVT CurVT = MVT::getVT(Args[i].Ty);
-    if (Handler.assignArg(i, CurVT, CurVT, CCValAssign::Full, Args[i], CCInfo))
-      return false;
-  }
-
-  for (unsigned i = 0, e = Args.size(), j = 0; i != e; ++i, ++j) {
-    assert(j < ArgLocs.size() && "Skipped too many arg locs");
-
-    CCValAssign &VA = ArgLocs[j];
-    assert(VA.getValNo() == i && "Location doesn't correspond to current arg");
-
-    if (VA.needsCustom()) {
-      j += Handler.assignCustomValue(Args[i], makeArrayRef(ArgLocs).slice(j));
-      continue;
-    }
-
-    if (VA.isRegLoc())
-      Handler.assignValueToReg(Args[i].Reg, VA.getLocReg(), VA);
-    else if (VA.isMemLoc()) {
-      unsigned Size = VA.getValVT() == MVT::iPTR
-                          ? DL.getPointerSize()
-                          : alignTo(VA.getValVT().getSizeInBits(), 8) / 8;
-      unsigned Offset = VA.getLocMemOffset();
-      MachinePointerInfo MPO;
-      unsigned StackAddr = Handler.getStackAddress(Size, Offset, MPO);
-      Handler.assignValueToAddress(Args[i].Reg, StackAddr, Size, MPO, VA);
-    } else {
-      // FIXME: Support byvals and other weirdness
-      return false;
-    }
-  }
-  return true;
-}
-
-unsigned CallLowering::ValueHandler::extendRegister(unsigned ValReg,
-                                                    CCValAssign &VA) {
-  LLT LocTy{VA.getLocVT()};
-  switch (VA.getLocInfo()) {
-  default: break;
-  case CCValAssign::Full:
-  case CCValAssign::BCvt:
-    // FIXME: bitconverting between vector types may or may not be a
-    // nop in big-endian situations.
-    return ValReg;
-  case CCValAssign::AExt: {
-    assert(!VA.getLocVT().isVector() && "unexpected vector extend");
-    auto MIB = MIRBuilder.buildAnyExt(LocTy, ValReg);
-    return MIB->getOperand(0).getReg();
-  }
-  case CCValAssign::SExt: {
-    unsigned NewReg = MRI.createGenericVirtualRegister(LocTy);
-    MIRBuilder.buildSExt(NewReg, ValReg);
-    return NewReg;
-  }
-  case CCValAssign::ZExt: {
-    unsigned NewReg = MRI.createGenericVirtualRegister(LocTy);
-    MIRBuilder.buildZExt(NewReg, ValReg);
-    return NewReg;
-  }
-  }
-  llvm_unreachable("unable to extend register");
-}

external/llvm/lib/CodeGen/GlobalISel/GlobalISel.cpp

@@ -1,25 +0,0 @@
-//===-- llvm/CodeGen/GlobalISel/GlobalIsel.cpp --- GlobalISel ----*- C++ -*-==//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-/// \file
-// This file implements the common initialization routines for the
-// GlobalISel library.
-//===----------------------------------------------------------------------===//
-
-#include "llvm/InitializePasses.h"
-#include "llvm/PassRegistry.h"
-
-using namespace llvm;
-
-void llvm::initializeGlobalISel(PassRegistry &Registry) {
-  initializeIRTranslatorPass(Registry);
-  initializeLegalizerPass(Registry);
-  initializeLocalizerPass(Registry);
-  initializeRegBankSelectPass(Registry);
-  initializeInstructionSelectPass(Registry);
-}

external/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp

@@ -1,211 +0,0 @@
-//===- llvm/CodeGen/GlobalISel/InstructionSelect.cpp - InstructionSelect ---==//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-/// \file
-/// This file implements the InstructionSelect class.
-//===----------------------------------------------------------------------===//
-
-#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
-#include "llvm/ADT/PostOrderIterator.h"
-#include "llvm/ADT/ScopeExit.h"
-#include "llvm/ADT/Twine.h"
-#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
-#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
-#include "llvm/CodeGen/GlobalISel/Utils.h"
-#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/TargetLowering.h"
-#include "llvm/CodeGen/TargetPassConfig.h"
-#include "llvm/CodeGen/TargetSubtargetInfo.h"
-#include "llvm/Config/config.h"
-#include "llvm/IR/Constants.h"
-#include "llvm/IR/Function.h"
-#include "llvm/Support/CommandLine.h"
-#include "llvm/Support/Debug.h"
-#include "llvm/Support/TargetRegistry.h"
-
-#define DEBUG_TYPE "instruction-select"
-
-using namespace llvm;
-
-#ifdef LLVM_GISEL_COV_PREFIX
-static cl::opt<std::string>
-    CoveragePrefix("gisel-coverage-prefix", cl::init(LLVM_GISEL_COV_PREFIX),
-                   cl::desc("Record GlobalISel rule coverage files of this "
-                            "prefix if instrumentation was generated"));
-#else
-static const std::string CoveragePrefix = "";
-#endif
-
-char InstructionSelect::ID = 0;
-INITIALIZE_PASS_BEGIN(InstructionSelect, DEBUG_TYPE,
-                      "Select target instructions out of generic instructions",
-                      false, false)
-INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
-INITIALIZE_PASS_END(InstructionSelect, DEBUG_TYPE,
-                    "Select target instructions out of generic instructions",
-                    false, false)
-
-InstructionSelect::InstructionSelect() : MachineFunctionPass(ID) {
-  initializeInstructionSelectPass(*PassRegistry::getPassRegistry());
-}
-
-void InstructionSelect::getAnalysisUsage(AnalysisUsage &AU) const {
-  AU.addRequired<TargetPassConfig>();
-  MachineFunctionPass::getAnalysisUsage(AU);
-}
-
-bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) {
-  const MachineRegisterInfo &MRI = MF.getRegInfo();
-
-  // No matter what happens, whether we successfully select the function or not,
-  // nothing is going to use the vreg types after us.  Make sure they disappear.
-  auto ClearVRegTypesOnReturn =
-      make_scope_exit([&]() { MRI.getVRegToType().clear(); });
-
-  // If the ISel pipeline failed, do not bother running that pass.
-  if (MF.getProperties().hasProperty(
-          MachineFunctionProperties::Property::FailedISel))
-    return false;
-
-  DEBUG(dbgs() << "Selecting function: " << MF.getName() << '\n');
-
-  const TargetPassConfig &TPC = getAnalysis<TargetPassConfig>();
-  const InstructionSelector *ISel = MF.getSubtarget().getInstructionSelector();
-  CodeGenCoverage CoverageInfo;
-  assert(ISel && "Cannot work without InstructionSelector");
-
-  // An optimization remark emitter. Used to report failures.
-  MachineOptimizationRemarkEmitter MORE(MF, /*MBFI=*/nullptr);
-
-  // FIXME: There are many other MF/MFI fields we need to initialize.
-
-#ifndef NDEBUG
-  // Check that our input is fully legal: we require the function to have the
-  // Legalized property, so it should be.
-  // FIXME: This should be in the MachineVerifier, but it can't use the
-  // LegalizerInfo as it's currently in the separate GlobalISel library.
-  // The RegBankSelected property is already checked in the verifier. Note
-  // that it has the same layering problem, but we only use inline methods so
-  // end up not needing to link against the GlobalISel library.
-  if (const LegalizerInfo *MLI = MF.getSubtarget().getLegalizerInfo())
-    for (MachineBasicBlock &MBB : MF)
-      for (MachineInstr &MI : MBB)
-        if (isPreISelGenericOpcode(MI.getOpcode()) && !MLI->isLegal(MI, MRI)) {
-          reportGISelFailure(MF, TPC, MORE, "gisel-select",
-                             "instruction is not legal", MI);
-          return false;
-        }
-
-#endif
-  // FIXME: We could introduce new blocks and will need to fix the outer loop.
-  // Until then, keep track of the number of blocks to assert that we don't.
-  const size_t NumBlocks = MF.size();
-
-  for (MachineBasicBlock *MBB : post_order(&MF)) {
-    if (MBB->empty())
-      continue;
-
-    // Select instructions in reverse block order. We permit erasing so have
-    // to resort to manually iterating and recognizing the begin (rend) case.
-    bool ReachedBegin = false;
-    for (auto MII = std::prev(MBB->end()), Begin = MBB->begin();
-         !ReachedBegin;) {
-#ifndef NDEBUG
-      // Keep track of the insertion range for debug printing.
-      const auto AfterIt = std::next(MII);
-#endif
-      // Select this instruction.
-      MachineInstr &MI = *MII;
-
-      // And have our iterator point to the next instruction, if there is one.
-      if (MII == Begin)
-        ReachedBegin = true;
-      else
-        --MII;
-
-      DEBUG(dbgs() << "Selecting: \n  " << MI);
-
-      // We could have folded this instruction away already, making it dead.
-      // If so, erase it.
-      if (isTriviallyDead(MI, MRI)) {
-        DEBUG(dbgs() << "Is dead; erasing.\n");
-        MI.eraseFromParentAndMarkDBGValuesForRemoval();
-        continue;
-      }
-
-      if (!ISel->select(MI, CoverageInfo)) {
-        // FIXME: It would be nice to dump all inserted instructions.  It's
-        // not obvious how, esp. considering select() can insert after MI.
-        reportGISelFailure(MF, TPC, MORE, "gisel-select", "cannot select", MI);
-        return false;
-      }
-
-      // Dump the range of instructions that MI expanded into.
-      DEBUG({
-        auto InsertedBegin = ReachedBegin ? MBB->begin() : std::next(MII);
-        dbgs() << "Into:\n";
-        for (auto &InsertedMI : make_range(InsertedBegin, AfterIt))
-          dbgs() << "  " << InsertedMI;
-        dbgs() << '\n';
-      });
-    }
-  }
-
-  const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
-
-  // Now that selection is complete, there are no more generic vregs.  Verify
-  // that the size of the now-constrained vreg is unchanged and that it has a
-  // register class.
-  for (auto &VRegToType : MRI.getVRegToType()) {
-    unsigned VReg = VRegToType.first;
-    auto *RC = MRI.getRegClassOrNull(VReg);
-    MachineInstr *MI = nullptr;
-    if (!MRI.def_empty(VReg))
-      MI = &*MRI.def_instr_begin(VReg);
-    else if (!MRI.use_empty(VReg))
-      MI = &*MRI.use_instr_begin(VReg);
-
-    if (MI && !RC) {
-      reportGISelFailure(MF, TPC, MORE, "gisel-select",
-                         "VReg has no regclass after selection", *MI);
-      return false;
-    } else if (!RC)
-      continue;
-
-    if (VRegToType.second.isValid() &&
-        VRegToType.second.getSizeInBits() > TRI.getRegSizeInBits(*RC)) {
-      reportGISelFailure(MF, TPC, MORE, "gisel-select",
-                         "VReg has explicit size different from class size",
-                         *MI);
-      return false;
-    }
-  }
-
-  if (MF.size() != NumBlocks) {
-    MachineOptimizationRemarkMissed R("gisel-select", "GISelFailure",
-                                      MF.getFunction().getSubprogram(),
-                                      /*MBB=*/nullptr);
-    R << "inserting blocks is not supported yet";
-    reportGISelFailure(MF, TPC, MORE, R);
-    return false;
-  }
-
-  auto &TLI = *MF.getSubtarget().getTargetLowering();
-  TLI.finalizeLowering(MF);
-
-  CoverageInfo.emit(CoveragePrefix,
-                    MF.getSubtarget()
-                        .getTargetLowering()
-                        ->getTargetMachine()
-                        .getTarget()
-                        .getBackendName());
-
-  // FIXME: Should we accurately track changes?
-  return true;
-}

external/llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp

@@ -1,128 +0,0 @@
-//===- llvm/CodeGen/GlobalISel/InstructionSelector.cpp --------------------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-/// \file
-/// This file implements the InstructionSelector class.
-//
-//===----------------------------------------------------------------------===//
-
-#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
-#include "llvm/CodeGen/GlobalISel/Utils.h"
-#include "llvm/CodeGen/MachineBasicBlock.h"
-#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/CodeGen/MachineOperand.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/TargetRegisterInfo.h"
-#include "llvm/MC/MCInstrDesc.h"
-#include "llvm/Support/Debug.h"
-#include "llvm/Support/raw_ostream.h"
-#include <cassert>
-
-#define DEBUG_TYPE "instructionselector"
-
-using namespace llvm;
-
-InstructionSelector::MatcherState::MatcherState(unsigned MaxRenderers)
-    : Renderers(MaxRenderers), MIs() {}
-
-InstructionSelector::InstructionSelector() = default;
-
-bool InstructionSelector::constrainOperandRegToRegClass(
-    MachineInstr &I, unsigned OpIdx, const TargetRegisterClass &RC,
-    const TargetInstrInfo &TII, const TargetRegisterInfo &TRI,
-    const RegisterBankInfo &RBI) const {
-  MachineBasicBlock &MBB = *I.getParent();
-  MachineFunction &MF = *MBB.getParent();
-  MachineRegisterInfo &MRI = MF.getRegInfo();
-
-  return
-      constrainRegToClass(MRI, TII, RBI, I, I.getOperand(OpIdx).getReg(), RC);
-}
-
-bool InstructionSelector::constrainSelectedInstRegOperands(
-    MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI,
-    const RegisterBankInfo &RBI) const {
-  MachineBasicBlock &MBB = *I.getParent();
-  MachineFunction &MF = *MBB.getParent();
-  MachineRegisterInfo &MRI = MF.getRegInfo();
-
-  for (unsigned OpI = 0, OpE = I.getNumExplicitOperands(); OpI != OpE; ++OpI) {
-    MachineOperand &MO = I.getOperand(OpI);
-
-    // There's nothing to be done on non-register operands.
-    if (!MO.isReg())
-      continue;
-
-    DEBUG(dbgs() << "Converting operand: " << MO << '\n');
-    assert(MO.isReg() && "Unsupported non-reg operand");
-
-    unsigned Reg = MO.getReg();
-    // Physical registers don't need to be constrained.
-    if (TRI.isPhysicalRegister(Reg))
-      continue;
-
-    // Register operands with a value of 0 (e.g. predicate operands) don't need
-    // to be constrained.
-    if (Reg == 0)
-      continue;
-
-    // If the operand is a vreg, we should constrain its regclass, and only
-    // insert COPYs if that's impossible.
-    // constrainOperandRegClass does that for us.
-    MO.setReg(constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(),
-                                       Reg, OpI));
-
-    // Tie uses to defs as indicated in MCInstrDesc if this hasn't already been
-    // done.
-    if (MO.isUse()) {
-      int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO);
-      if (DefIdx != -1 && !I.isRegTiedToUseOperand(DefIdx))
-        I.tieOperands(DefIdx, OpI);
-    }
-  }
-  return true;
-}
-
-bool InstructionSelector::isOperandImmEqual(
-    const MachineOperand &MO, int64_t Value,
-    const MachineRegisterInfo &MRI) const {
-  if (MO.isReg() && MO.getReg())
-    if (auto VRegVal = getConstantVRegVal(MO.getReg(), MRI))
-      return *VRegVal == Value;
-  return false;
-}
-
-bool InstructionSelector::isBaseWithConstantOffset(
-    const MachineOperand &Root, const MachineRegisterInfo &MRI) const {
-  if (!Root.isReg())
-    return false;
-
-  MachineInstr *RootI = MRI.getVRegDef(Root.getReg());
-  if (RootI->getOpcode() != TargetOpcode::G_GEP)
-    return false;
-
-  MachineOperand &RHS = RootI->getOperand(2);
-  MachineInstr *RHSI = MRI.getVRegDef(RHS.getReg());
-  if (RHSI->getOpcode() != TargetOpcode::G_CONSTANT)
-    return false;
-
-  return true;
-}
-
-bool InstructionSelector::isObviouslySafeToFold(MachineInstr &MI,
-                                                MachineInstr &IntoMI) const {
-  // Immediate neighbours are already folded.
-  if (MI.getParent() == IntoMI.getParent() &&
-      std::next(MI.getIterator()) == IntoMI.getIterator())
-    return true;
-
-  return !MI.mayLoadOrStore() && !MI.hasUnmodeledSideEffects() &&
-         MI.implicit_operands().begin() == MI.implicit_operands().end();
-}

external/llvm/lib/CodeGen/GlobalISel/LLVMBuild.txt

@@ -1,22 +0,0 @@
-;===- ./lib/CodeGen/GlobalISel/LLVMBuild.txt -----------------*- Conf -*--===;
-;
-;                     The LLVM Compiler Infrastructure
-;
-; This file is distributed under the University of Illinois Open Source
-; License. See LICENSE.TXT for details.
-;
-;===------------------------------------------------------------------------===;
-;
-; This is an LLVMBuild description file for the components in this subdirectory.
-;
-; For more information on the LLVMBuild system, please see:
-;
-;   http://llvm.org/docs/LLVMBuild.html
-;
-;===------------------------------------------------------------------------===;
-
-[component_0]
-type = Library
-name = GlobalISel
-parent = CodeGen
-required_libraries = Analysis CodeGen Core MC Support Target TransformUtils

external/llvm/lib/CodeGen/GlobalISel/Legalizer.cpp

@@ -1,186 +0,0 @@
-//===-- llvm/CodeGen/GlobalISel/Legalizer.cpp -----------------------------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-/// \file This file implements the LegalizerHelper class to legalize individual
-/// instructions and the LegalizePass wrapper pass for the primary
-/// legalization.
-//
-//===----------------------------------------------------------------------===//
-
-#include "llvm/CodeGen/GlobalISel/Legalizer.h"
-#include "llvm/ADT/PostOrderIterator.h"
-#include "llvm/ADT/SetVector.h"
-#include "llvm/CodeGen/GlobalISel/GISelWorkList.h"
-#include "llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h"
-#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
-#include "llvm/CodeGen/GlobalISel/Utils.h"
-#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/TargetPassConfig.h"
-#include "llvm/CodeGen/TargetSubtargetInfo.h"
-#include "llvm/Support/Debug.h"
-
-#include <iterator>
-
-#define DEBUG_TYPE "legalizer"
-
-using namespace llvm;
-
-char Legalizer::ID = 0;
-INITIALIZE_PASS_BEGIN(Legalizer, DEBUG_TYPE,
-                      "Legalize the Machine IR a function's Machine IR", false,
-                      false)
-INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
-INITIALIZE_PASS_END(Legalizer, DEBUG_TYPE,
-                    "Legalize the Machine IR a function's Machine IR", false,
-                    false)
-
-Legalizer::Legalizer() : MachineFunctionPass(ID) {
-  initializeLegalizerPass(*PassRegistry::getPassRegistry());
-}
-
-void Legalizer::getAnalysisUsage(AnalysisUsage &AU) const {
-  AU.addRequired<TargetPassConfig>();
-  MachineFunctionPass::getAnalysisUsage(AU);
-}
-
-void Legalizer::init(MachineFunction &MF) {
-}
-
-static bool isArtifact(const MachineInstr &MI) {
-  switch (MI.getOpcode()) {
-  default:
-    return false;
-  case TargetOpcode::G_TRUNC:
-  case TargetOpcode::G_ZEXT:
-  case TargetOpcode::G_ANYEXT:
-  case TargetOpcode::G_SEXT:
-  case TargetOpcode::G_MERGE_VALUES:
-  case TargetOpcode::G_UNMERGE_VALUES:
-    return true;
-  }
-}
-
-bool Legalizer::runOnMachineFunction(MachineFunction &MF) {
-  // If the ISel pipeline failed, do not bother running that pass.
-  if (MF.getProperties().hasProperty(
-          MachineFunctionProperties::Property::FailedISel))
-    return false;
-  DEBUG(dbgs() << "Legalize Machine IR for: " << MF.getName() << '\n');
-  init(MF);
-  const TargetPassConfig &TPC = getAnalysis<TargetPassConfig>();
-  MachineOptimizationRemarkEmitter MORE(MF, /*MBFI=*/nullptr);
-  LegalizerHelper Helper(MF);
-
-  const size_t NumBlocks = MF.size();
-  MachineRegisterInfo &MRI = MF.getRegInfo();
-
-  // Populate Insts
-  GISelWorkList<256> InstList;
-  GISelWorkList<128> ArtifactList;
-  ReversePostOrderTraversal<MachineFunction *> RPOT(&MF);
-  // Perform legalization bottom up so we can DCE as we legalize.
-  // Traverse BB in RPOT and within each basic block, add insts top down,
-  // so when we pop_back_val in the legalization process, we traverse bottom-up.
-  for (auto *MBB : RPOT) {
-    if (MBB->empty())
-      continue;
-    for (MachineInstr &MI : *MBB) {
-      // Only legalize pre-isel generic instructions: others don't have types
-      // and are assumed to be legal.
-      if (!isPreISelGenericOpcode(MI.getOpcode()))
-        continue;
-      if (isArtifact(MI))
-        ArtifactList.insert(&MI);
-      else
-        InstList.insert(&MI);
-    }
-  }
-  Helper.MIRBuilder.recordInsertions([&](MachineInstr *MI) {
-    // Only legalize pre-isel generic instructions.
-    // Legalization process could generate Target specific pseudo
-    // instructions with generic types. Don't record them
-    if (isPreISelGenericOpcode(MI->getOpcode())) {
-      if (isArtifact(*MI))
-        ArtifactList.insert(MI);
-      else
-        InstList.insert(MI);
-    }
-    DEBUG(dbgs() << ".. .. New MI: " << *MI;);
-  });
-  const LegalizerInfo &LInfo(Helper.getLegalizerInfo());
-  LegalizationArtifactCombiner ArtCombiner(Helper.MIRBuilder, MF.getRegInfo(), LInfo);
-  auto RemoveDeadInstFromLists = [&InstList,
-                                  &ArtifactList](MachineInstr *DeadMI) {
-    InstList.remove(DeadMI);
-    ArtifactList.remove(DeadMI);
-  };
-  bool Changed = false;
-  do {
-    while (!InstList.empty()) {
-      MachineInstr &MI = *InstList.pop_back_val();
-      assert(isPreISelGenericOpcode(MI.getOpcode()) && "Expecting generic opcode");
-      if (isTriviallyDead(MI, MRI)) {
-        DEBUG(dbgs() << MI << "Is dead; erasing.\n");
-        MI.eraseFromParentAndMarkDBGValuesForRemoval();
-        continue;
-      }
-
-      // Do the legalization for this instruction.
-      auto Res = Helper.legalizeInstrStep(MI);
-      // Error out if we couldn't legalize this instruction. We may want to
-      // fall back to DAG ISel instead in the future.
-      if (Res == LegalizerHelper::UnableToLegalize) {
-        Helper.MIRBuilder.stopRecordingInsertions();
-        reportGISelFailure(MF, TPC, MORE, "gisel-legalize",
-                           "unable to legalize instruction", MI);
-        return false;
-      }
-      Changed |= Res == LegalizerHelper::Legalized;
-    }
-    while (!ArtifactList.empty()) {
-      MachineInstr &MI = *ArtifactList.pop_back_val();
-      assert(isPreISelGenericOpcode(MI.getOpcode()) && "Expecting generic opcode");
-      if (isTriviallyDead(MI, MRI)) {
-        DEBUG(dbgs() << MI << "Is dead; erasing.\n");
-        RemoveDeadInstFromLists(&MI);
-        MI.eraseFromParentAndMarkDBGValuesForRemoval();
-        continue;
-      }
-      SmallVector<MachineInstr *, 4> DeadInstructions;
-      if (ArtCombiner.tryCombineInstruction(MI, DeadInstructions)) {
-        for (auto *DeadMI : DeadInstructions) {
-          DEBUG(dbgs() << ".. Erasing Dead Instruction " << *DeadMI);
-          RemoveDeadInstFromLists(DeadMI);
-          DeadMI->eraseFromParentAndMarkDBGValuesForRemoval();
-        }
-        Changed = true;
-        continue;
-      }
-      // If this was not an artifact (that could be combined away), this might
-      // need special handling. Add it to InstList, so when it's processed
-      // there, it has to be legal or specially handled.
-      else
-        InstList.insert(&MI);
-    }
-  } while (!InstList.empty());
-
-  // For now don't support if new blocks are inserted - we would need to fix the
-  // outerloop for that.
-  if (MF.size() != NumBlocks) {
-    MachineOptimizationRemarkMissed R("gisel-legalize", "GISelFailure",
-                                      MF.getFunction().getSubprogram(),
-                                      /*MBB=*/nullptr);
-    R << "inserting blocks is not supported yet";
-    reportGISelFailure(MF, TPC, MORE, R);
-    return false;
-  }
-
-  return Changed;
-}

external/llvm/lib/CodeGen/GlobalISel/LegalizerInfo.cpp

@@ -1,382 +0,0 @@
-//===- lib/CodeGen/GlobalISel/LegalizerInfo.cpp - Legalizer ---------------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// Implement an interface to specify and query how an illegal operation on a
-// given type should be expanded.
-//
-// Issues to be resolved:
-//   + Make it fast.
-//   + Support weird types like i3, <7 x i3>, ...
-//   + Operations with more than one type (ICMP, CMPXCHG, intrinsics, ...)
-//
-//===----------------------------------------------------------------------===//
-
-#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
-#include "llvm/ADT/SmallBitVector.h"
-#include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/CodeGen/MachineOperand.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/TargetOpcodes.h"
-#include "llvm/MC/MCInstrDesc.h"
-#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/LowLevelTypeImpl.h"
-#include "llvm/Support/MathExtras.h"
-#include <algorithm>
-#include <map>
-using namespace llvm;
-
-LegalizerInfo::LegalizerInfo() : TablesInitialized(false) {
-  // Set defaults.
-  // FIXME: these two (G_ANYEXT and G_TRUNC?) can be legalized to the
-  // fundamental load/store Jakob proposed. Once loads & stores are supported.
-  setScalarAction(TargetOpcode::G_ANYEXT, 1, {{1, Legal}});
-  setScalarAction(TargetOpcode::G_ZEXT, 1, {{1, Legal}});
-  setScalarAction(TargetOpcode::G_SEXT, 1, {{1, Legal}});
-  setScalarAction(TargetOpcode::G_TRUNC, 0, {{1, Legal}});
-  setScalarAction(TargetOpcode::G_TRUNC, 1, {{1, Legal}});
-
-  setScalarAction(TargetOpcode::G_INTRINSIC, 0, {{1, Legal}});
-  setScalarAction(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS, 0, {{1, Legal}});
-
-  setLegalizeScalarToDifferentSizeStrategy(
-      TargetOpcode::G_IMPLICIT_DEF, 0, narrowToSmallerAndUnsupportedIfTooSmall);
-  setLegalizeScalarToDifferentSizeStrategy(
-      TargetOpcode::G_ADD, 0, widenToLargerTypesAndNarrowToLargest);
-  setLegalizeScalarToDifferentSizeStrategy(
-      TargetOpcode::G_OR, 0, widenToLargerTypesAndNarrowToLargest);
-  setLegalizeScalarToDifferentSizeStrategy(
-      TargetOpcode::G_LOAD, 0, narrowToSmallerAndUnsupportedIfTooSmall);
-  setLegalizeScalarToDifferentSizeStrategy(
-      TargetOpcode::G_STORE, 0, narrowToSmallerAndUnsupportedIfTooSmall);
-
-  setLegalizeScalarToDifferentSizeStrategy(
-      TargetOpcode::G_BRCOND, 0, widenToLargerTypesUnsupportedOtherwise);
-  setLegalizeScalarToDifferentSizeStrategy(
-      TargetOpcode::G_INSERT, 0, narrowToSmallerAndUnsupportedIfTooSmall);
-  setLegalizeScalarToDifferentSizeStrategy(
-      TargetOpcode::G_EXTRACT, 0, narrowToSmallerAndUnsupportedIfTooSmall);
-  setLegalizeScalarToDifferentSizeStrategy(
-      TargetOpcode::G_EXTRACT, 1, narrowToSmallerAndUnsupportedIfTooSmall);
-  setScalarAction(TargetOpcode::G_FNEG, 0, {{1, Lower}});
-}
-
-void LegalizerInfo::computeTables() {
-  assert(TablesInitialized == false);
-
-  for (unsigned OpcodeIdx = 0; OpcodeIdx <= LastOp - FirstOp; ++OpcodeIdx) {
-    const unsigned Opcode = FirstOp + OpcodeIdx;
-    for (unsigned TypeIdx = 0; TypeIdx != SpecifiedActions[OpcodeIdx].size();
-         ++TypeIdx) {
-      // 0. Collect information specified through the setAction API, i.e.
-      // for specific bit sizes.
-      // For scalar types:
-      SizeAndActionsVec ScalarSpecifiedActions;
-      // For pointer types:
-      std::map<uint16_t, SizeAndActionsVec> AddressSpace2SpecifiedActions;
-      // For vector types:
-      std::map<uint16_t, SizeAndActionsVec> ElemSize2SpecifiedActions;
-      for (auto LLT2Action : SpecifiedActions[OpcodeIdx][TypeIdx]) {
-        const LLT Type = LLT2Action.first;
-        const LegalizeAction Action = LLT2Action.second;
-
-        auto SizeAction = std::make_pair(Type.getSizeInBits(), Action);
-        if (Type.isPointer())
-          AddressSpace2SpecifiedActions[Type.getAddressSpace()].push_back(
-              SizeAction);
-        else if (Type.isVector())
-          ElemSize2SpecifiedActions[Type.getElementType().getSizeInBits()]
-              .push_back(SizeAction);
-        else
-          ScalarSpecifiedActions.push_back(SizeAction);
-      }
-
-      // 1. Handle scalar types
-      {
-        // Decide how to handle bit sizes for which no explicit specification
-        // was given.
-        SizeChangeStrategy S = &unsupportedForDifferentSizes;
-        if (TypeIdx < ScalarSizeChangeStrategies[OpcodeIdx].size() &&
-            ScalarSizeChangeStrategies[OpcodeIdx][TypeIdx] != nullptr)
-          S = ScalarSizeChangeStrategies[OpcodeIdx][TypeIdx];
-        std::sort(ScalarSpecifiedActions.begin(), ScalarSpecifiedActions.end());
-        checkPartialSizeAndActionsVector(ScalarSpecifiedActions);
-        setScalarAction(Opcode, TypeIdx, S(ScalarSpecifiedActions));
-      }
-
-      // 2. Handle pointer types
-      for (auto PointerSpecifiedActions : AddressSpace2SpecifiedActions) {
-        std::sort(PointerSpecifiedActions.second.begin(),
-                  PointerSpecifiedActions.second.end());
-        checkPartialSizeAndActionsVector(PointerSpecifiedActions.second);
-        // For pointer types, we assume that there isn't a meaningfull way
-        // to change the number of bits used in the pointer.
-        setPointerAction(
-            Opcode, TypeIdx, PointerSpecifiedActions.first,
-            unsupportedForDifferentSizes(PointerSpecifiedActions.second));
-      }
-
-      // 3. Handle vector types
-      SizeAndActionsVec ElementSizesSeen;
-      for (auto VectorSpecifiedActions : ElemSize2SpecifiedActions) {
-        std::sort(VectorSpecifiedActions.second.begin(),
-                  VectorSpecifiedActions.second.end());
-        const uint16_t ElementSize = VectorSpecifiedActions.first;
-        ElementSizesSeen.push_back({ElementSize, Legal});
-        checkPartialSizeAndActionsVector(VectorSpecifiedActions.second);
-        // For vector types, we assume that the best way to adapt the number
-        // of elements is to the next larger number of elements type for which
-        // the vector type is legal, unless there is no such type. In that case,
-        // legalize towards a vector type with a smaller number of elements.
-        SizeAndActionsVec NumElementsActions;
-        for (SizeAndAction BitsizeAndAction : VectorSpecifiedActions.second) {
-          assert(BitsizeAndAction.first % ElementSize == 0);
-          const uint16_t NumElements = BitsizeAndAction.first / ElementSize;
-          NumElementsActions.push_back({NumElements, BitsizeAndAction.second});
-        }
-        setVectorNumElementAction(
-            Opcode, TypeIdx, ElementSize,
-            moreToWiderTypesAndLessToWidest(NumElementsActions));
-      }
-      std::sort(ElementSizesSeen.begin(), ElementSizesSeen.end());
-      SizeChangeStrategy VectorElementSizeChangeStrategy =
-          &unsupportedForDifferentSizes;
-      if (TypeIdx < VectorElementSizeChangeStrategies[OpcodeIdx].size() &&
-          VectorElementSizeChangeStrategies[OpcodeIdx][TypeIdx] != nullptr)
-        VectorElementSizeChangeStrategy =
-            VectorElementSizeChangeStrategies[OpcodeIdx][TypeIdx];
-      setScalarInVectorAction(
-          Opcode, TypeIdx, VectorElementSizeChangeStrategy(ElementSizesSeen));
-    }
-  }
-
-  TablesInitialized = true;
-}
-
-// FIXME: inefficient implementation for now. Without ComputeValueVTs we're
-// probably going to need specialized lookup structures for various types before
-// we have any hope of doing well with something like <13 x i3>. Even the common
-// cases should do better than what we have now.
-std::pair<LegalizerInfo::LegalizeAction, LLT>
-LegalizerInfo::getAction(const InstrAspect &Aspect) const {
-  assert(TablesInitialized && "backend forgot to call computeTables");
-  // These *have* to be implemented for now, they're the fundamental basis of
-  // how everything else is transformed.
-  if (Aspect.Type.isScalar() || Aspect.Type.isPointer())
-    return findScalarLegalAction(Aspect);
-  assert(Aspect.Type.isVector());
-  return findVectorLegalAction(Aspect);
-}
-
-/// Helper function to get LLT for the given type index.
-static LLT getTypeFromTypeIdx(const MachineInstr &MI,
-                              const MachineRegisterInfo &MRI, unsigned OpIdx,
-                              unsigned TypeIdx) {
-  assert(TypeIdx < MI.getNumOperands() && "Unexpected TypeIdx");
-  // G_UNMERGE_VALUES has variable number of operands, but there is only
-  // one source type and one destination type as all destinations must be the
-  // same type. So, get the last operand if TypeIdx == 1.
-  if (MI.getOpcode() == TargetOpcode::G_UNMERGE_VALUES && TypeIdx == 1)
-    return MRI.getType(MI.getOperand(MI.getNumOperands() - 1).getReg());
-  return MRI.getType(MI.getOperand(OpIdx).getReg());
-}
-
-std::tuple<LegalizerInfo::LegalizeAction, unsigned, LLT>
-LegalizerInfo::getAction(const MachineInstr &MI,
-                         const MachineRegisterInfo &MRI) const {
-  SmallBitVector SeenTypes(8);
-  const MCOperandInfo *OpInfo = MI.getDesc().OpInfo;
-  // FIXME: probably we'll need to cache the results here somehow?
-  for (unsigned i = 0; i < MI.getDesc().getNumOperands(); ++i) {
-    if (!OpInfo[i].isGenericType())
-      continue;
-
-    // We must only record actions once for each TypeIdx; otherwise we'd
-    // try to legalize operands multiple times down the line.
-    unsigned TypeIdx = OpInfo[i].getGenericTypeIndex();
-    if (SeenTypes[TypeIdx])
-      continue;
-
-    SeenTypes.set(TypeIdx);
-
-    LLT Ty = getTypeFromTypeIdx(MI, MRI, i, TypeIdx);
-    auto Action = getAction({MI.getOpcode(), TypeIdx, Ty});
-    if (Action.first != Legal)
-      return std::make_tuple(Action.first, TypeIdx, Action.second);
-  }
-  return std::make_tuple(Legal, 0, LLT{});
-}
-
-bool LegalizerInfo::isLegal(const MachineInstr &MI,
-                            const MachineRegisterInfo &MRI) const {
-  return std::get<0>(getAction(MI, MRI)) == Legal;
-}
-
-bool LegalizerInfo::legalizeCustom(MachineInstr &MI, MachineRegisterInfo &MRI,
-                                   MachineIRBuilder &MIRBuilder) const {
-  return false;
-}
-
-LegalizerInfo::SizeAndActionsVec
-LegalizerInfo::increaseToLargerTypesAndDecreaseToLargest(
-    const SizeAndActionsVec &v, LegalizeAction IncreaseAction,
-    LegalizeAction DecreaseAction) {
-  SizeAndActionsVec result;
-  unsigned LargestSizeSoFar = 0;
-  if (v.size() >= 1 && v[0].first != 1)
-    result.push_back({1, IncreaseAction});
-  for (size_t i = 0; i < v.size(); ++i) {
-    result.push_back(v[i]);
-    LargestSizeSoFar = v[i].first;
-    if (i + 1 < v.size() && v[i + 1].first != v[i].first + 1) {
-      result.push_back({LargestSizeSoFar + 1, IncreaseAction});
-      LargestSizeSoFar = v[i].first + 1;
-    }
-  }
-  result.push_back({LargestSizeSoFar + 1, DecreaseAction});
-  return result;
-}
-
-LegalizerInfo::SizeAndActionsVec
-LegalizerInfo::decreaseToSmallerTypesAndIncreaseToSmallest(
-    const SizeAndActionsVec &v, LegalizeAction DecreaseAction,
-    LegalizeAction IncreaseAction) {
-  SizeAndActionsVec result;
-  if (v.size() == 0 || v[0].first != 1)
-    result.push_back({1, IncreaseAction});
-  for (size_t i = 0; i < v.size(); ++i) {
-    result.push_back(v[i]);
-    if (i + 1 == v.size() || v[i + 1].first != v[i].first + 1) {
-      result.push_back({v[i].first + 1, DecreaseAction});
-    }
-  }
-  return result;
-}
-
-LegalizerInfo::SizeAndAction
-LegalizerInfo::findAction(const SizeAndActionsVec &Vec, const uint32_t Size) {
-  assert(Size >= 1);
-  // Find the last element in Vec that has a bitsize equal to or smaller than
-  // the requested bit size.
-  // That is the element just before the first element that is bigger than Size.
-  auto VecIt = std::upper_bound(
-      Vec.begin(), Vec.end(), Size,
-      [](const uint32_t Size, const SizeAndAction lhs) -> bool {
-        return Size < lhs.first;
-      });
-  assert(VecIt != Vec.begin() && "Does Vec not start with size 1?");
-  --VecIt;
-  int VecIdx = VecIt - Vec.begin();
-
-  LegalizeAction Action = Vec[VecIdx].second;
-  switch (Action) {
-  case Legal:
-  case Lower:
-  case Libcall:
-  case Custom:
-    return {Size, Action};
-  case FewerElements:
-    // FIXME: is this special case still needed and correct?
-    // Special case for scalarization:
-    if (Vec == SizeAndActionsVec({{1, FewerElements}}))
-      return {1, FewerElements};
-    LLVM_FALLTHROUGH;
-  case NarrowScalar: {
-    // The following needs to be a loop, as for now, we do allow needing to
-    // go over "Unsupported" bit sizes before finding a legalizable bit size.
-    // e.g. (s8, WidenScalar), (s9, Unsupported), (s32, Legal). if Size==8,
-    // we need to iterate over s9, and then to s32 to return (s32, Legal).
-    // If we want to get rid of the below loop, we should have stronger asserts
-    // when building the SizeAndActionsVecs, probably not allowing
-    // "Unsupported" unless at the ends of the vector.
-    for (int i = VecIdx - 1; i >= 0; --i)
-      if (!needsLegalizingToDifferentSize(Vec[i].second) &&
-          Vec[i].second != Unsupported)
-        return {Vec[i].first, Action};
-    llvm_unreachable("");
-  }
-  case WidenScalar:
-  case MoreElements: {
-    // See above, the following needs to be a loop, at least for now.
-    for (std::size_t i = VecIdx + 1; i < Vec.size(); ++i)
-      if (!needsLegalizingToDifferentSize(Vec[i].second) &&
-          Vec[i].second != Unsupported)
-        return {Vec[i].first, Action};
-    llvm_unreachable("");
-  }
-  case Unsupported:
-    return {Size, Unsupported};
-  case NotFound:
-    llvm_unreachable("NotFound");
-  }
-  llvm_unreachable("Action has an unknown enum value");
-}
-
-std::pair<LegalizerInfo::LegalizeAction, LLT>
-LegalizerInfo::findScalarLegalAction(const InstrAspect &Aspect) const {
-  assert(Aspect.Type.isScalar() || Aspect.Type.isPointer());
-  if (Aspect.Opcode < FirstOp || Aspect.Opcode > LastOp)
-    return {NotFound, LLT()};
-  const unsigned OpcodeIdx = Aspect.Opcode - FirstOp;
-  if (Aspect.Type.isPointer() &&
-      AddrSpace2PointerActions[OpcodeIdx].find(Aspect.Type.getAddressSpace()) ==
-          AddrSpace2PointerActions[OpcodeIdx].end()) {
-    return {NotFound, LLT()};
-  }
-  const SmallVector<SizeAndActionsVec, 1> &Actions =
-      Aspect.Type.isPointer()
-          ? AddrSpace2PointerActions[OpcodeIdx]
-                .find(Aspect.Type.getAddressSpace())
-                ->second
-          : ScalarActions[OpcodeIdx];
-  if (Aspect.Idx >= Actions.size())
-    return {NotFound, LLT()};
-  const SizeAndActionsVec &Vec = Actions[Aspect.Idx];
-  // FIXME: speed up this search, e.g. by using a results cache for repeated
-  // queries?
-  auto SizeAndAction = findAction(Vec, Aspect.Type.getSizeInBits());
-  return {SizeAndAction.second,
-          Aspect.Type.isScalar() ? LLT::scalar(SizeAndAction.first)
-                                 : LLT::pointer(Aspect.Type.getAddressSpace(),
-                                                SizeAndAction.first)};
-}
-
-std::pair<LegalizerInfo::LegalizeAction, LLT>
-LegalizerInfo::findVectorLegalAction(const InstrAspect &Aspect) const {
-  assert(Aspect.Type.isVector());
-  // First legalize the vector element size, then legalize the number of
-  // lanes in the vector.
-  if (Aspect.Opcode < FirstOp || Aspect.Opcode > LastOp)
-    return {NotFound, Aspect.Type};
-  const unsigned OpcodeIdx = Aspect.Opcode - FirstOp;
-  const unsigned TypeIdx = Aspect.Idx;
-  if (TypeIdx >= ScalarInVectorActions[OpcodeIdx].size())
-    return {NotFound, Aspect.Type};
-  const SizeAndActionsVec &ElemSizeVec =
-      ScalarInVectorActions[OpcodeIdx][TypeIdx];
-
-  LLT IntermediateType;
-  auto ElementSizeAndAction =
-      findAction(ElemSizeVec, Aspect.Type.getScalarSizeInBits());
-  IntermediateType =
-      LLT::vector(Aspect.Type.getNumElements(), ElementSizeAndAction.first);
-  if (ElementSizeAndAction.second != Legal)
-    return {ElementSizeAndAction.second, IntermediateType};
-
-  auto i = NumElements2Actions[OpcodeIdx].find(
-      IntermediateType.getScalarSizeInBits());
-  if (i == NumElements2Actions[OpcodeIdx].end()) {
-    return {NotFound, IntermediateType};
-  }
-  const SizeAndActionsVec &NumElementsVec = (*i).second[TypeIdx];
-  auto NumElementsAndAction =
-      findAction(NumElementsVec, IntermediateType.getNumElements());
-  return {NumElementsAndAction.second,
-          LLT::vector(NumElementsAndAction.first,
-                      IntermediateType.getScalarSizeInBits())};
-}

external/llvm/lib/CodeGen/GlobalISel/Localizer.cpp

@@ -1,124 +0,0 @@
-//===- Localizer.cpp ---------------------- Localize some instrs -*- C++ -*-==//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-/// \file
-/// This file implements the Localizer class.
-//===----------------------------------------------------------------------===//
-
-#include "llvm/CodeGen/GlobalISel/Localizer.h"
-#include "llvm/ADT/DenseMap.h"
-#include "llvm/ADT/SmallPtrSet.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/Support/Debug.h"
-
-#define DEBUG_TYPE "localizer"
-
-using namespace llvm;
-
-char Localizer::ID = 0;
-INITIALIZE_PASS(Localizer, DEBUG_TYPE,
-                "Move/duplicate certain instructions close to their use", false,
-                false)
-
-Localizer::Localizer() : MachineFunctionPass(ID) {
-  initializeLocalizerPass(*PassRegistry::getPassRegistry());
-}
-
-void Localizer::init(MachineFunction &MF) { MRI = &MF.getRegInfo(); }
-
-bool Localizer::shouldLocalize(const MachineInstr &MI) {
-  switch (MI.getOpcode()) {
-  default:
-    return false;
-  // Constants-like instructions should be close to their users.
-  // We don't want long live-ranges for them.
-  case TargetOpcode::G_CONSTANT:
-  case TargetOpcode::G_FCONSTANT:
-  case TargetOpcode::G_FRAME_INDEX:
-    return true;
-  }
-}
-
-bool Localizer::isLocalUse(MachineOperand &MOUse, const MachineInstr &Def,
-                           MachineBasicBlock *&InsertMBB) {
-  MachineInstr &MIUse = *MOUse.getParent();
-  InsertMBB = MIUse.getParent();
-  if (MIUse.isPHI())
-    InsertMBB = MIUse.getOperand(MIUse.getOperandNo(&MOUse) + 1).getMBB();
-  return InsertMBB == Def.getParent();
-}
-
-bool Localizer::runOnMachineFunction(MachineFunction &MF) {
-  // If the ISel pipeline failed, do not bother running that pass.
-  if (MF.getProperties().hasProperty(
-          MachineFunctionProperties::Property::FailedISel))
-    return false;
-
-  DEBUG(dbgs() << "Localize instructions for: " << MF.getName() << '\n');
-
-  init(MF);
-
-  bool Changed = false;
-  // Keep track of the instructions we localized.
-  // We won't need to process them if we see them later in the CFG.
-  SmallPtrSet<MachineInstr *, 16> LocalizedInstrs;
-  DenseMap<std::pair<MachineBasicBlock *, unsigned>, unsigned> MBBWithLocalDef;
-  // TODO: Do bottom up traversal.
-  for (MachineBasicBlock &MBB : MF) {
-    for (MachineInstr &MI : MBB) {
-      if (LocalizedInstrs.count(&MI) || !shouldLocalize(MI))
-        continue;
-      DEBUG(dbgs() << "Should localize: " << MI);
-      assert(MI.getDesc().getNumDefs() == 1 &&
-             "More than one definition not supported yet");
-      unsigned Reg = MI.getOperand(0).getReg();
-      // Check if all the users of MI are local.
-      // We are going to invalidation the list of use operands, so we
-      // can't use range iterator.
-      for (auto MOIt = MRI->use_begin(Reg), MOItEnd = MRI->use_end();
-           MOIt != MOItEnd;) {
-        MachineOperand &MOUse = *MOIt++;
-        // Check if the use is already local.
-        MachineBasicBlock *InsertMBB;
-        DEBUG(MachineInstr &MIUse = *MOUse.getParent();
-              dbgs() << "Checking use: " << MIUse
-                     << " #Opd: " << MIUse.getOperandNo(&MOUse) << '\n');
-        if (isLocalUse(MOUse, MI, InsertMBB))
-          continue;
-        DEBUG(dbgs() << "Fixing non-local use\n");
-        Changed = true;
-        auto MBBAndReg = std::make_pair(InsertMBB, Reg);
-        auto NewVRegIt = MBBWithLocalDef.find(MBBAndReg);
-        if (NewVRegIt == MBBWithLocalDef.end()) {
-          // Create the localized instruction.
-          MachineInstr *LocalizedMI = MF.CloneMachineInstr(&MI);
-          LocalizedInstrs.insert(LocalizedMI);
-          // Don't try to be smart for the insertion point.
-          // There is no guarantee that the first seen use is the first
-          // use in the block.
-          InsertMBB->insert(InsertMBB->SkipPHIsAndLabels(InsertMBB->begin()),
-                            LocalizedMI);
-
-          // Set a new register for the definition.
-          unsigned NewReg =
-              MRI->createGenericVirtualRegister(MRI->getType(Reg));
-          MRI->setRegClassOrRegBank(NewReg, MRI->getRegClassOrRegBank(Reg));
-          LocalizedMI->getOperand(0).setReg(NewReg);
-          NewVRegIt =
-              MBBWithLocalDef.insert(std::make_pair(MBBAndReg, NewReg)).first;
-          DEBUG(dbgs() << "Inserted: " << *LocalizedMI);
-        }
-        DEBUG(dbgs() << "Update use with: " << printReg(NewVRegIt->second)
-                     << '\n');
-        // Update the user reg.
-        MOUse.setReg(NewVRegIt->second);
-      }
-    }
-  }
-  return Changed;
-}

external/llvm/lib/CodeGen/GlobalISel/RegisterBank.cpp

@@ -1,113 +0,0 @@
-//===- llvm/CodeGen/GlobalISel/RegisterBank.cpp - Register Bank --*- C++ -*-==//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-/// \file
-/// This file implements the RegisterBank class.
-//===----------------------------------------------------------------------===//
-
-#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
-#include "llvm/CodeGen/TargetRegisterInfo.h"
-
-#define DEBUG_TYPE "registerbank"
-
-using namespace llvm;
-
-const unsigned RegisterBank::InvalidID = UINT_MAX;
-
-RegisterBank::RegisterBank(
-    unsigned ID, const char *Name, unsigned Size,
-    const uint32_t *CoveredClasses, unsigned NumRegClasses)
-    : ID(ID), Name(Name), Size(Size) {
-  ContainedRegClasses.resize(NumRegClasses);
-  ContainedRegClasses.setBitsInMask(CoveredClasses);
-}
-
-bool RegisterBank::verify(const TargetRegisterInfo &TRI) const {
-  assert(isValid() && "Invalid register bank");
-  for (unsigned RCId = 0, End = TRI.getNumRegClasses(); RCId != End; ++RCId) {
-    const TargetRegisterClass &RC = *TRI.getRegClass(RCId);
-
-    if (!covers(RC))
-      continue;
-    // Verify that the register bank covers all the sub classes of the
-    // classes it covers.
-
-    // Use a different (slow in that case) method than
-    // RegisterBankInfo to find the subclasses of RC, to make sure
-    // both agree on the covers.
-    for (unsigned SubRCId = 0; SubRCId != End; ++SubRCId) {
-      const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId);
-
-      if (!RC.hasSubClassEq(&SubRC))
-        continue;
-
-      // Verify that the Size of the register bank is big enough to cover
-      // all the register classes it covers.
-      assert(getSize() >= TRI.getRegSizeInBits(SubRC) &&
-             "Size is not big enough for all the subclasses!");
-      assert(covers(SubRC) && "Not all subclasses are covered");
-    }
-  }
-  return true;
-}
-
-bool RegisterBank::covers(const TargetRegisterClass &RC) const {
-  assert(isValid() && "RB hasn't been initialized yet");
-  return ContainedRegClasses.test(RC.getID());
-}
-
-bool RegisterBank::isValid() const {
-  return ID != InvalidID && Name != nullptr && Size != 0 &&
-         // A register bank that does not cover anything is useless.
-         !ContainedRegClasses.empty();
-}
-
-bool RegisterBank::operator==(const RegisterBank &OtherRB) const {
-  // There must be only one instance of a given register bank alive
-  // for the whole compilation.
-  // The RegisterBankInfo is supposed to enforce that.
-  assert((OtherRB.getID() != getID() || &OtherRB == this) &&
-         "ID does not uniquely identify a RegisterBank");
-  return &OtherRB == this;
-}
-
-#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
-LLVM_DUMP_METHOD void RegisterBank::dump(const TargetRegisterInfo *TRI) const {
-  print(dbgs(), /* IsForDebug */ true, TRI);
-}
-#endif
-
-void RegisterBank::print(raw_ostream &OS, bool IsForDebug,
-                         const TargetRegisterInfo *TRI) const {
-  OS << getName();
-  if (!IsForDebug)
-    return;
-  OS << "(ID:" << getID() << ", Size:" << getSize() << ")\n"
-     << "isValid:" << isValid() << '\n'
-     << "Number of Covered register classes: " << ContainedRegClasses.count()
-     << '\n';
-  // Print all the subclasses if we can.
-  // This register classes may not be properly initialized yet.
-  if (!TRI || ContainedRegClasses.empty())
-    return;
-  assert(ContainedRegClasses.size() == TRI->getNumRegClasses() &&
-         "TRI does not match the initialization process?");
-  bool IsFirst = true;
-  OS << "Covered register classes:\n";
-  for (unsigned RCId = 0, End = TRI->getNumRegClasses(); RCId != End; ++RCId) {
-    const TargetRegisterClass &RC = *TRI->getRegClass(RCId);
-
-    if (!covers(RC))
-      continue;
-
-    if (!IsFirst)
-      OS << ", ";
-    OS << TRI->getRegClassName(&RC);
-    IsFirst = false;
-  }
-}

external/llvm/lib/CodeGen/GlobalISel/Utils.cpp

@@ -1,147 +0,0 @@
-//===- llvm/CodeGen/GlobalISel/Utils.cpp -------------------------*- C++ -*-==//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-/// \file This file implements the utility functions used by the GlobalISel
-/// pipeline.
-//===----------------------------------------------------------------------===//
-
-#include "llvm/CodeGen/GlobalISel/Utils.h"
-#include "llvm/ADT/Twine.h"
-#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
-#include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/TargetInstrInfo.h"
-#include "llvm/CodeGen/TargetPassConfig.h"
-#include "llvm/CodeGen/TargetRegisterInfo.h"
-#include "llvm/IR/Constants.h"
-
-#define DEBUG_TYPE "globalisel-utils"
-
-using namespace llvm;
-
-unsigned llvm::constrainRegToClass(MachineRegisterInfo &MRI,
-                                   const TargetInstrInfo &TII,
-                                   const RegisterBankInfo &RBI,
-                                   MachineInstr &InsertPt, unsigned Reg,
-                                   const TargetRegisterClass &RegClass) {
-  if (!RBI.constrainGenericRegister(Reg, RegClass, MRI)) {
-    unsigned NewReg = MRI.createVirtualRegister(&RegClass);
-    BuildMI(*InsertPt.getParent(), InsertPt, InsertPt.getDebugLoc(),
-            TII.get(TargetOpcode::COPY), NewReg)
-        .addReg(Reg);
-    return NewReg;
-  }
-
-  return Reg;
-}
-
-
-unsigned llvm::constrainOperandRegClass(
-    const MachineFunction &MF, const TargetRegisterInfo &TRI,
-    MachineRegisterInfo &MRI, const TargetInstrInfo &TII,
-    const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II,
-    unsigned Reg, unsigned OpIdx) {
-  // Assume physical registers are properly constrained.
-  assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
-         "PhysReg not implemented");
-
-  const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF);
-  return constrainRegToClass(MRI, TII, RBI, InsertPt, Reg, *RegClass);
-}
-
-bool llvm::isTriviallyDead(const MachineInstr &MI,
-                           const MachineRegisterInfo &MRI) {
-  // If we can move an instruction, we can remove it.  Otherwise, it has
-  // a side-effect of some sort.
-  bool SawStore = false;
-  if (!MI.isSafeToMove(/*AA=*/nullptr, SawStore))
-    return false;
-
-  // Instructions without side-effects are dead iff they only define dead vregs.
-  for (auto &MO : MI.operands()) {
-    if (!MO.isReg() || !MO.isDef())
-      continue;
-
-    unsigned Reg = MO.getReg();
-    if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
-        !MRI.use_nodbg_empty(Reg))
-      return false;
-  }
-  return true;
-}
-
-void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
-                              MachineOptimizationRemarkEmitter &MORE,
-                              MachineOptimizationRemarkMissed &R) {
-  MF.getProperties().set(MachineFunctionProperties::Property::FailedISel);
-
-  // Print the function name explicitly if we don't have a debug location (which
-  // makes the diagnostic less useful) or if we're going to emit a raw error.
-  if (!R.getLocation().isValid() || TPC.isGlobalISelAbortEnabled())
-    R << (" (in function: " + MF.getName() + ")").str();
-
-  if (TPC.isGlobalISelAbortEnabled())
-    report_fatal_error(R.getMsg());
-  else
-    MORE.emit(R);
-}
-
-void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
-                              MachineOptimizationRemarkEmitter &MORE,
-                              const char *PassName, StringRef Msg,
-                              const MachineInstr &MI) {
-  MachineOptimizationRemarkMissed R(PassName, "GISelFailure: ",
-                                    MI.getDebugLoc(), MI.getParent());
-  R << Msg;
-  // Printing MI is expensive;  only do it if expensive remarks are enabled.
-  if (MORE.allowExtraAnalysis(PassName))
-    R << ": " << ore::MNV("Inst", MI);
-  reportGISelFailure(MF, TPC, MORE, R);
-}
-
-Optional<int64_t> llvm::getConstantVRegVal(unsigned VReg,
-                                           const MachineRegisterInfo &MRI) {
-  MachineInstr *MI = MRI.getVRegDef(VReg);
-  if (MI->getOpcode() != TargetOpcode::G_CONSTANT)
-    return None;
-
-  if (MI->getOperand(1).isImm())
-    return MI->getOperand(1).getImm();
-
-  if (MI->getOperand(1).isCImm() &&
-      MI->getOperand(1).getCImm()->getBitWidth() <= 64)
-    return MI->getOperand(1).getCImm()->getSExtValue();
-
-  return None;
-}
-
-const llvm::ConstantFP* llvm::getConstantFPVRegVal(unsigned VReg,
-                                       const MachineRegisterInfo &MRI) {
-  MachineInstr *MI = MRI.getVRegDef(VReg);
-  if (TargetOpcode::G_FCONSTANT != MI->getOpcode())
-    return nullptr;
-  return MI->getOperand(1).getFPImm();
-}
-
-llvm::MachineInstr *llvm::getOpcodeDef(unsigned Opcode, unsigned Reg,
-                                       const MachineRegisterInfo &MRI) {
-  auto *DefMI = MRI.getVRegDef(Reg);
-  auto DstTy = MRI.getType(DefMI->getOperand(0).getReg());
-  if (!DstTy.isValid())
-    return nullptr;
-  while (DefMI->getOpcode() == TargetOpcode::COPY) {
-    unsigned SrcReg = DefMI->getOperand(1).getReg();
-    auto SrcTy = MRI.getType(SrcReg);
-    if (!SrcTy.isValid() || SrcTy != DstTy)
-      break;
-    DefMI = MRI.getVRegDef(SrcReg);
-  }
-  return DefMI->getOpcode() == Opcode ? DefMI : nullptr;
-}