Imported Upstream version 5.18.0.205

Former-commit-id: 7f59f7e792705db773f1caecdaa823092f4e2927

external/llvm/test/TableGen/2003-08-03-PassCode.td

@@ -0,0 +1,7 @@
+// RUN: llvm-tblgen %s
+
+class test<code C> {
+  code Code = C;
+}
+
+def foo : test<[{ hello world! }]>;

external/llvm/test/TableGen/2006-09-18-LargeInt.td

@@ -0,0 +1,7 @@
+// RUN: llvm-tblgen %s | FileCheck %s
+
+// CHECK: 4294901760
+
+def X {
+  int Y = 0xFFFF0000;
+}

external/llvm/test/TableGen/2010-03-24-PrematureDefaults.td

@@ -0,0 +1,44 @@
+// RUN: llvm-tblgen %s | FileCheck %s
+// XFAIL: vg_leak
+
+class A<int k, bits<2> x = 1> {
+  int K = k;
+  bits<2> Bits = x;
+}
+
+// CHECK: def a1
+// CHECK: Bits = { 0, 1 }
+def a1 : A<12>;
+
+// CHECK: def a2
+// CHECK: Bits = { 1, 0 }
+def a2 : A<13, 2>;
+
+// Here was the bug: X.Bits would get resolved to the default a1.Bits while
+// resolving the first template argument. When the second template argument
+// was processed, X would be set correctly, but Bits retained the default
+// value.
+class B<int k, A x = a1> {
+  A X = x;
+  bits<2> Bits = X.Bits;
+}
+
+// CHECK: def b1
+// CHECK: Bits = { 0, 1 }
+def b1 : B<27>;
+
+// CHECK: def b2
+// CHECK: Bits = { 1, 0 }
+def b2 : B<28, a2>;
+
+class C<A x = a1> {
+  bits<2> Bits = x.Bits;
+}
+
+// CHECK: def c1
+// CHECK: Bits = { 0, 1 }
+def c1 : C;
+
+// CHECK: def c2
+// CHECK: Bits = { 1, 0 }
+def c2 : C<a2>;

external/llvm/test/TableGen/AllowDuplicateRegisterNames.td

@@ -0,0 +1,86 @@
+// RUN: llvm-tblgen -gen-asm-matcher -I %p/../../include %s | FileCheck %s
+
+// Check that MatchRegisterName and MatchRegisterAltName are generated
+// correctly when multiple registers are defined with the same name and
+// AllowDuplicateRegisterNames is set.
+
+include "llvm/Target/Target.td"
+
+def ArchInstrInfo : InstrInfo;
+
+def ArchAsmParser : AsmParser {
+  let AllowDuplicateRegisterNames = 1;
+  let ShouldEmitMatchRegisterAltName = 1;
+}
+
+def Arch : Target {
+  let InstructionSet = ArchInstrInfo;
+  let AssemblyParsers = [ArchAsmParser];
+}
+
+let Namespace = "Arch" in {
+class ArchReg<string n, list <string> alt, list <RegAltNameIndex> altidx>
+    : Register<n> {
+  let AltNames = alt;
+  let RegAltNameIndices = altidx;
+}
+
+def ABIRegAltName : RegAltNameIndex;
+
+foreach i = 0-3 in {
+  def R#i#_32 : ArchReg<"r"#i, ["x"#i], [ABIRegAltName]>;
+  def R#i#_64 : ArchReg<"r"#i, ["x"#i], [ABIRegAltName]>;
+}
+} // Namespace = "Arch"
+
+def GPR32 : RegisterClass<"Arch", [i32], 32, (add
+    (sequence "R%u_32", 0, 3)
+)>;
+
+def GPR64 : RegisterClass<"Arch", [i64], 64, (add
+    (sequence "R%u_64", 0, 3)
+)>;
+
+// CHECK: static unsigned MatchRegisterName(StringRef Name) {
+// CHECK:   switch (Name.size()) {
+// CHECK:   default: break;
+// CHECK:   case 2:  // 8 strings to match.
+// CHECK:     if (Name[0] != 'r')
+// CHECK:       break;
+// CHECK:     switch (Name[1]) {
+// CHECK:     default: break;
+// CHECK:     case '0':  // 2 strings to match.
+// CHECK:       return 1;  // "r0"
+// CHECK:     case '1':  // 2 strings to match.
+// CHECK:       return 3;  // "r1"
+// CHECK:     case '2':  // 2 strings to match.
+// CHECK:       return 5;  // "r2"
+// CHECK:     case '3':  // 2 strings to match.
+// CHECK:       return 7;  // "r3"
+// CHECK:     }
+// CHECK:     break;
+// CHECK:   }
+// CHECK:   return 0;
+// CHECK: }
+
+// CHECK: static unsigned MatchRegisterAltName(StringRef Name) {
+// CHECK:   switch (Name.size()) {
+// CHECK:   default: break;
+// CHECK:   case 2:  // 8 strings to match.
+// CHECK:     if (Name[0] != 'x')
+// CHECK:       break;
+// CHECK:     switch (Name[1]) {
+// CHECK:     default: break;
+// CHECK:     case '0':  // 2 strings to match.
+// CHECK:       return 1;  // "x0"
+// CHECK:     case '1':  // 2 strings to match.
+// CHECK:       return 3;  // "x1"
+// CHECK:     case '2':  // 2 strings to match.
+// CHECK:       return 5;  // "x2"
+// CHECK:     case '3':  // 2 strings to match.
+// CHECK:       return 7;  // "x3"
+// CHECK:     }
+// CHECK:     break;
+// CHECK:   }
+// CHECK:   return 0;
+// CHECK: }

external/llvm/test/TableGen/AnonDefinitionOnDemand.td

@@ -0,0 +1,13 @@
+// RUN: llvm-tblgen < %s
+// XFAIL: vg_leak
+
+class foo<int X> { int THEVAL = X; }
+def foo_imp : foo<1>;
+
+def x {
+  foo Y = foo_imp;    // This works.
+}
+
+def X {
+  foo Y = foo<1>;     // This should work too, synthesizing a new foo<1>.
+}

external/llvm/test/TableGen/AsmPredicateCondsEmission.td

@@ -0,0 +1,31 @@
+// RUN: llvm-tblgen -gen-disassembler -I %p/../../include %s | FileCheck %s
+
+// Check that we don't generate invalid code of the form "( && Cond2)" when
+// emitting AssemblerPredicate conditions. In the example below, the invalid
+// code would be: "return ( && (Bits & arch::AssemblerCondition2));".
+
+include "llvm/Target/Target.td"
+
+def archInstrInfo : InstrInfo { }
+
+def arch : Target {
+  let InstructionSet = archInstrInfo;
+}
+
+def Pred1 : Predicate<"Condition1">;
+def Pred2 : Predicate<"Condition2">,
+            AssemblerPredicate<"AssemblerCondition2">;
+
+def foo : Instruction {
+  let Size = 2;
+  let OutOperandList = (outs);
+  let InOperandList = (ins);
+  field bits<16> Inst;
+  let Inst = 0xAAAA;
+  let AsmString = "foo";
+  field bits<16> SoftFail = 0;
+  // This is the important bit:
+  let Predicates = [Pred1, Pred2];
+}
+
+// CHECK: return (Bits[arch::AssemblerCondition2]);

external/llvm/test/TableGen/AsmVariant.td

@@ -0,0 +1,47 @@
+// RUN: llvm-tblgen -gen-asm-matcher -I %p/../../include %s | FileCheck %s
+
+// Check that specifying AsmVariant works correctly
+
+include "llvm/Target/Target.td"
+
+def ArchInstrInfo : InstrInfo { }
+
+def FooAsmParserVariant : AsmParserVariant {
+  let Variant = 0;
+  let Name = "Foo";
+}
+
+def BarAsmParserVariant : AsmParserVariant {
+  let Variant = 1;
+  let Name = "Bar";
+}
+
+def Arch : Target {
+  let InstructionSet = ArchInstrInfo;
+  let AssemblyParserVariants = [FooAsmParserVariant, BarAsmParserVariant];
+}
+
+def Reg : Register<"reg">;
+
+def RegClass : RegisterClass<"foo", [i32], 0, (add Reg)>;
+
+def foo : Instruction {
+  let Size = 2;
+  let OutOperandList = (outs);
+  let InOperandList = (ins);
+  let AsmString = "foo";
+  let AsmVariantName = "Foo";
+  let Namespace = "Arch";
+}
+
+def BarAlias : InstAlias<"bar", (foo)> {
+  string AsmVariantName = "Bar";
+}
+
+// CHECK: static const MatchEntry MatchTable0[] = {
+// CHECK-NEXT: /* foo */, Arch::foo
+// CHECK-NEXT: };
+
+// CHECK: static const MatchEntry MatchTable1[] = {
+// CHECK-NEXT: /* bar */, Arch::foo
+// CHECK-NEXT: };

external/llvm/test/TableGen/BitOffsetDecoder.td

@@ -0,0 +1,74 @@
+// RUN: llvm-tblgen -gen-disassembler -I %p/../../include %s | FileCheck %s
+
+include "llvm/Target/Target.td"
+
+def archInstrInfo : InstrInfo { }
+
+def arch : Target {
+    let InstructionSet = archInstrInfo;
+}
+
+def  Myi32  : Operand<i32> {
+  let DecoderMethod = "DecodeMyi32";
+}
+
+
+let OutOperandList = (outs), Size = 2 in {
+
+def foo : Instruction {
+    let InOperandList = (ins i32imm:$factor);
+    field bits<16> Inst;
+    bits<32> factor;
+    let Inst{7-0} = 0xAA;
+    let Inst{14-8} = factor{6-0}; // no offset
+    let AsmString = "foo  $factor";
+    field bits<16> SoftFail = 0;
+    }
+
+def bar : Instruction {
+    let InOperandList = (ins i32imm:$factor);
+    field bits<16> Inst;
+    bits<32> factor;
+    let Inst{7-0} = 0xBB;
+    let Inst{15-8} = factor{10-3}; // offset by 3
+    let AsmString = "bar  $factor";
+    field bits<16> SoftFail = 0;
+    }
+
+def biz : Instruction {
+    let InOperandList = (ins i32imm:$factor);
+    field bits<16> Inst;
+    bits<32> factor;
+    let Inst{7-0} = 0xCC;
+    let Inst{11-8,15-12} = factor{10-3}; // offset by 3, multipart
+    let AsmString = "biz  $factor";
+    field bits<16> SoftFail = 0;
+    }
+
+def baz : Instruction {
+    let InOperandList = (ins Myi32:$factor);
+    field bits<16> Inst;
+    bits<32> factor;
+    let Inst{7-0} = 0xDD;
+    let Inst{15-8} = factor{11-4}; // offset by 4 + custom decode
+    let AsmString = "baz  $factor";
+    field bits<16> SoftFail = 0;
+    }
+
+def bum : Instruction {
+    let InOperandList = (ins i32imm:$factor);
+    field bits<16> Inst;
+    bits<32> factor;
+    let Inst{7-0} = 0xEE;
+    let Inst{15-8} = !srl(factor,5);
+    let AsmString = "bum  $factor";
+    field bits<16> SoftFail = 0;
+    }
+}
+
+
+// CHECK: tmp = fieldFromInstruction(insn, 8, 7);
+// CHECK: tmp = fieldFromInstruction(insn, 8, 8) << 3;
+// CHECK: tmp |= fieldFromInstruction(insn, 8, 4) << 7;
+// CHECK: tmp |= fieldFromInstruction(insn, 12, 4) << 3;
+// CHECK: tmp = fieldFromInstruction(insn, 8, 8) << 4;

external/llvm/test/TableGen/BitsInit.td

@@ -0,0 +1,85 @@
+
+// RUN: not llvm-tblgen %s 2>&1 > %t
+// RUN: FileCheck %s < %t
+
+def a {
+  bits<2> opc = { 0, 1 };
+  bits<2> opc2 = { 1, 0 };
+  bits<1> opc3 = { 1 };
+  bits<2> a = { opc, opc2 }; // error!
+  bits<2> b = { opc{0}, opc2{0} };
+  bits<2> c = { opc{1}, opc2{1} };
+  bits<2> c = { opc3{0}, opc3 };
+}
+
+// CHECK: def a {
+// CHECK:   bits<2> opc = { 0, 1 };
+// CHECK:   bits<2> opc2 = { 1, 0 };
+// CHECK:   bits<1> opc3 = { 1 };
+// CHECK:   bits<2> a;
+// CHECK:   bits<2> b = { 1, 0 };
+// CHECK:   bits<2> c = { 1, 1 };
+// CHECK: }
+
+def {
+  bits<2> B1 = 0b011;  // bitfield is too small, reject
+  bits<3> B2 = 0b011;  // ok
+
+  bits<2> C1 = 0b111;  // bitfield is too small, reject
+  bits<3> C2 = 0b111;  // ok
+
+  bits<2> D1 = { 0, 0 }; // ok
+  bits<2> D2 = { 0b00 }; // ok
+  bits<3> D3 = { 0, 0 }; // type mismatch.  RHS doesn't have enough bits
+  bits<3> D4 = { 0b00 }; // type mismatch.  RHS doesn't have enough bits
+  bits<1> D5 = { 0 };    // ok
+  bits<1> D6 = { 1 };    // ok
+  bits<1> D7 = { 3 };    // type mismatch.  LHS doesn't have enough bits
+  bits<2> D8 = { 0 };    // type mismatch.  RHS doesn't have enough bits
+
+  bits<8> E;
+  let E{7-0} = {0,0,1,?,?,?,?,?};
+  let E{3-0} = 0b0010;
+
+  bits<8> F1 = { 0, 1, 0b1001, 0, 0b0 }; // ok
+  bits<7> F2 = { 0, 1, 0b1001, 0, 0b0 }; // LHS doesn't have enough bits
+  bits<9> F3 = { 0, 1, 0b1001, 0, 0b0 }; // RHS doesn't have enough bits
+
+  bits<8> G1 = { 0, { 1, 0b1001, 0 }, 0b0 }; // ok
+  bits<8> G2 = { 0, { 1, 0b1001 }, 0, 0b0 }; // ok
+  bits<8> G3 = { 0, 1, { 0b1001 }, 0, 0b0 }; // ok
+
+  bits<16> H;
+  let H{15-0} = { { 0b11001100 }, 0b00110011 };
+  bits<16> I = { G1, G2 };
+
+  // Make sure we can initialise ints with bits<> values.
+  int J = H;
+  int K = { 0, 1 };
+}
+
+// CHECK: def {{.*}} {
+// CHECK: bits<2> B1;
+// CHECK: bits<3> B2 = { 0, 1, 1 };
+// CHECK: bits<2> C1;
+// CHECK: bits<3> C2 = { 1, 1, 1 };
+// CHECK: bits<2> D1 = { 0, 0 };
+// CHECK: bits<2> D2 = { 0, 0 };
+// CHECK: bits<3> D3;
+// CHECK: bits<3> D4;
+// CHECK: bits<1> D5 = { 0 };
+// CHECK: bits<1> D6 = { 1 };
+// CHECK: bits<1> D7 = { ? };
+// CHECK: bits<2> D8;
+// CHECK: bits<8> E = { 0, 0, 1, ?, 0, 0, 1, 0 };
+// CHECK: bits<8> F1 = { 0, 1, 1, 0, 0, 1, 0, 0 };
+// CHECK: bits<7> F2;
+// CHECK: bits<9> F3;
+// CHECK: bits<8> G1 = { 0, 1, 1, 0, 0, 1, 0, 0 };
+// CHECK: bits<8> G2 = { 0, 1, 1, 0, 0, 1, 0, 0 };
+// CHECK: bits<8> G3 = { 0, 1, 1, 0, 0, 1, 0, 0 };
+// CHECK: bits<16> H = { 1, 1, 0, 0, 1, 1, 0, 0, 0, 0, 1, 1, 0, 0, 1, 1 };
+// CHECK: bits<16> I = { 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0 };
+// CHECK: int J = 52275;
+// CHECK: int K = 1;
+// CHECK: }

external/llvm/test/TableGen/BitsInitOverflow.td

@@ -0,0 +1,5 @@
+// RUN: not llvm-tblgen %s 2> /dev/null
+
+def {
+  bits<2> X = 5;  // bitfield is too small, reject
+}

external/llvm/test/TableGen/CStyleComment.td

@@ -0,0 +1,14 @@
+// Test that multiline, nested, comments work correctly.
+//
+// RUN: llvm-tblgen < %s
+
+/* Foo
+  bar
+  /* 
+  blah
+  */
+
+  stuff
+  */
+
+def x;

external/llvm/test/TableGen/ClassInstanceValue.td

@@ -0,0 +1,19 @@
+// RUN: llvm-tblgen %s | FileCheck %s
+// XFAIL: vg_leak
+
+class Struct<int i> {
+  int I = !shl(i, 1);
+  int J = !shl(I, 1);
+}
+
+class Class<Struct s> {
+    int Class_J = s.J;
+}
+
+multiclass MultiClass<int i> {
+  def Def : Class<Struct<i>>;
+// CHECK: Class_J = 8
+// CHECK-NOT: Class_J = !shl(I, 1)
+}
+
+defm Defm : MultiClass<2>;

external/llvm/test/TableGen/ConcatenatedSubregs.td

@@ -0,0 +1,130 @@
+// RUN: llvm-tblgen -gen-register-info -register-info-debug -I %p/../../include %s -o /dev/null 2>&1 | FileCheck %s
+// Checks that tablegen correctly and completely infers subregister relations.
+include "llvm/Target/Target.td"
+
+class MyReg<string n, list<Register> subregs = []>
+  : Register<n> {
+  let Namespace = "Test";
+  let SubRegs = subregs;
+  let CoveredBySubRegs = 1;
+}
+class MyClass<int size, list<ValueType> types, dag registers>
+  : RegisterClass<"Test", types, size, registers> {
+  let Size = size;
+}
+
+// Register Example:
+// D0_D1 -- D0 (sub0) -- S0 (ssub0)
+//       \            \- S1 (ssub1)
+//        \ D1 (sub1) -- S2 (ssub2)
+//                    \- S3 (ssub3)
+
+def sub0 : SubRegIndex<32>;
+def sub1 : SubRegIndex<32, 32>;
+def sub2 : SubRegIndex<32, 64>;
+
+def ssub0 : SubRegIndex<16>;
+def ssub1 : SubRegIndex<16, 16>;
+def ssub2 : ComposedSubRegIndex<sub1, ssub0>;
+def ssub3 : ComposedSubRegIndex<sub1, ssub1>;
+def ssub4 : ComposedSubRegIndex<sub2, ssub0>;
+
+def S0 : MyReg<"s0">;
+def S1 : MyReg<"s1">;
+def S2 : MyReg<"s2">;
+def S3 : MyReg<"s3">;
+def S4 : MyReg<"s4">;
+def S5 : MyReg<"s5">;
+def S6 : MyReg<"s6">;
+def S7 : MyReg<"s7">;
+def S8 : MyReg<"s8">;
+def S9 : MyReg<"s9">;
+def S10 : MyReg<"s10">;
+def S11 : MyReg<"s11">;
+def S12 : MyReg<"s12">;
+def S13 : MyReg<"s13">;
+def S14 : MyReg<"s14">;
+def S15 : MyReg<"s15">;
+def SRegs : MyClass<16, [i16], (sequence "S%u", 0, 15)>;
+
+let SubRegIndices = [ssub0, ssub1] in {
+def D0 : MyReg<"d0", [S0, S1]>;
+def D1 : MyReg<"d1", [S2, S3]>;
+def D2 : MyReg<"d2", [S4, S5]>;
+def D3 : MyReg<"d3", [S6, S7]>;
+def D4 : MyReg<"d4", [S8, S9]>;
+def D5 : MyReg<"d5", [S10, S11]>;
+def D6 : MyReg<"d6", [S12, S13]>;
+def D7 : MyReg<"d7", [S14, S15]>;
+}
+def DRegs : MyClass<32, [i32], (sequence "D%u", 0, 7)>;
+
+def Dtup2regs : RegisterTuples<[sub0, sub1],
+                           [(shl DRegs, 0), (shl DRegs, 1)]>;
+def Dtup2 : MyClass<64, [untyped], (add Dtup2regs)>;
+
+def Stup2_odds_regs : RegisterTuples<[ssub0, ssub1],
+                                     [(decimate (shl SRegs, 1), 2),
+                                      (decimate (shl SRegs, 2), 2)]>;
+def Stup2 : MyClass<32, [untyped], (interleave DRegs, Stup2_odds_regs)>;
+
+def Stup5 : RegisterTuples<[ssub0, ssub1, ssub2, ssub3, ssub4], [
+                            (shl SRegs, 0),
+                            (shl SRegs, 1),
+                            (shl SRegs, 2),
+                            (shl SRegs, 3),
+                            (shl SRegs, 4)
+                           ]>;
+
+
+def TestTarget : Target;
+
+// CHECK-LABEL: RegisterClass SRegs:
+// CHECK: CoveredBySubRegs: 1
+// CHECK: Regs: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15
+
+// CHECK-LABEL: RegisterClass Stup2:
+// CHECK: CoveredBySubRegs: 1
+// CHECK: Regs: D0 D1 D2 D3 D4 D5 D6 D7 S1_S2 S3_S4 S5_S6 S7_S8 S9_S10 S11_S12 S13_S14
+// CHECK-LABEL: RegisterClass DRegs:
+
+// CHECK-LABEL: SubRegIndex sub0:
+// CHECK-LABEL: SubRegIndex sub1:
+// CHECK-LABEL: SubRegIndex sub2:
+// Check infered indexes:
+// CHECK: SubRegIndex ssub1_ssub2:
+// CHECK: SubRegIndex ssub3_ssub4:
+// CHECK: SubRegIndex ssub0_ssub1_ssub2_ssub3:
+// CHECK: SubRegIndex ssub1_ssub2_ssub3_ssub4:
+
+// Check that all subregs are generated on some examples
+// CHECK-LABEL: Register D0:
+// CHECK: HasDisjunctSubRegs: 1
+// CHECK-NEXT: SubReg ssub0 = S0
+// CHECK-NEXT: SubReg ssub1 = S1
+
+// CHECK-LABEL: Register S9_S10_S11_S12_S13:
+// CHECK: HasDisjunctSubRegs: 1
+// CHECK-NEXT: SubReg ssub0 = S9
+// CHECK-NEXT: SubReg ssub1 = S10
+// CHECK-NEXT: SubReg ssub2 = S11
+// CHECK-NEXT: SubReg ssub3 = S12
+// CHECK-NEXT: SubReg ssub4 = S13
+// CHECK-NEXT: SubReg sub0 = S9_S10
+// CHECK-NEXT: SubReg sub1 = S11_S12
+// CHECK-NEXT: SubReg ssub1_ssub2 = D5
+// CHECK-NEXT: SubReg ssub3_ssub4 = D6
+// CHECK-NEXT: SubReg ssub1_ssub2_ssub3_ssub4 = D5_D6
+
+// CHECK-LABEL: Register S10_S11_S12_S13_S14:
+// CHECK: HasDisjunctSubRegs: 1
+// CHECK-NEXT: SubReg ssub0 = S10
+// CHECK-NEXT: SubReg ssub1 = S11
+// CHECK-NEXT: SubReg ssub2 = S12
+// CHECK-NEXT: SubReg ssub3 = S13
+// CHECK-NEXT: SubReg ssub4 = S14
+// CHECK-NEXT: SubReg sub0 = D5
+// CHECK-NEXT: SubReg sub1 = D6
+// CHECK-NEXT: SubReg ssub1_ssub2 = S11_S12
+// CHECK-NEXT: SubReg ssub3_ssub4 = S13_S14
+// CHECK-NEXT: SubReg ssub0_ssub1_ssub2_ssub3 = D5_D6

external/llvm/test/TableGen/Dag.td

@@ -0,0 +1,85 @@
+// RUN: llvm-tblgen %s | FileCheck %s
+// XFAIL: vg_leak
+
+//===----------------------------------------------------------------------===//
+// Substitution of an int.
+def X1;
+
+class C1<int N> {
+  dag d = (X1 N);
+}
+
+def VAL1 : C1<13>;
+
+// CHECK: def VAL1 {
+// CHECK-NEXT: dag d = (X1 13)
+
+
+//===----------------------------------------------------------------------===//
+// Substitution of a DAG.
+def X2;
+
+class yclass;
+def Y2 : yclass;
+
+class C2<yclass N> {
+  dag d = (X2 N);
+  dag e = (N X2);
+}
+
+def VAL2 : C2<Y2>;
+
+// CHECK: def VAL2 {
+// CHECK-NEXT: dag d = (X2 Y2)
+// CHECK-NEXT: dag e = (Y2 X2)
+
+
+//===----------------------------------------------------------------------===//
+// Complex dag operator (F.TheOp).
+
+class operator;
+def somedef1 : operator;
+def somedef2 : operator;
+
+class foo<operator a> {
+ operator TheOp = a;
+}
+
+class bar<foo F, operator a> {
+  dag Dag1 = (somedef1 1);
+  dag Dag2 = (a 2);
+  dag Dag3 = (F.TheOp 2);
+}
+
+def foo1 : foo<somedef1>;
+def foo2 : foo<somedef2>;
+
+def VAL3 : bar<foo1, somedef1>;
+
+// CHECK:     def VAL3 {	// bar
+// CHECK-NEXT:  dag Dag1 = (somedef1 1);
+// CHECK-NEXT:  dag Dag2 = (somedef1 2);
+// CHECK-NEXT:  dag Dag3 = (somedef1 2);
+// CHECK-NEXT:  NAME = ?
+// CHECK-NEXT: }
+
+
+def VAL4 : bar<foo2, somedef2>;
+// CHECK:      def VAL4 {
+// CHECK-NEXT:  dag Dag1 = (somedef1 1);
+// CHECK-NEXT:  dag Dag2 = (somedef2 2);
+// CHECK-NEXT:  dag Dag3 = (somedef2 2);
+// CHECK-NEXT:  NAME = ?
+// CHECK-NEXT: }
+
+def VAL5 : bar<foo2, somedef2> {
+  // Named operands.
+  let Dag1 = (somedef1 1:$name1);
+
+  // Name, no node.
+  let Dag2 = (somedef2 $name2, $name3);
+}
+
+// CHECK:      def VAL5 {
+// CHECK-NEXT:  dag Dag1 = (somedef1 1:$name1);
+// CHECK-NEXT:  dag Dag2 = (somedef2 ?:$name2, ?:$name3);

external/llvm/test/TableGen/DefmInherit.td

@@ -0,0 +1,39 @@
+// RUN: llvm-tblgen %s | FileCheck %s
+// XFAIL: vg_leak
+
+// CHECK: zing = 4
+// CHECK: zing = 4
+// CHECK: zing = 4
+// CHECK: zing = 4
+// CHECK-NOT: zing = 4
+
+class C1<int A, string B> { 
+  int bar = A;
+  string thestr = B;
+  int zing;
+}
+
+def T : C1<4, "blah">;
+
+multiclass t<int a> {
+  def S1 : C1<a, "foo"> {
+    int foo = 4;
+    let bar = 1;
+  }
+  def S2 : C1<a, "bar">;
+}
+
+multiclass s<int a> {
+  def S3 : C1<a, "moo"> {
+    int moo = 3;
+    let bar = 1;
+  }
+  def S4 : C1<a, "baz">;
+}
+
+defm FOO : t<42>, s<24>;
+
+def T4 : C1<6, "foo">;
+
+let zing = 4 in
+  defm BAZ : t<3>, s<4>;

external/llvm/test/TableGen/DefmInsideMultiClass.td

@@ -0,0 +1,28 @@
+// RUN: llvm-tblgen %s | FileCheck %s
+// XFAIL: vg_leak
+
+// CHECK: ADDPSrr
+// CHECK-NOT: ADDPSrr
+
+class Instruction<bits<4> opc, string Name> {
+  bits<4> opcode = opc;
+  string name = Name;
+}
+
+multiclass basic_r<bits<4> opc> {
+  def rr : Instruction<opc, "rr">;
+  def rm : Instruction<opc, "rm">;
+}
+
+multiclass basic_s<bits<4> opc> {
+  defm SS : basic_r<opc>;
+  defm SD : basic_r<opc>;
+}
+
+multiclass basic_p<bits<4> opc> {
+  defm PS : basic_r<opc>;
+  defm PD : basic_r<opc>;
+}
+
+defm ADD : basic_s<0xf>, basic_p<0xf>;
+defm SUB : basic_s<0xe>, basic_p<0xe>;

external/llvm/test/TableGen/DuplicateFieldValues.td

@@ -0,0 +1,84 @@
+// RUN: llvm-tblgen -gen-instr-info -I %p/../../include %s | FileCheck %s
+
+// CHECK: ABCForm_A
+// CHECK-NOT: ABCForm_A
+
+//
+// include Target.td for InstrMapping class and define minimally required objects
+//
+
+include "llvm/Target/Target.td"
+
+class DFVReg<string n> : Register<n> {
+  let Namespace = "DFV";
+}
+
+def R0 : DFVReg<"r0">;
+def DFVRegClass : RegisterClass<"DFV",[i32],0,(add R0)>;
+def DFVInstrInfo : InstrInfo;
+
+def DFVTest : Target {
+  let InstructionSet = DFVInstrInfo;
+}
+
+//
+// Define a number of a InstrMappings with repeated ValueCol fields
+//
+
+class ABCRel;
+
+def getAFormFromBForm : InstrMapping {
+  let FilterClass = "ABCRel";
+  let RowFields = ["BaseName"];
+  let ColFields = ["ABCForm"];
+  let KeyCol = ["B"];
+  let ValueCols = [["A"]];
+}
+
+def getAFormFromCForm : InstrMapping {
+  let FilterClass = "ABCRel";
+  let RowFields = ["BaseName"];
+  let ColFields = ["ABCForm"];
+  let KeyCol = ["C"];
+  let ValueCols = [["A"]];
+}
+
+def getAFormFromDForm : InstrMapping {
+  let FilterClass = "ABCRel";
+  let RowFields = ["BaseName"];
+  let ColFields = ["ABCForm"];
+  let KeyCol = ["D"];
+  let ValueCols = [["A"]];
+}
+
+def getAFormFromEForm : InstrMapping {
+  let FilterClass = "ABCRel";
+  let RowFields = ["BaseName"];
+  let ColFields = ["ABCForm"];
+  let KeyCol = ["E"];
+  let ValueCols = [["A"]];
+}
+
+class I : Instruction {
+  let Namespace = "DFV";
+  let OutOperandList = (outs);
+  let InOperandList = (ins);
+
+  string BaseName = "";
+  string ABCForm = "";
+}
+
+class isAForm { string ABCForm = "A"; }
+class isBForm { string ABCForm = "B"; }
+class isCForm { string ABCForm = "C"; }
+class isDForm { string ABCForm = "D"; }
+class isEForm { string ABCForm = "E"; }
+
+let BaseName = "0" in {
+  def A0 : I, ABCRel, isAForm;
+  def B0 : I, ABCRel, isBForm;
+  def C0 : I, ABCRel, isCForm;
+  def D0 : I, ABCRel, isDForm;
+  def E0 : I, ABCRel, isEForm;
+}
+

external/llvm/test/TableGen/FieldAccess.td

@@ -0,0 +1,16 @@
+// RUN: llvm-tblgen %s
+// XFAIL: vg_leak
+
+class Bla<string t>
+{
+  string blu = t;
+}
+
+class Bli<Bla t>
+{
+  Bla bla = t;
+}
+
+def a : Bli<Bla<"">>;
+def b : Bla<!cast<Bla>(a.bla).blu>; // works
+def c : Bla<a.bla.blu>; // doesn't work: Cannot access field 'blu' of value 'a.bla'

external/llvm/test/TableGen/ForeachList.td

@@ -0,0 +1,75 @@
+// RUN: llvm-tblgen %s | FileCheck %s
+
+class Register<string name, int idx> {
+  string Name = name;
+  int Index = idx;
+}
+
+foreach i = [0, 1, 2, 3, 4, 5, 6, 7] in {
+  def R#i : Register<"R"#i, i>;
+  def F#i : Register<"F"#i, i>;
+}
+
+// CHECK: def F0
+// CHECK: string Name = "F0";
+// CHECK: int Index = 0;
+
+// CHECK: def F1
+// CHECK: string Name = "F1";
+// CHECK: int Index = 1;
+
+// CHECK: def F2
+// CHECK: string Name = "F2";
+// CHECK: int Index = 2;
+
+// CHECK: def F3
+// CHECK: string Name = "F3";
+// CHECK: int Index = 3;
+
+// CHECK: def F4
+// CHECK: string Name = "F4";
+// CHECK: int Index = 4;
+
+// CHECK: def F5
+// CHECK: string Name = "F5";
+// CHECK: int Index = 5;
+
+// CHECK: def F6
+// CHECK: string Name = "F6";
+// CHECK: int Index = 6;
+
+// CHECK: def F7
+// CHECK: string Name = "F7";
+// CHECK: int Index = 7;
+
+// CHECK: def R0
+// CHECK: string Name = "R0";
+// CHECK: int Index = 0;
+
+// CHECK: def R1
+// CHECK: string Name = "R1";
+// CHECK: int Index = 1;
+
+// CHECK: def R2
+// CHECK: string Name = "R2";
+// CHECK: int Index = 2;
+
+// CHECK: def R3
+// CHECK: string Name = "R3";
+// CHECK: int Index = 3;
+
+// CHECK: def R4
+// CHECK: string Name = "R4";
+// CHECK: int Index = 4;
+
+// CHECK: def R5
+// CHECK: string Name = "R5";
+// CHECK: int Index = 5;
+
+// CHECK: def R6
+// CHECK: string Name = "R6";
+// CHECK: int Index = 6;
+
+// CHECK: def R7
+// CHECK: string Name = "R7";
+// CHECK: int Index = 7;

external/llvm/test/TableGen/ForeachLoop.td

@@ -0,0 +1,86 @@
+// RUN: llvm-tblgen %s | FileCheck %s
+
+class Register<string name, int idx> {
+  string Name = name;
+  int Index = idx;
+}
+
+// CHECK-NOT: !strconcat
+
+foreach i = 0-3 in
+  def Q#i : Register<"Q"#i, i>;
+
+// CHECK: def Q0
+// CHECK: def Q1
+// CHECK: def Q2
+// CHECK: def Q3
+
+foreach i = [0, 1, 2, 3, 4, 5, 6, 7] in
+  def R#i : Register<"R"#i, i>;
+
+// CHECK: def R0
+// CHECK: string Name = "R0";
+// CHECK: int Index = 0;
+
+// CHECK: def R1
+// CHECK: string Name = "R1";
+// CHECK: int Index = 1;
+
+// CHECK: def R2
+// CHECK: string Name = "R2";
+// CHECK: int Index = 2;
+
+// CHECK: def R3
+// CHECK: string Name = "R3";
+// CHECK: int Index = 3;
+
+// CHECK: def R4
+// CHECK: string Name = "R4";
+// CHECK: int Index = 4;
+
+// CHECK: def R5
+// CHECK: string Name = "R5";
+// CHECK: int Index = 5;
+
+// CHECK: def R6
+// CHECK: string Name = "R6";
+// CHECK: int Index = 6;
+
+// CHECK: def R7
+// CHECK: string Name = "R7";
+// CHECK: int Index = 7;
+
+foreach i = {0-3,9-7} in {
+  def S#i : Register<"Q"#i, i>;
+  def : Register<"T"#i, i>;
+}
+
+// CHECK: def S0
+// CHECK: def S1
+// CHECK: def S2
+// CHECK: def S3
+// CHECK: def S7
+// CHECK: def S8
+// CHECK: def S9
+
+// CHECK: def
+// CHECK: string Name = "T0";
+
+// CHECK: def
+// CHECK: string Name = "T1";
+
+// CHECK: def
+// CHECK: string Name = "T2";
+
+// CHECK: def
+// CHECK: string Name = "T3";
+
+// CHECK: def
+// CHECK: string Name = "T9";
+
+// CHECK: def
+// CHECK: string Name = "T8";
+
+// CHECK: def
+// CHECK: string Name = "T7";
+