Imported Upstream version 5.18.0.205

Former-commit-id: 7f59f7e792705db773f1caecdaa823092f4e2927

external/llvm/test/CodeGen/Mips/tailcall/tail-call-arguments-clobber.ll

@@ -0,0 +1,71 @@
+; RUN: llc -march=mips -mcpu=mips32 -O0 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck \
+; RUN:     %s -check-prefix=MIPS32
+; RUN: llc -march=mips64 -mcpu=mips64 -O0 -relocation-model=pic -target-abi n64 \
+; RUN:     -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=MIPS64
+; RUN: llc -march=mips64 -mcpu=mips64 -O0 -relocation-model=pic -target-abi n32 \
+; RUN:     -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=MIPS64
+
+
+; LLVM PR/30197
+; Test that the scheduler does not order loads and stores of arguments that
+; are passed on the stack such that the arguments of the caller are clobbered
+; too early.
+
+; This test is more fragile than I'd like. The -NEXT directives enforce an
+; assumption that any GOT related instructions will not appear between the
+; loads and stores.
+
+; O32 case: The last two arguments should appear at 16(sp), 20(sp). The order
+;           of the loads doesn't matter, but they have to become before the
+;           stores
+define internal i32 @func2(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f) {
+  %1 = add i32 %a, %b
+  %2 = add i32 %1, %c
+  %3 = add i32 %2, %d
+  %4 = add i32 %3, %e
+  %5 = add i32 %4, %f
+  ret i32 %5
+}
+
+define i32 @func1(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f){
+; MIPS32-LABEL: func1:
+
+; MIPS32: lw ${{[0-9]+}}, {{[0-9]+}}($sp)
+; MIPS32-NEXT: lw ${{[0-9]+}}, {{[0-9]+}}($sp)
+; MIPS32-NEXT: sw ${{[0-9]+}}, {{[0-9]+}}($sp)
+; MIPS32-NEXT: sw ${{[0-9]+}}, {{[0-9]+}}($sp)
+  %retval = tail call i32 @func2(i32 %a, i32 %f, i32 %c, i32 %d, i32 %e, i32 %b)
+
+  ret i32 %retval
+}
+
+; N64, N32 cases: N64 and N32 both pass 8 arguments in registers. The order
+;           of the loads doesn't matter, but they have to become before the
+;           stores
+
+define internal i64 @func4(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e,
+                           i64 %f, i64 %g, i64 %h, i64 %i, i64 %j) {
+  %1 = add i64 %a, %b
+  %2 = add i64 %1, %c
+  %3 = add i64 %2, %d
+  %4 = add i64 %3, %e
+  %5 = add i64 %4, %f
+  %6 = add i64 %1, %g
+  %7 = add i64 %2, %h
+  %8 = add i64 %3, %i
+  %9 = add i64 %4, %j
+  ret i64 %5
+}
+define i64 @func3(i64 %a, i64 %b, i64 %c, i64 %d,
+                  i64 %e, i64 %f, i64 %g, i64 %h,
+                  i64 %i, i64 %j){
+; MIPS64-LABEL: func3:
+
+; MIPS64: ld ${{[0-9]+}}, {{[0-9]+}}($sp)
+; MIPS64-NEXT: ld ${{[0-9]+}}, {{[0-9]+}}($sp)
+; MIPS64-NEXT: sd ${{[0-9]+}}, {{[0-9]+}}($sp)
+; MIPS64-NEXT: sd ${{[0-9]+}}, {{[0-9]+}}($sp)
+  %retval = tail call i64 @func4(i64 %a, i64 %j, i64 %c, i64 %d, i64 %e, i64 %f, i64 %g, i64 %h, i64 %i, i64 %b)
+
+  ret i64 %retval
+}

external/llvm/test/CodeGen/Mips/tailcall/tailcall-wrong-isa.ll

@@ -0,0 +1,53 @@
+; RUN: llc -filetype=obj -march=mipsel -relocation-model=pic -verify-machineinstrs -mips-tail-calls=1 < %s -o - \
+; RUN:   | llvm-objdump  -d - | FileCheck %s -check-prefix=PIC32
+
+; RUN: llc -filetype=obj -march=mipsel -relocation-model=static -verify-machineinstrs -mips-tail-calls=1 < %s -o - \
+; RUN:   | llvm-objdump  -d - | FileCheck %s -check-prefix=STATIC32
+
+; RUN: llc -filetype=obj -march=mips64el -relocation-model=pic -mcpu=mips64 -verify-machineinstrs -mips-tail-calls=1 < %s -o - \
+; RUN:   | llvm-objdump  -d - | FileCheck %s -check-prefix=PIC64
+
+; RUN: llc -filetype=obj -march=mips64el -relocation-model=static -mcpu=mips64 -verify-machineinstrs -mips-tail-calls=1 < %s -o - \
+; RUN:   | llvm-objdump  -d - | FileCheck %s -check-prefix=STATIC64
+
+; RUN: llc -filetype=obj -march=mipsel -relocation-model=pic -mattr=+micromips -mips-tail-calls=1 < %s -o - \
+; RUN:   | llvm-objdump  -d - | FileCheck %s -check-prefix=PIC32MM
+
+; RUN: llc -filetype=obj -march=mipsel -relocation-model=static -mattr=+micromips -mips-tail-calls=1 < %s -o - \
+; RUN:   | llvm-objdump  -d - | FileCheck %s -check-prefix=STATIC32MM
+
+; RUN: llc -filetype=obj -march=mipsel -relocation-model=pic -mcpu=mips32r6 -mips-tail-calls=1 < %s -o - \
+; RUN:   | llvm-objdump  -d - | FileCheck %s  -check-prefix=PIC32R6
+; RUN: llc -filetype=obj -march=mipsel -relocation-model=static -mcpu=mips32r6 -mips-tail-calls=1 < %s -o - \
+; RUN:   | llvm-objdump  -d - | FileCheck %s -check-prefix=STATIC32R6
+
+; RUN: llc -filetype=obj -march=mips64el -relocation-model=pic -mcpu=mips64r6 -mips-tail-calls=1 < %s -o - \
+; RUN:   | llvm-objdump  -d - | FileCheck %s -check-prefix=PIC64R6
+; RUN: llc -filetype=obj -march=mips64el -relocation-model=static -mcpu=mips64r6 -mips-tail-calls=1 < %s -o - \
+; RUN:   | llvm-objdump  -d - | FileCheck %s -check-prefix=STATIC64R6
+
+
+define internal i8 @f2(i8) {
+  ret i8 4
+}
+
+define i8 @f1(i8 signext %i) nounwind {
+  %a = tail call i8 @f2(i8 %i)
+  ret i8 %a
+}
+
+; ALL:        f1:
+; PIC32:      {{[0-9a-z]}}: 08 00 20 03  jr $25
+; STATIC32:   {{[0-9a-z]}}: 00 00 00 08  j 0
+
+; PIC64:      {{[0-9a-z]+}}: 08 00 20 03  jr $25
+; STATIC64:   {{[0-9]}}: 00 00 00 08  j 0
+
+; PIC32MM:    {{[0-9a-z]+}}: b9 45 jrc $25
+; STATIC32MM: {{[0-9a-z]}}: 00 d4 00 00 j 0
+
+; PIC32R6:    {{[0-9a-z]}}: 00 00 19 d8  jrc $25
+; STATIC32R6: {{[0-9a-z]}}: 00 00 00 08  j 0
+
+; PIC64R6:    {{[0-9a-z]+}}: 00 00 19 d8  jrc $25
+; STATIC64R6: {{[0-9]}}: 00 00 00 08  j 0

external/llvm/test/CodeGen/Mips/tailcall/tailcall.ll

@@ -0,0 +1,325 @@
+; RUN: llc -march=mipsel -relocation-model=pic  \
+; RUN:     -verify-machineinstrs -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,PIC32
+; RUN: llc -march=mipsel -relocation-model=static  \
+; RUN:     -verify-machineinstrs -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,STATIC32
+; RUN: llc -march=mips64el -mcpu=mips64r2  -relocation-model=pic \
+; RUN:     -verify-machineinstrs -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,PIC64
+; RUN: llc -march=mips64el -mcpu=mips64r2  -relocation-model=static \
+; RUN:     -verify-machineinstrs -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,STATIC64
+; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic \
+; RUN:      -verify-machineinstrs -mips-tail-calls=1 < %s | \
+; RUN:     FileCheck %s -check-prefixes=ALL,PIC16
+
+; RUN: llc -march=mipsel -relocation-model=pic -mattr=+micromips -mips-tail-calls=1 < %s | \
+; RUN:     FileCheck %s -check-prefixes=ALL,PIC32MM
+; RUN: llc -march=mipsel -relocation-model=static -mattr=+micromips \
+; RUN:     -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,STATIC32
+
+; RUN: llc -march=mipsel -relocation-model=pic -mcpu=mips32r6 -mips-tail-calls=1 < %s | \
+; RUN:     FileCheck %s -check-prefixes=ALL,PIC32R6
+; RUN: llc -march=mipsel -relocation-model=static -mcpu=mips32r2 \
+; RUN:     -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,STATIC32
+; RUN: llc -march=mips64el -relocation-model=pic -mcpu=mips64r2  \
+; RUN:     -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=PIC64
+; RUN: llc -march=mips64el -relocation-model=pic -mcpu=mips64r6  \
+; RUN:     -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=STATIC64
+
+; RUN: llc -march=mipsel -relocation-model=pic -mcpu=mips32r6 -mattr=+micromips \
+; RUN:      -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,PIC32MM
+; RUN: llc -march=mipsel -relocation-model=static -mcpu=mips32r6 \
+; RUN:     -mattr=+micromips -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,STATIC32MMR6
+
+@g0 = common global i32 0, align 4
+@g1 = common global i32 0, align 4
+@g2 = common global i32 0, align 4
+@g3 = common global i32 0, align 4
+@g4 = common global i32 0, align 4
+@g5 = common global i32 0, align 4
+@g6 = common global i32 0, align 4
+@g7 = common global i32 0, align 4
+@g8 = common global i32 0, align 4
+@g9 = common global i32 0, align 4
+
+define i32 @caller1(i32 %a0) nounwind {
+entry:
+; ALL-LABEL: caller1:
+; PIC32: jalr $25
+; PIC32MM: jalr $25
+; PIC32R6: jalr $25
+; STATIC32: jal
+; STATIC32MMR6: jal
+; N64: jalr $25
+; N64R6: jalr $25
+; PIC16: jalrc
+
+  %call = tail call i32 @callee1(i32 1, i32 1, i32 1, i32 %a0) nounwind
+  ret i32 %call
+}
+
+declare i32 @callee1(i32, i32, i32, i32)
+
+define i32 @caller2(i32 %a0, i32 %a1, i32 %a2, i32 %a3) nounwind {
+entry:
+; ALL-LABEL: caller2
+; PIC32: jalr $25
+; PIC32MM: jalr $25
+; PIC32R6: jalr $25
+; STATIC32: jal
+; STATIC32MMR6: jal
+; N64: jalr $25
+; N64R6: jalr $25
+; PIC16: jalrc
+
+  %call = tail call i32 @callee2(i32 1, i32 %a0, i32 %a1, i32 %a2, i32 %a3) nounwind
+  ret i32 %call
+}
+
+declare i32 @callee2(i32, i32, i32, i32, i32)
+
+define i32 @caller3(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4) nounwind {
+entry:
+; ALL-LABEL: caller3:
+; PIC32: jalr $25
+; PIC32R6: jalr $25
+; PIC32MM: jalr $25
+; STATIC32: jal
+; STATIC32MMR6: jal
+; N64: jalr $25
+; N64R6: jalr $25
+; PIC16: jalrc
+
+  %call = tail call i32 @callee3(i32 1, i32 1, i32 1, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4) nounwind
+  ret i32 %call
+}
+
+declare i32 @callee3(i32, i32, i32, i32, i32, i32, i32, i32)
+
+define i32 @caller4(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7) nounwind {
+entry:
+; ALL-LABEL: caller4:
+; PIC32: jalr $25
+; PIC32R6: jalr $25
+; PIC32MM: jalr $25
+; STATIC32: jal
+; SATATIC32MMR6: jal
+; PIC64: jalr $25
+; STATIC64: jal
+; N64R6: jalr $25
+; PIC16: jalrc
+
+  %call = tail call i32 @callee4(i32 1, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7) nounwind
+  ret i32 %call
+}
+
+declare i32 @callee4(i32, i32, i32, i32, i32, i32, i32, i32, i32)
+
+define i32 @caller5() nounwind readonly {
+entry:
+; ALL-LABEL: caller5:
+; PIC32: jr $25
+; PIC32R6: jr $25
+; PIC32MM: jr
+; STATIC32: j
+; STATIC32MMR6: bc
+; PIC64: jr $25
+; STATIC64: j
+; PIC16: jalrc
+
+  %0 = load i32, i32* @g0, align 4
+  %1 = load i32, i32* @g1, align 4
+  %2 = load i32, i32* @g2, align 4
+  %3 = load i32, i32* @g3, align 4
+  %4 = load i32, i32* @g4, align 4
+  %5 = load i32, i32* @g5, align 4
+  %6 = load i32, i32* @g6, align 4
+  %7 = load i32, i32* @g7, align 4
+  %8 = load i32, i32* @g8, align 4
+  %9 = load i32, i32* @g9, align 4
+  %call = tail call fastcc i32 @callee5(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7, i32 %8, i32 %9)
+  ret i32 %call
+}
+
+define internal fastcc i32 @callee5(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7, i32 %a8, i32 %a9) nounwind readnone noinline {
+entry:
+  %add = add nsw i32 %a1, %a0
+  %add1 = add nsw i32 %add, %a2
+  %add2 = add nsw i32 %add1, %a3
+  %add3 = add nsw i32 %add2, %a4
+  %add4 = add nsw i32 %add3, %a5
+  %add5 = add nsw i32 %add4, %a6
+  %add6 = add nsw i32 %add5, %a7
+  %add7 = add nsw i32 %add6, %a8
+  %add8 = add nsw i32 %add7, %a9
+  ret i32 %add8
+}
+
+declare i32 @callee8(i32, ...)
+
+define i32 @caller8_0() nounwind {
+entry:
+; ALL-LABEL: caller8_0:
+; PIC32: jr $25
+; PIC32R6: jrc $25
+; PIC32MM: jrc
+; STATIC32: j
+; STATIC32MMR6: bc
+; PIC64: jr $25
+; PIC64R6: jrc $25
+; STATIC64: j
+; PIC16: jalrc
+
+  %call = tail call fastcc i32 @caller8_1()
+  ret i32 %call
+}
+
+define internal fastcc i32 @caller8_1() nounwind noinline {
+entry:
+; ALL-LABEL: caller8_1:
+; PIC32: jalr $25
+; PIC32R6: jalr $25
+; PIC32MM: jalr $25
+; STATIC32: jal
+; STATIC32MMR6: jal
+; PIC64: jalr $25
+; STATIC64: jal
+; PIC16: jalrc
+
+  %call = tail call i32 (i32, ...) @callee8(i32 2, i32 1) nounwind
+  ret i32 %call
+}
+
+%struct.S = type { [2 x i32] }
+
+@gs1 = external global %struct.S
+
+declare i32 @callee9(%struct.S* byval)
+
+define i32 @caller9_0() nounwind {
+entry:
+; ALL-LABEL: caller9_0:
+; PIC32: jr $25
+; PIC32R6: jrc $25
+; PIC32MM: jrc
+; STATIC32: j
+; STATIC32MMR6: bc
+; PIC64: jr $25
+; STATIC64: j
+; PIC64R6: jrc $25
+; PIC16: jalrc
+  %call = tail call fastcc i32 @caller9_1()
+  ret i32 %call
+}
+
+define internal fastcc i32 @caller9_1() nounwind noinline {
+entry:
+; ALL-LABEL: caller9_1:
+; PIC32: jalr $25
+; PIC32R6: jalrc $25
+; PIC32MM: jalr $25
+; STATIC32: jal
+; STATIC32MMR6: jal
+; STATIC64: jal
+; PIC64: jalr $25
+; PIC64R6: jalrc $25
+; PIC16: jalrc
+
+  %call = tail call i32 @callee9(%struct.S* byval @gs1) nounwind
+  ret i32 %call
+}
+
+declare i32 @callee10(i32, i32, i32, i32, i32, i32, i32, i32, i32)
+
+define i32 @caller10(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7, i32 %a8) nounwind {
+entry:
+; ALL-LABEL: caller10:
+; PIC32: jalr $25
+; PIC32R6: jalr $25
+; PIC32MM: jalr $25
+; STATIC32: jal
+; STATIC32MMR6: jal
+; STATIC64: jal
+; PIC64: jalr $25
+; PIC64R6: jalr $25
+; PIC16: jalrc
+
+  %call = tail call i32 @callee10(i32 %a8, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7) nounwind
+  ret i32 %call
+}
+
+declare i32 @callee11(%struct.S* byval)
+
+define i32 @caller11() nounwind noinline {
+entry:
+; ALL-LABEL: caller11:
+; PIC32: jalr $25
+; PIC32R6: jalrc $25
+; PIC32MM: jalr $25
+; STATIC32: jal
+; STATIC32MMR6: jal
+; STATIC64: jal
+; PIC64: jalr $25
+; PIC64R6: jalrc $25
+; PIC16: jalrc
+
+  %call = tail call i32 @callee11(%struct.S* byval @gs1) nounwind
+  ret i32 %call
+}
+
+declare i32 @callee12()
+
+declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind
+
+define i32 @caller12(%struct.S* nocapture byval %a0) nounwind {
+entry:
+; ALL-LABEL: caller12:
+; PIC32: jalr $25
+; PIC32R6: jalrc $25
+; PIC32MM: jalr $25
+; STATIC32: jal
+; STATIC32MMR6: jal
+; STATIC64: jal
+; PIC64: jalr $25
+; PIC64R6: jalrc $25
+; PIC16: jalrc
+
+  %0 = bitcast %struct.S* %a0 to i8*
+  tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* bitcast (%struct.S* @gs1 to i8*), i8* %0, i32 8, i32 4, i1 false)
+  %call = tail call i32 @callee12() nounwind
+  ret i32 %call
+}
+
+declare i32 @callee13(i32, ...)
+
+define i32 @caller13() nounwind {
+entry:
+; ALL-LABEL: caller13:
+; PIC32: jalr $25
+; PIC32R6: jalr $25
+; PIC32MM: jalr $25
+; STATIC32: jal
+; STATIC32MMR6: jal
+; STATIC64: jal
+; PIC64R6: jalr $25
+; PIC64: jalr $25
+; PIC16: jalrc
+
+  %call = tail call i32 (i32, ...) @callee13(i32 1, i32 2) nounwind
+  ret i32 %call
+}
+
+; Check that there is a chain edge between the load and store nodes.
+;
+; ALL-LABEL: caller14:
+; PIC32: lw ${{[0-9]+}}, 48($sp)
+; PIC32: sw $4, 16($sp)
+
+; PIC32MM: lw ${{[0-9]+}}, 48($sp)
+; PIC32MM: sw16 $4, 16(${{[0-9]+}})
+
+define void @caller14(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+entry:
+  tail call void @callee14(i32 %e, i32 %b, i32 %c, i32 %d, i32 %a)
+  ret void
+}
+
+declare void @callee14(i32, i32, i32, i32, i32)