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Imported Upstream version 5.18.0.205
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external/llvm/test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll
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179
external/llvm/test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll
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; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
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; RUN: < %s | FileCheck %s
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; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
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; RUN: < %s | FileCheck %s
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; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
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; RUN: < %s | FileCheck %s -check-prefix=mips32r2
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; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
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; RUN: < %s | FileCheck %s -check-prefix=mips32
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@b2 = global i8 0, align 1
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@b1 = global i8 1, align 1
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@uc1 = global i8 0, align 1
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@uc2 = global i8 -1, align 1
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@sc1 = global i8 -128, align 1
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@sc2 = global i8 127, align 1
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@ss1 = global i16 -32768, align 2
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@ss2 = global i16 32767, align 2
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@us1 = global i16 0, align 2
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@us2 = global i16 -1, align 2
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@ssi = global i16 0, align 2
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@ssj = global i16 0, align 2
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@i = global i32 0, align 4
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@j = global i32 0, align 4
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@.str = private unnamed_addr constant [4 x i8] c"%i\0A\00", align 1
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@.str1 = private unnamed_addr constant [7 x i8] c"%i %i\0A\00", align 1
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; Function Attrs: nounwind
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define void @_Z3b_iv() {
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entry:
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; CHECK-LABEL: .ent _Z3b_iv
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%0 = load i8, i8* @b1, align 1
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%tobool = trunc i8 %0 to i1
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%frombool = zext i1 %tobool to i8
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store i8 %frombool, i8* @b2, align 1
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%1 = load i8, i8* @b2, align 1
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%tobool1 = trunc i8 %1 to i1
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%conv = zext i1 %tobool1 to i32
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store i32 %conv, i32* @i, align 4
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; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
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; CHECK: andi $[[REG2:[0-9]+]], $[[REG1]], 1
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; CHECK: sb $[[REG2]], 0(${{[0-9]+}})
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ret void
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; CHECK: .end _Z3b_iv
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}
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; Function Attrs: nounwind
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define void @_Z4uc_iv() {
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entry:
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; CHECK-LABEL: .ent _Z4uc_iv
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%0 = load i8, i8* @uc1, align 1
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%conv = zext i8 %0 to i32
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store i32 %conv, i32* @i, align 4
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%1 = load i8, i8* @uc2, align 1
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%conv1 = zext i8 %1 to i32
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; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
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; CHECK: andi ${{[0-9]+}}, $[[REG1]], 255
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store i32 %conv1, i32* @j, align 4
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ret void
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; CHECK: .end _Z4uc_iv
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}
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; Function Attrs: nounwind
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define void @_Z4sc_iv() {
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entry:
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; mips32r2-LABEL: .ent _Z4sc_iv
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; mips32-LABEL: .ent _Z4sc_iv
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%0 = load i8, i8* @sc1, align 1
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%conv = sext i8 %0 to i32
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store i32 %conv, i32* @i, align 4
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%1 = load i8, i8* @sc2, align 1
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%conv1 = sext i8 %1 to i32
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store i32 %conv1, i32* @j, align 4
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; mips32r2: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
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; mips32r2: seb ${{[0-9]+}}, $[[REG1]]
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; mips32: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
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; mips32: sll $[[REG2:[0-9]+]], $[[REG1]], 24
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; mips32: sra ${{[0-9]+}}, $[[REG2]], 24
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ret void
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; CHECK: .end _Z4sc_iv
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}
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; Function Attrs: nounwind
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define void @_Z4us_iv() {
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entry:
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; CHECK-LABEL: .ent _Z4us_iv
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%0 = load i16, i16* @us1, align 2
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%conv = zext i16 %0 to i32
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store i32 %conv, i32* @i, align 4
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%1 = load i16, i16* @us2, align 2
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%conv1 = zext i16 %1 to i32
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store i32 %conv1, i32* @j, align 4
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ret void
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; CHECK: lhu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
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; CHECK: andi ${{[0-9]+}}, $[[REG1]], 65535
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; CHECK: .end _Z4us_iv
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}
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; Function Attrs: nounwind
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define void @_Z4ss_iv() {
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entry:
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; mips32r2-LABEL: .ent _Z4ss_iv
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; mips32=LABEL: .ent _Z4ss_iv
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%0 = load i16, i16* @ss1, align 2
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%conv = sext i16 %0 to i32
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store i32 %conv, i32* @i, align 4
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%1 = load i16, i16* @ss2, align 2
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%conv1 = sext i16 %1 to i32
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store i32 %conv1, i32* @j, align 4
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; mips32r2: lhu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
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; mips32r2: seh ${{[0-9]+}}, $[[REG1]]
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; mips32: lhu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
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; mips32: sll $[[REG2:[0-9]+]], $[[REG1]], 16
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; mips32: sra ${{[0-9]+}}, $[[REG2]], 16
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ret void
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; CHECK: .end _Z4ss_iv
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}
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; Function Attrs: nounwind
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define void @_Z4b_ssv() {
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entry:
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; CHECK-LABEL: .ent _Z4b_ssv
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%0 = load i8, i8* @b2, align 1
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%tobool = trunc i8 %0 to i1
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%conv = zext i1 %tobool to i16
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store i16 %conv, i16* @ssi, align 2
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ret void
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; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
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; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1
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; CHECK: .end _Z4b_ssv
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}
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; Function Attrs: nounwind
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define void @_Z5uc_ssv() {
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entry:
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; CHECK-LABEL: .ent _Z5uc_ssv
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%0 = load i8, i8* @uc1, align 1
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%conv = zext i8 %0 to i16
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store i16 %conv, i16* @ssi, align 2
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%1 = load i8, i8* @uc2, align 1
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%conv1 = zext i8 %1 to i16
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; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
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; CHECK: andi ${{[0-9]+}}, $[[REG1]], 255
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store i16 %conv1, i16* @ssj, align 2
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ret void
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; CHECK: .end _Z5uc_ssv
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}
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; Function Attrs: nounwind
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define void @_Z5sc_ssv() {
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entry:
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; mips32r2-LABEL: .ent _Z5sc_ssv
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; mips32-LABEL: .ent _Z5sc_ssv
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%0 = load i8, i8* @sc1, align 1
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%conv = sext i8 %0 to i16
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store i16 %conv, i16* @ssi, align 2
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%1 = load i8, i8* @sc2, align 1
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%conv1 = sext i8 %1 to i16
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store i16 %conv1, i16* @ssj, align 2
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; mips32r2: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
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; mips32r2: seb ${{[0-9]+}}, $[[REG1]]
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; mips32: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
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; mips32: sll $[[REG2:[0-9]+]], $[[REG1]], 24
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; mips32: sra ${{[0-9]+}}, $[[REG2]], 24
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ret void
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; CHECK: .end _Z5sc_ssv
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}
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