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Imported Upstream version 5.18.0.205
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external/llvm/test/CodeGen/Hexagon/autohvx/isel-vec-ext.ll
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external/llvm/test/CodeGen/Hexagon/autohvx/isel-vec-ext.ll
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; RUN: llc -march=hexagon < %s | FileCheck %s
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target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
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target triple = "hexagon"
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; CHECK-LABEL: danny:
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; CHECK: vsxt
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; CHECK-NOT: vinsert
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define void @danny() local_unnamed_addr #0 {
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b2:
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%v16 = select <16 x i1> undef, <16 x i16> undef, <16 x i16> zeroinitializer
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%v17 = sext <16 x i16> %v16 to <16 x i32>
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store <16 x i32> %v17, <16 x i32>* undef, align 128
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unreachable
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}
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; CHECK-LABEL: sammy:
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; CHECK: vsxt
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; CHECK-NOT: vinsert
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define void @sammy() local_unnamed_addr #1 {
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b2:
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%v16 = select <32 x i1> undef, <32 x i16> undef, <32 x i16> zeroinitializer
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%v17 = sext <32 x i16> %v16 to <32 x i32>
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store <32 x i32> %v17, <32 x i32>* undef, align 128
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unreachable
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}
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attributes #0 = { noinline norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-length64b,+hvxv60" }
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attributes #1 = { noinline norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-length128b,+hvxv60" }
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