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Imported Upstream version 5.18.0.205
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18
external/llvm/test/CodeGen/Hexagon/absimm.ll
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18
external/llvm/test/CodeGen/Hexagon/absimm.ll
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; Check that we generate absolute addressing mode instructions
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; with immediate value.
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define i32 @f1(i32 %i) nounwind {
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; CHECK: memw(##786432){{ *}}={{ *}}r{{[0-9]+}}
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entry:
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store volatile i32 %i, i32* inttoptr (i32 786432 to i32*), align 262144
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ret i32 %i
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}
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define i32* @f2(i32* nocapture %i) nounwind {
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entry:
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(##786432)
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%0 = load volatile i32, i32* inttoptr (i32 786432 to i32*), align 262144
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%1 = inttoptr i32 %0 to i32*
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ret i32* %1
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}
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