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Imported Upstream version 5.18.0.205

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Former-commit-id: 7f59f7e792705db773f1caecdaa823092f4e2927
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Xamarin Public Jenkins (auto-signing)
2018-11-16 08:20:38 +00:00
parent 5cd5df71cc
commit 8e12397d70
28486 changed files with 3867013 additions and 66 deletions
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26
external/llvm/test/CodeGen/ARM/cortex-a57-misched-vsub.ll vendored Normal file
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; REQUIRES: asserts
; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -misched-postra -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
; CHECK-LABEL: subv_i32:%bb.0
; CHECK: SU(8): {{.*}} VSUBv4i32
; CHECK-NEXT: # preds left
; CHECK-NEXT: # succs left
; CHECK-NEXT: # rdefs left
; CHECK-NEXT: Latency : 3
define <4 x i32> @subv_i32(<4 x i32>, <4 x i32>) {
%3 = sub <4 x i32> %1, %0
ret <4 x i32> %3
}
; CHECK-LABEL: subv_f32:%bb.0
; CHECK: SU(8): {{.*}} VSUBfq
; CHECK-NEXT: # preds left
; CHECK-NEXT: # succs left
; CHECK-NEXT: # rdefs left
; CHECK-NEXT: Latency : 5
define <4 x float> @subv_f32(<4 x float>, <4 x float>) {
%3 = fsub <4 x float> %0, %1
ret <4 x float> %3
}