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Imported Upstream version 5.18.0.205
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external/llvm/test/CodeGen/AMDGPU/tti-unroll-prefs.ll
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external/llvm/test/CodeGen/AMDGPU/tti-unroll-prefs.ll
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; RUN: opt -loop-unroll -S -mtriple=amdgcn-- -mcpu=tahiti %s | FileCheck %s
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; This IR comes from this OpenCL C code:
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;
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; if (b + 4 > a) {
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; for (int i = 0; i < 4; i++, b++) {
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; if (b + 1 <= a)
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; *(dst + c + b) = 0;
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; else
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; break;
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; }
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; }
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;
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; This test is meant to check that this loop isn't unrolled into more than
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; four iterations. The loop unrolling preferences we currently use cause this
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; loop to not be unrolled at all, but that may change in the future.
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; CHECK-LABEL: @test
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; CHECK: store i8 0, i8 addrspace(1)*
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; CHECK-NOT: store i8 0, i8 addrspace(1)*
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; CHECK: ret void
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define amdgpu_kernel void @test(i8 addrspace(1)* nocapture %dst, i32 %a, i32 %b, i32 %c) {
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entry:
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%add = add nsw i32 %b, 4
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%cmp = icmp sgt i32 %add, %a
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br i1 %cmp, label %for.cond.preheader, label %if.end7
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for.cond.preheader: ; preds = %entry
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%cmp313 = icmp slt i32 %b, %a
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br i1 %cmp313, label %if.then4.lr.ph, label %if.end7.loopexit
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if.then4.lr.ph: ; preds = %for.cond.preheader
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%0 = sext i32 %c to i64
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br label %if.then4
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if.then4: ; preds = %if.then4.lr.ph, %if.then4
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%i.015 = phi i32 [ 0, %if.then4.lr.ph ], [ %inc, %if.then4 ]
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%b.addr.014 = phi i32 [ %b, %if.then4.lr.ph ], [ %add2, %if.then4 ]
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%add2 = add nsw i32 %b.addr.014, 1
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%1 = sext i32 %b.addr.014 to i64
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%add.ptr.sum = add nsw i64 %1, %0
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%add.ptr5 = getelementptr inbounds i8, i8 addrspace(1)* %dst, i64 %add.ptr.sum
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store i8 0, i8 addrspace(1)* %add.ptr5, align 1
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%inc = add nsw i32 %i.015, 1
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%cmp1 = icmp slt i32 %inc, 4
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%cmp3 = icmp slt i32 %add2, %a
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%or.cond = and i1 %cmp3, %cmp1
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br i1 %or.cond, label %if.then4, label %for.cond.if.end7.loopexit_crit_edge
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for.cond.if.end7.loopexit_crit_edge: ; preds = %if.then4
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br label %if.end7.loopexit
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if.end7.loopexit: ; preds = %for.cond.if.end7.loopexit_crit_edge, %for.cond.preheader
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br label %if.end7
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if.end7: ; preds = %if.end7.loopexit, %entry
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ret void
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}
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