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Imported Upstream version 5.18.0.179
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external/llvm/test/CodeGen/SystemZ/extract-vector-elt-zEC12.ll
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external/llvm/test/CodeGen/SystemZ/extract-vector-elt-zEC12.ll
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 | FileCheck %s
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;
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; Test that <1 x i8> is legalized properly without vector support.
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define void @autogen_SD18500(i8*) {
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; CHECK: .text
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BB:
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%L5 = load i8, i8* %0
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%I22 = insertelement <1 x i8> undef, i8 %L5, i32 0
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%Cmp53 = icmp ule i1 undef, undef
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br label %CF244
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CF244: ; preds = %CF244, %BB
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%Sl119 = select i1 %Cmp53, <1 x i8> %I22, <1 x i8> undef
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%Cmp148 = fcmp une float 0x3E03A81780000000, 0x42D92DCD00000000
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br i1 %Cmp148, label %CF244, label %CF241
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CF241: ; preds = %CF241, %CF244
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%Sl199 = select i1 true, <1 x i8> %Sl119, <1 x i8> zeroinitializer
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br label %CF241
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}
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