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Imported Upstream version 5.18.0.179
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external/llvm/test/Bitcode/arm32_neon_vcnt_upgrade.ll
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external/llvm/test/Bitcode/arm32_neon_vcnt_upgrade.ll
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; RUN: llvm-as < %s | llvm-dis | FileCheck %s
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; RUN: verify-uselistorder < %s
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; Tests vclz and vcnt
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define <4 x i16> @vclz16(<4 x i16>* %A) nounwind {
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;CHECK: @vclz16
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%tmp1 = load <4 x i16>, <4 x i16>* %A
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%tmp2 = call <4 x i16> @llvm.arm.neon.vclz.v4i16(<4 x i16> %tmp1)
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;CHECK: {{call.*@llvm.ctlz.v4i16\(<4 x i16>.*, i1 false}}
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ret <4 x i16> %tmp2
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}
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define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind {
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;CHECK: @vcnt8
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp2 = call <8 x i8> @llvm.arm.neon.vcnt.v8i8(<8 x i8> %tmp1)
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;CHECK: call <8 x i8> @llvm.ctpop.v8i8(<8 x i8>
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ret <8 x i8> %tmp2
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}
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declare <4 x i16> @llvm.arm.neon.vclz.v4i16(<4 x i16>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vcnt.v8i8(<8 x i8>) nounwind readnone
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