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Imported Upstream version 6.0.0.172

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Former-commit-id: f3cc9b82f3e5bd8f0fd3ebc098f789556b44e9cd
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Xamarin Public Jenkins (auto-signing)
2019-04-12 14:10:50 +00:00
parent 8016999e4d
commit 64ac736ec5
32155 changed files with 3981439 additions and 75368 deletions
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18
external/llvm/test/MC/Disassembler/AArch64/ldp-preind.predictable.txt vendored Normal file
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# RUN: llvm-mc -triple=aarch64 -mattr=+fp-armv8 -disassemble < %s 2>&1 | FileCheck %s
# RUN: llvm-mc -triple=arm64 -mattr=+fp-armv8 -disassemble < %s 2>&1 | FileCheck %s
# None of these instructions should be classified as unpredictable:
# CHECK-NOT: potentially undefined instruction encoding
# Stores from duplicated registers should be fine.
0xe3 0x0f 0x80 0xa9
# CHECK: stp x3, x3, [sp, #0]!
# d5 != x5 so "ldp d5, d6, [x5, #24]!" is fine.
0xa5 0x98 0xc1 0x6d
# CHECK: ldp d5, d6, [x5, #24]!
# xzr != sp so "stp xzr, xzr, [sp, #8]!" is fine.
0xff 0xff 0x80 0xa9
# CHECK: stp xzr, xzr, [sp, #8]!