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Imported Upstream version 6.0.0.172
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external/llvm/test/CodeGen/X86/sse4a-schedule.ll
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125
external/llvm/test/CodeGen/X86/sse4a-schedule.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=x86-64 -mattr=+sse4a | FileCheck %s --check-prefix=GENERIC
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=btver2 | FileCheck %s --check-prefix=BTVER2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=znver1 | FileCheck %s --check-prefix=ZNVER1
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define <2 x i64> @test_extrq(<2 x i64> %a0, <16 x i8> %a1) {
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; GENERIC-LABEL: test_extrq:
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; GENERIC: # %bb.0:
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; GENERIC-NEXT: extrq %xmm1, %xmm0 # sched: [3:1.00]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; BTVER2-LABEL: test_extrq:
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; BTVER2: # %bb.0:
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; BTVER2-NEXT: extrq %xmm1, %xmm0 # sched: [1:0.50]
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; BTVER2-NEXT: retq # sched: [4:1.00]
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;
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; ZNVER1-LABEL: test_extrq:
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; ZNVER1: # %bb.0:
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; ZNVER1-NEXT: extrq %xmm1, %xmm0 # sched: [2:1.00]
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; ZNVER1-NEXT: retq # sched: [1:0.50]
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%1 = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> %a0, <16 x i8> %a1)
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ret <2 x i64> %1
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}
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declare <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64>, <16 x i8>)
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define <2 x i64> @test_extrqi(<2 x i64> %a0) {
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; GENERIC-LABEL: test_extrqi:
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; GENERIC: # %bb.0:
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; GENERIC-NEXT: extrq $2, $3, %xmm0 # sched: [3:1.00]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; BTVER2-LABEL: test_extrqi:
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; BTVER2: # %bb.0:
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; BTVER2-NEXT: extrq $2, $3, %xmm0 # sched: [1:0.50]
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; BTVER2-NEXT: retq # sched: [4:1.00]
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;
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; ZNVER1-LABEL: test_extrqi:
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; ZNVER1: # %bb.0:
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; ZNVER1-NEXT: extrq $2, $3, %xmm0 # sched: [2:1.00]
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; ZNVER1-NEXT: retq # sched: [1:0.50]
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%1 = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> %a0, i8 3, i8 2)
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ret <2 x i64> %1
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}
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declare <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64>, i8, i8)
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define <2 x i64> @test_insertq(<2 x i64> %a0, <2 x i64> %a1) {
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; GENERIC-LABEL: test_insertq:
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; GENERIC: # %bb.0:
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; GENERIC-NEXT: insertq %xmm1, %xmm0 # sched: [3:1.00]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; BTVER2-LABEL: test_insertq:
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; BTVER2: # %bb.0:
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; BTVER2-NEXT: insertq %xmm1, %xmm0 # sched: [2:2.00]
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; BTVER2-NEXT: retq # sched: [4:1.00]
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;
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; ZNVER1-LABEL: test_insertq:
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; ZNVER1: # %bb.0:
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; ZNVER1-NEXT: insertq %xmm1, %xmm0 # sched: [4:1.00]
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; ZNVER1-NEXT: retq # sched: [1:0.50]
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%1 = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> %a0, <2 x i64> %a1)
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ret <2 x i64> %1
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}
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declare <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64>, <2 x i64>)
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define <2 x i64> @test_insertqi(<2 x i64> %a0, <2 x i64> %a1) {
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; GENERIC-LABEL: test_insertqi:
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; GENERIC: # %bb.0:
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; GENERIC-NEXT: insertq $6, $5, %xmm1, %xmm0 # sched: [3:1.00]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; BTVER2-LABEL: test_insertqi:
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; BTVER2: # %bb.0:
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; BTVER2-NEXT: insertq $6, $5, %xmm1, %xmm0 # sched: [2:2.00]
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; BTVER2-NEXT: retq # sched: [4:1.00]
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;
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; ZNVER1-LABEL: test_insertqi:
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; ZNVER1: # %bb.0:
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; ZNVER1-NEXT: insertq $6, $5, %xmm1, %xmm0 # sched: [4:1.00]
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; ZNVER1-NEXT: retq # sched: [1:0.50]
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%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %a0, <2 x i64> %a1, i8 5, i8 6)
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ret <2 x i64> %1
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}
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declare <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64>, <2 x i64>, i8, i8)
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define void @test_movntsd(i8* %p, <2 x double> %a) {
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; GENERIC-LABEL: test_movntsd:
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; GENERIC: # %bb.0:
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; GENERIC-NEXT: movntsd %xmm0, (%rdi) # sched: [1:1.00]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; BTVER2-LABEL: test_movntsd:
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; BTVER2: # %bb.0:
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; BTVER2-NEXT: movntsd %xmm0, (%rdi) # sched: [1:1.00]
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; BTVER2-NEXT: retq # sched: [4:1.00]
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;
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; ZNVER1-LABEL: test_movntsd:
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; ZNVER1: # %bb.0:
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; ZNVER1-NEXT: movntsd %xmm0, (%rdi) # sched: [8:1.00]
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; ZNVER1-NEXT: retq # sched: [1:0.50]
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tail call void @llvm.x86.sse4a.movnt.sd(i8* %p, <2 x double> %a)
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ret void
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}
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declare void @llvm.x86.sse4a.movnt.sd(i8*, <2 x double>)
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define void @test_movntss(i8* %p, <4 x float> %a) {
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; GENERIC-LABEL: test_movntss:
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; GENERIC: # %bb.0:
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; GENERIC-NEXT: movntss %xmm0, (%rdi) # sched: [1:1.00]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; BTVER2-LABEL: test_movntss:
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; BTVER2: # %bb.0:
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; BTVER2-NEXT: movntss %xmm0, (%rdi) # sched: [1:1.00]
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; BTVER2-NEXT: retq # sched: [4:1.00]
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;
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; ZNVER1-LABEL: test_movntss:
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; ZNVER1: # %bb.0:
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; ZNVER1-NEXT: movntss %xmm0, (%rdi) # sched: [8:1.00]
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; ZNVER1-NEXT: retq # sched: [1:0.50]
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tail call void @llvm.x86.sse4a.movnt.ss(i8* %p, <4 x float> %a)
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ret void
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}
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declare void @llvm.x86.sse4a.movnt.ss(i8*, <4 x float>)
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