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Imported Upstream version 6.0.0.172

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Former-commit-id: f3cc9b82f3e5bd8f0fd3ebc098f789556b44e9cd
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Xamarin Public Jenkins (auto-signing)
2019-04-12 14:10:50 +00:00
parent 8016999e4d
commit 64ac736ec5
32155 changed files with 3981439 additions and 75368 deletions
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20
external/llvm/test/CodeGen/ARM/2006-11-10-CycleInDAG.ll vendored Normal file
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@@ -0,0 +1,20 @@
; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o /dev/null
%struct.layer_data = type { i32, [2048 x i8], i8*, [16 x i8], i32, i8*, i32, i32, [64 x i32], [64 x i32], [64 x i32], [64 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [12 x [64 x i16]] }
@ld = external global %struct.layer_data* ; <%struct.layer_data**> [#uses=1]
define void @main() {
entry:
br i1 false, label %bb169.i, label %cond_true11
bb169.i: ; preds = %entry
ret void
cond_true11: ; preds = %entry
%tmp.i32 = load %struct.layer_data*, %struct.layer_data** @ld ; <%struct.layer_data*> [#uses=2]
%tmp3.i35 = getelementptr %struct.layer_data, %struct.layer_data* %tmp.i32, i32 0, i32 1, i32 2048; <i8*> [#uses=2]
%tmp.i36 = getelementptr %struct.layer_data, %struct.layer_data* %tmp.i32, i32 0, i32 2 ; <i8**> [#uses=1]
store i8* %tmp3.i35, i8** %tmp.i36
store i8* %tmp3.i35, i8** null
ret void
}

112
external/llvm/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll vendored Normal file
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@@ -0,0 +1,112 @@
; RUN: llc < %s -mtriple=arm-apple-ios -mattr=+v6,+vfp2 | FileCheck %s
; RUN: llc < %s -mtriple=arm-apple-ios -mattr=+v6,+vfp2 | FileCheck --check-prefix=DOMAIN %s
; The execution domain checking code would translate vmovs to vorr whether or not
; we had NEON instructions. Verify we don't if we're not compiled with NEON.
; DOMAIN-NOT: vorr
@quant_coef = external global [6 x [4 x [4 x i32]]] ; <[6 x [4 x [4 x i32]]]*> [#uses=1]
@dequant_coef = external global [6 x [4 x [4 x i32]]] ; <[6 x [4 x [4 x i32]]]*> [#uses=1]
@A = external global [4 x [4 x i32]] ; <[4 x [4 x i32]]*> [#uses=1]
; CHECK-LABEL: dct_luma_sp:
define fastcc i32 @dct_luma_sp(i32 %block_x, i32 %block_y, i32* %coeff_cost) "no-frame-pointer-elim"="true" {
entry:
; Make sure to use base-updating stores for saving callee-saved registers.
; CHECK: push
; CHECK-NOT: sub sp
; CHECK: push
%predicted_block = alloca [4 x [4 x i32]], align 4 ; <[4 x [4 x i32]]*> [#uses=1]
br label %cond_next489
cond_next489: ; preds = %cond_false, %bb471
%j.7.in = load i8, i8* null ; <i8> [#uses=1]
%i.8.in = load i8, i8* null ; <i8> [#uses=1]
%i.8 = zext i8 %i.8.in to i32 ; <i32> [#uses=4]
%j.7 = zext i8 %j.7.in to i32 ; <i32> [#uses=4]
%tmp495 = getelementptr [4 x [4 x i32]], [4 x [4 x i32]]* %predicted_block, i32 0, i32 %i.8, i32 %j.7 ; <i32*> [#uses=2]
%tmp496 = load i32, i32* %tmp495 ; <i32> [#uses=2]
%tmp502 = load i32, i32* null ; <i32> [#uses=1]
%tmp542 = getelementptr [6 x [4 x [4 x i32]]], [6 x [4 x [4 x i32]]]* @quant_coef, i32 0, i32 0, i32 %i.8, i32 %j.7 ; <i32*> [#uses=1]
%tmp543 = load i32, i32* %tmp542 ; <i32> [#uses=1]
%tmp548 = ashr i32 0, 0 ; <i32> [#uses=3]
%tmp561 = sub i32 0, %tmp496 ; <i32> [#uses=3]
%abscond563 = icmp sgt i32 %tmp561, -1 ; <i1> [#uses=1]
%abs564 = select i1 %abscond563, i32 %tmp561, i32 0 ; <i32> [#uses=1]
%tmp572 = mul i32 %abs564, %tmp543 ; <i32> [#uses=1]
%tmp574 = add i32 %tmp572, 0 ; <i32> [#uses=1]
%tmp576 = ashr i32 %tmp574, 0 ; <i32> [#uses=7]
%tmp579 = icmp eq i32 %tmp548, %tmp576 ; <i1> [#uses=1]
br i1 %tmp579, label %bb712, label %cond_next589
cond_next589: ; preds = %cond_next489
%tmp605 = getelementptr [6 x [4 x [4 x i32]]], [6 x [4 x [4 x i32]]]* @dequant_coef, i32 0, i32 0, i32 %i.8, i32 %j.7 ; <i32*> [#uses=1]
%tmp606 = load i32, i32* %tmp605 ; <i32> [#uses=1]
%tmp612 = load i32, i32* null ; <i32> [#uses=1]
%tmp629 = load i32, i32* null ; <i32> [#uses=1]
%tmp629a = sitofp i32 %tmp629 to double ; <double> [#uses=1]
%tmp631 = fmul double %tmp629a, 0.000000e+00 ; <double> [#uses=1]
%tmp632 = fadd double 0.000000e+00, %tmp631 ; <double> [#uses=1]
%tmp642 = call fastcc i32 @sign( i32 %tmp576, i32 %tmp561 ) ; <i32> [#uses=1]
%tmp650 = mul i32 %tmp606, %tmp642 ; <i32> [#uses=1]
%tmp656 = mul i32 %tmp650, %tmp612 ; <i32> [#uses=1]
%tmp658 = shl i32 %tmp656, 0 ; <i32> [#uses=1]
%tmp659 = ashr i32 %tmp658, 6 ; <i32> [#uses=1]
%tmp660 = sub i32 0, %tmp659 ; <i32> [#uses=1]
%tmp666 = sub i32 %tmp660, %tmp496 ; <i32> [#uses=1]
%tmp667 = sitofp i32 %tmp666 to double ; <double> [#uses=2]
call void @levrun_linfo_inter( i32 %tmp576, i32 0, i32* null, i32* null )
%tmp671 = fmul double %tmp667, %tmp667 ; <double> [#uses=1]
%tmp675 = fadd double %tmp671, 0.000000e+00 ; <double> [#uses=1]
%tmp678 = fcmp oeq double %tmp632, %tmp675 ; <i1> [#uses=1]
br i1 %tmp678, label %cond_true679, label %cond_false693
cond_true679: ; preds = %cond_next589
%abscond681 = icmp sgt i32 %tmp548, -1 ; <i1> [#uses=1]
%abs682 = select i1 %abscond681, i32 %tmp548, i32 0 ; <i32> [#uses=1]
%abscond684 = icmp sgt i32 %tmp576, -1 ; <i1> [#uses=1]
%abs685 = select i1 %abscond684, i32 %tmp576, i32 0 ; <i32> [#uses=1]
%tmp686 = icmp slt i32 %abs682, %abs685 ; <i1> [#uses=1]
br i1 %tmp686, label %cond_next702, label %cond_false689
cond_false689: ; preds = %cond_true679
%tmp739 = icmp eq i32 %tmp576, 0 ; <i1> [#uses=1]
br i1 %tmp579, label %bb737, label %cond_false708
cond_false693: ; preds = %cond_next589
ret i32 0
cond_next702: ; preds = %cond_true679
ret i32 0
cond_false708: ; preds = %cond_false689
ret i32 0
bb712: ; preds = %cond_next489
ret i32 0
bb737: ; preds = %cond_false689
br i1 %tmp739, label %cond_next791, label %cond_true740
cond_true740: ; preds = %bb737
%tmp761 = call fastcc i32 @sign( i32 %tmp576, i32 0 ) ; <i32> [#uses=1]
%tmp780 = load i32, i32* null ; <i32> [#uses=1]
%tmp785 = getelementptr [4 x [4 x i32]], [4 x [4 x i32]]* @A, i32 0, i32 %i.8, i32 %j.7 ; <i32*> [#uses=1]
%tmp786 = load i32, i32* %tmp785 ; <i32> [#uses=1]
%tmp781 = mul i32 %tmp780, %tmp761 ; <i32> [#uses=1]
%tmp787 = mul i32 %tmp781, %tmp786 ; <i32> [#uses=1]
%tmp789 = shl i32 %tmp787, 0 ; <i32> [#uses=1]
%tmp790 = ashr i32 %tmp789, 6 ; <i32> [#uses=1]
br label %cond_next791
cond_next791: ; preds = %cond_true740, %bb737
%ilev.1 = phi i32 [ %tmp790, %cond_true740 ], [ 0, %bb737 ] ; <i32> [#uses=1]
%tmp796 = load i32, i32* %tmp495 ; <i32> [#uses=1]
%tmp798 = add i32 %tmp796, %ilev.1 ; <i32> [#uses=1]
%tmp812 = mul i32 0, %tmp502 ; <i32> [#uses=0]
%tmp818 = call fastcc i32 @sign( i32 0, i32 %tmp798 ) ; <i32> [#uses=0]
unreachable
}
declare i32 @sign(i32, i32)
declare void @levrun_linfo_inter(i32, i32, i32*, i32*)

21
external/llvm/test/CodeGen/ARM/2007-03-07-CombinerCrash.ll vendored Normal file
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; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6,+vfp2
define fastcc i8* @read_sleb128(i8* %p, i32* %val) {
br label %bb
bb: ; preds = %bb, %0
%p_addr.0 = getelementptr i8, i8* %p, i32 0 ; <i8*> [#uses=1]
%tmp2 = load i8, i8* %p_addr.0 ; <i8> [#uses=2]
%tmp4.rec = add i32 0, 1 ; <i32> [#uses=1]
%tmp4 = getelementptr i8, i8* %p, i32 %tmp4.rec ; <i8*> [#uses=1]
%tmp56 = zext i8 %tmp2 to i32 ; <i32> [#uses=1]
%tmp7 = and i32 %tmp56, 127 ; <i32> [#uses=1]
%tmp9 = shl i32 %tmp7, 0 ; <i32> [#uses=1]
%tmp11 = or i32 %tmp9, 0 ; <i32> [#uses=1]
icmp slt i8 %tmp2, 0 ; <i1>:1 [#uses=1]
br i1 %1, label %bb, label %cond_next28
cond_next28: ; preds = %bb
store i32 %tmp11, i32* %val
ret i8* %tmp4
}

53
external/llvm/test/CodeGen/ARM/2007-03-13-InstrSched.ll vendored Normal file
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@@ -0,0 +1,53 @@
; REQUIRES: asserts
; RUN: llc -mtriple arm-apple-darwin -relocation-model pic -mattr=+v6 -filetype asm -o - %s | FileCheck -check-prefix CHECK-R9 %s
; RUN: llc -mtriple arm-apple-darwin -relocation-model pic -mattr=+v6,+reserve-r9 -ifcvt-limit=0 -stats -o /dev/null %s 2>&1 | FileCheck -check-prefix CHECK-ASM-PRINTER %s
define void @test(i32 %tmp56222, i32 %tmp36224, i32 %tmp46223, i32 %i.0196.0.ph, i32 %tmp8, i32* %tmp1011, i32** %tmp1, i32* %d2.1.out, i32* %d3.1.out, i32* %d0.1.out, i32* %d1.1.out) {
newFuncRoot:
br label %bb74
bb78.exitStub:
store i32 %d2.1, i32* %d2.1.out
store i32 %d3.1, i32* %d3.1.out
store i32 %d0.1, i32* %d0.1.out
store i32 %d1.1, i32* %d1.1.out
ret void
bb74:
%fp.1.rec = phi i32 [ 0, %newFuncRoot ], [ %tmp71.rec, %bb26 ]
%fm.1.in = phi i32* [ %tmp71, %bb26 ], [ %tmp1011, %newFuncRoot ]
%d0.1 = phi i32 [ %tmp44, %bb26 ], [ 8192, %newFuncRoot ]
%d1.1 = phi i32 [ %tmp54, %bb26 ], [ 8192, %newFuncRoot ]
%d2.1 = phi i32 [ %tmp64, %bb26 ], [ 8192, %newFuncRoot ]
%d3.1 = phi i32 [ %tmp69, %bb26 ], [ 8192, %newFuncRoot ]
%fm.1 = load i32, i32* %fm.1.in
icmp eq i32 %fp.1.rec, %tmp8
br i1 %0, label %bb78.exitStub, label %bb26
bb26:
%tmp28 = getelementptr i32*, i32** %tmp1, i32 %fp.1.rec
%tmp30 = load i32*, i32** %tmp28
%tmp33 = getelementptr i32, i32* %tmp30, i32 %i.0196.0.ph
%tmp34 = load i32, i32* %tmp33
%tmp38 = getelementptr i32, i32* %tmp30, i32 %tmp36224
%tmp39 = load i32, i32* %tmp38
%tmp42 = mul i32 %tmp34, %fm.1
%tmp44 = add i32 %tmp42, %d0.1
%tmp48 = getelementptr i32, i32* %tmp30, i32 %tmp46223
%tmp49 = load i32, i32* %tmp48
%tmp52 = mul i32 %tmp39, %fm.1
%tmp54 = add i32 %tmp52, %d1.1
%tmp58 = getelementptr i32, i32* %tmp30, i32 %tmp56222
%tmp59 = load i32, i32* %tmp58
%tmp62 = mul i32 %tmp49, %fm.1
%tmp64 = add i32 %tmp62, %d2.1
%tmp67 = mul i32 %tmp59, %fm.1
%tmp69 = add i32 %tmp67, %d3.1
%tmp71.rec = add i32 %fp.1.rec, 1
%tmp71 = getelementptr i32, i32* %tmp1011, i32 %tmp71.rec
br label %bb74
}
; CHECK-R9: r9
; CHECK-ASM-PRINTER: asm-printer

96
external/llvm/test/CodeGen/ARM/2007-03-21-JoinIntervalsCrash.ll vendored Normal file
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@@ -0,0 +1,96 @@
; RUN: llc < %s -mtriple=arm-linux-gnueabi
; PR1257
%struct.CUMULATIVE_ARGS = type { i32, i32, i32, i32, i32, i32 }
%struct.arm_stack_offsets = type { i32, i32, i32, i32, i32 }
%struct.c_arg_info = type { %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, i8 }
%struct.c_language_function = type { %struct.stmt_tree_s }
%struct.c_switch = type opaque
%struct.eh_status = type opaque
%struct.emit_status = type { i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack*, i32, %struct.location_t, i32, i8*, %struct.rtx_def** }
%struct.expr_status = type { i32, i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def* }
%struct.function = type { %struct.eh_status*, %struct.expr_status*, %struct.emit_status*, %struct.varasm_status*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.function*, i32, i32, i32, i32, %struct.rtx_def*, %struct.CUMULATIVE_ARGS, %struct.rtx_def*, %struct.rtx_def*, %struct.initial_value_struct*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, i8, i32, i64, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, %struct.varray_head_tag*, %struct.temp_slot*, i32, %struct.var_refs_queue*, i32, i32, %struct.rtvec_def*, %struct.tree_node*, i32, i32, i32, %struct.machine_function*, i32, i32, i8, i8, %struct.language_function*, %struct.rtx_def*, i32, i32, i32, i32, %struct.location_t, %struct.varray_head_tag*, %struct.tree_node*, i8, i8, i8 }
%struct.ht_identifier = type { i8*, i32, i32 }
%struct.initial_value_struct = type opaque
%struct.lang_decl = type { i8 }
%struct.language_function = type { %struct.c_language_function, %struct.tree_node*, %struct.tree_node*, %struct.c_switch*, %struct.c_arg_info*, i32, i32, i32, i32 }
%struct.location_t = type { i8*, i32 }
%struct.machine_function = type { %struct.rtx_def*, i32, i32, i32, %struct.arm_stack_offsets, i32, i32, i32, [14 x %struct.rtx_def*] }
%struct.rtvec_def = type { i32, [1 x %struct.rtx_def*] }
%struct.rtx_def = type { i16, i8, i8, %struct.u }
%struct.sequence_stack = type { %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack* }
%struct.stmt_tree_s = type { %struct.tree_node*, i32 }
%struct.temp_slot = type opaque
%struct.tree_common = type { %struct.tree_node*, %struct.tree_node*, %union.tree_ann_d*, i8, i8, i8, i8, i8 }
%struct.tree_decl = type { %struct.tree_common, %struct.location_t, i32, %struct.tree_node*, i8, i8, i8, i8, i8, i8, i8, i8, i32, %struct.tree_decl_u1, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, i32, %struct.tree_decl_u2, %struct.tree_node*, %struct.tree_node*, i64, %struct.lang_decl* }
%struct.tree_decl_u1 = type { i64 }
%struct.tree_decl_u2 = type { %struct.function* }
%struct.tree_identifier = type { %struct.tree_common, %struct.ht_identifier }
%struct.tree_node = type { %struct.tree_decl }
%struct.u = type { [1 x i64] }
%struct.var_refs_queue = type { %struct.rtx_def*, i32, i32, %struct.var_refs_queue* }
%struct.varasm_status = type opaque
%struct.varray_head_tag = type opaque
%union.tree_ann_d = type opaque
define void @declspecs_add_type(i32 %spec.1) {
entry:
%spec.1961 = zext i32 %spec.1 to i64 ; <i64> [#uses=1]
%spec.1961.adj = shl i64 %spec.1961, 32 ; <i64> [#uses=1]
%spec.1961.adj.ins = or i64 %spec.1961.adj, 0 ; <i64> [#uses=2]
%tmp10959 = lshr i64 %spec.1961.adj.ins, 32 ; <i64> [#uses=2]
%tmp1920 = inttoptr i64 %tmp10959 to %struct.tree_common* ; <%struct.tree_common*> [#uses=1]
%tmp21 = getelementptr %struct.tree_common, %struct.tree_common* %tmp1920, i32 0, i32 3 ; <i8*> [#uses=1]
%tmp2122 = bitcast i8* %tmp21 to i32* ; <i32*> [#uses=1]
br i1 false, label %cond_next53, label %cond_true
cond_true: ; preds = %entry
ret void
cond_next53: ; preds = %entry
br i1 false, label %cond_true63, label %cond_next689
cond_true63: ; preds = %cond_next53
ret void
cond_next689: ; preds = %cond_next53
br i1 false, label %cond_false841, label %bb743
bb743: ; preds = %cond_next689
ret void
cond_false841: ; preds = %cond_next689
br i1 false, label %cond_true851, label %cond_true918
cond_true851: ; preds = %cond_false841
tail call void @lookup_name( )
br i1 false, label %bb866, label %cond_next856
cond_next856: ; preds = %cond_true851
ret void
bb866: ; preds = %cond_true851
%tmp874 = load i32, i32* %tmp2122 ; <i32> [#uses=1]
%tmp876877 = trunc i32 %tmp874 to i8 ; <i8> [#uses=1]
icmp eq i8 %tmp876877, 1 ; <i1>:0 [#uses=1]
br i1 %0, label %cond_next881, label %cond_true878
cond_true878: ; preds = %bb866
unreachable
cond_next881: ; preds = %bb866
%tmp884885 = inttoptr i64 %tmp10959 to %struct.tree_identifier* ; <%struct.tree_identifier*> [#uses=1]
%tmp887 = getelementptr %struct.tree_identifier, %struct.tree_identifier* %tmp884885, i32 0, i32 1, i32 0 ; <i8**> [#uses=1]
%tmp888 = load i8*, i8** %tmp887 ; <i8*> [#uses=1]
tail call void (i32, ...) @error( i32 undef, i8* %tmp888 )
ret void
cond_true918: ; preds = %cond_false841
%tmp920957 = trunc i64 %spec.1961.adj.ins to i32 ; <i32> [#uses=0]
ret void
}
declare void @error(i32, ...)
declare void @lookup_name()

35
external/llvm/test/CodeGen/ARM/2007-03-27-RegScavengerAssert.ll vendored Normal file
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@@ -0,0 +1,35 @@
; RUN: llc < %s -mtriple=arm-linux-gnueabi
; PR1279
%struct.rtx_def = type { i16, i8, i8, %struct.u }
%struct.u = type { [1 x i64] }
define fastcc void @find_reloads_address(%struct.rtx_def** %loc) {
entry:
%ad_addr = alloca %struct.rtx_def* ; <%struct.rtx_def**> [#uses=2]
br i1 false, label %cond_next416, label %cond_true340
cond_true340: ; preds = %entry
ret void
cond_next416: ; preds = %entry
%tmp1085 = load %struct.rtx_def*, %struct.rtx_def** %ad_addr ; <%struct.rtx_def*> [#uses=1]
br i1 false, label %bb1084, label %cond_true418
cond_true418: ; preds = %cond_next416
ret void
bb1084: ; preds = %cond_next416
br i1 false, label %cond_true1092, label %cond_next1102
cond_true1092: ; preds = %bb1084
%tmp1094 = getelementptr %struct.rtx_def, %struct.rtx_def* %tmp1085, i32 0, i32 3 ; <%struct.u*> [#uses=1]
%tmp10981099 = bitcast %struct.u* %tmp1094 to %struct.rtx_def** ; <%struct.rtx_def**> [#uses=2]
%tmp1101 = load %struct.rtx_def*, %struct.rtx_def** %tmp10981099 ; <%struct.rtx_def*> [#uses=1]
store %struct.rtx_def* %tmp1101, %struct.rtx_def** %ad_addr
br label %cond_next1102
cond_next1102: ; preds = %cond_true1092, %bb1084
%loc_addr.0 = phi %struct.rtx_def** [ %tmp10981099, %cond_true1092 ], [ %loc, %bb1084 ] ; <%struct.rtx_def**> [#uses=0]
ret void
}

101
external/llvm/test/CodeGen/ARM/2007-03-30-RegScavengerAssert.ll vendored Normal file
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@@ -0,0 +1,101 @@
; RUN: llc < %s -mtriple=arm-linux-gnueabi
; PR1279
%struct.CUMULATIVE_ARGS = type { i32, i32, i32, i32, i32, i32 }
%struct.arm_stack_offsets = type { i32, i32, i32, i32, i32 }
%struct.eh_status = type opaque
%struct.emit_status = type { i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack*, i32, %struct.location_t, i32, i8*, %struct.rtx_def** }
%struct.expr_status = type { i32, i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def* }
%struct.function = type { %struct.eh_status*, %struct.expr_status*, %struct.emit_status*, %struct.varasm_status*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.function*, i32, i32, i32, i32, %struct.rtx_def*, %struct.CUMULATIVE_ARGS, %struct.rtx_def*, %struct.rtx_def*, %struct.initial_value_struct*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, i8, i32, i64, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, %struct.varray_head_tag*, %struct.temp_slot*, i32, %struct.var_refs_queue*, i32, i32, %struct.rtvec_def*, %struct.tree_node*, i32, i32, i32, %struct.machine_function*, i32, i32, i8, i8, %struct.language_function*, %struct.rtx_def*, i32, i32, i32, i32, %struct.location_t, %struct.varray_head_tag*, %struct.tree_node*, i8, i8, i8 }
%struct.initial_value_struct = type opaque
%struct.lang_decl = type opaque
%struct.language_function = type opaque
%struct.location_t = type { i8*, i32 }
%struct.machine_function = type { %struct.rtx_def*, i32, i32, i32, %struct.arm_stack_offsets, i32, i32, i32, [14 x %struct.rtx_def*] }
%struct.rtvec_def = type { i32, [1 x %struct.rtx_def*] }
%struct.rtx_def = type { i16, i8, i8, %struct.u }
%struct.sequence_stack = type { %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack* }
%struct.temp_slot = type opaque
%struct.tree_common = type { %struct.tree_node*, %struct.tree_node*, %union.tree_ann_d*, i8, i8, i8, i8, i8 }
%struct.tree_decl = type { %struct.tree_common, %struct.location_t, i32, %struct.tree_node*, i8, i8, i8, i8, i8, i8, i8, i8, i32, %struct.tree_decl_u1, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, i32, %struct.tree_decl_u2, %struct.tree_node*, %struct.tree_node*, i64, %struct.lang_decl* }
%struct.tree_decl_u1 = type { i64 }
%struct.tree_decl_u2 = type { %struct.function* }
%struct.tree_node = type { %struct.tree_decl }
%struct.u = type { [1 x i64] }
%struct.var_refs_queue = type { %struct.rtx_def*, i32, i32, %struct.var_refs_queue* }
%struct.varasm_status = type opaque
%struct.varray_head_tag = type { i32, i32, i32, i8*, %struct.u }
%union.tree_ann_d = type opaque
@str469 = external global [42 x i8] ; <[42 x i8]*> [#uses=0]
@__FUNCTION__.24265 = external global [19 x i8] ; <[19 x i8]*> [#uses=0]
declare void @fancy_abort()
define fastcc void @fold_builtin_bitop() {
entry:
br i1 false, label %cond_true105, label %UnifiedReturnBlock
cond_true105: ; preds = %entry
br i1 false, label %cond_true134, label %UnifiedReturnBlock
cond_true134: ; preds = %cond_true105
switch i32 0, label %bb479 [
i32 378, label %bb313
i32 380, label %bb313
i32 381, label %bb313
i32 383, label %bb366
i32 385, label %bb366
i32 386, label %bb366
i32 403, label %bb250
i32 405, label %bb250
i32 406, label %bb250
i32 434, label %bb464
i32 436, label %bb464
i32 437, label %bb464
i32 438, label %bb441
i32 440, label %bb441
i32 441, label %bb441
]
bb250: ; preds = %cond_true134, %cond_true134, %cond_true134
ret void
bb313: ; preds = %cond_true134, %cond_true134, %cond_true134
ret void
bb366: ; preds = %cond_true134, %cond_true134, %cond_true134
ret void
bb441: ; preds = %cond_true134, %cond_true134, %cond_true134
ret void
bb457: ; preds = %bb464, %bb457
%tmp459 = add i64 0, 1 ; <i64> [#uses=1]
br i1 false, label %bb474.preheader, label %bb457
bb464: ; preds = %cond_true134, %cond_true134, %cond_true134
br i1 false, label %bb474.preheader, label %bb457
bb474.preheader: ; preds = %bb464, %bb457
%result.5.ph = phi i64 [ 0, %bb464 ], [ %tmp459, %bb457 ] ; <i64> [#uses=1]
br label %bb474
bb467: ; preds = %bb474
%indvar.next586 = add i64 %indvar585, 1 ; <i64> [#uses=1]
br label %bb474
bb474: ; preds = %bb467, %bb474.preheader
%indvar585 = phi i64 [ 0, %bb474.preheader ], [ %indvar.next586, %bb467 ] ; <i64> [#uses=2]
br i1 false, label %bb476, label %bb467
bb476: ; preds = %bb474
%result.5 = add i64 %indvar585, %result.5.ph ; <i64> [#uses=0]
ret void
bb479: ; preds = %cond_true134
tail call void @fancy_abort( )
unreachable
UnifiedReturnBlock: ; preds = %cond_true105, %entry
ret void
}

55
external/llvm/test/CodeGen/ARM/2007-04-02-RegScavengerAssert.ll vendored Normal file
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@@ -0,0 +1,55 @@
; RUN: llc < %s -mtriple=arm-apple-darwin
%struct.H_TBL = type { [17 x i8], [256 x i8], i32 }
%struct.Q_TBL = type { [64 x i16], i32 }
%struct.anon = type { [80 x i8] }
%struct.X_c_coef_ccler = type { void (%struct.X_Y*, i32)*, i32 (%struct.X_Y*, i8***)* }
%struct.X_c_main_ccler = type { void (%struct.X_Y*, i32)*, void (%struct.X_Y*, i8**, i32*, i32)* }
%struct.X_c_prep_ccler = type { void (%struct.X_Y*, i32)*, void (%struct.X_Y*, i8**, i32*, i32, i8***, i32*, i32)* }
%struct.X_color_converter = type { void (%struct.X_Y*)*, void (%struct.X_Y*, i8**, i8***, i32, i32)* }
%struct.X_common_struct = type { %struct.X_error_mgr*, %struct.X_memory_mgr*, %struct.X_progress_mgr*, i8*, i32, i32 }
%struct.X_comp_master = type { void (%struct.X_Y*)*, void (%struct.X_Y*)*, void (%struct.X_Y*)*, i32, i32 }
%struct.X_component_info = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.Q_TBL*, i8* }
%struct.X_Y = type { %struct.X_error_mgr*, %struct.X_memory_mgr*, %struct.X_progress_mgr*, i8*, i32, i32, %struct.X_destination_mgr*, i32, i32, i32, i32, double, i32, i32, i32, %struct.X_component_info*, [4 x %struct.Q_TBL*], [4 x %struct.H_TBL*], [4 x %struct.H_TBL*], [16 x i8], [16 x i8], [16 x i8], i32, %struct.X_scan_info*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8, i8, i8, i16, i16, i32, i32, i32, i32, i32, i32, i32, [4 x %struct.X_component_info*], i32, i32, i32, [10 x i32], i32, i32, i32, i32, %struct.X_comp_master*, %struct.X_c_main_ccler*, %struct.X_c_prep_ccler*, %struct.X_c_coef_ccler*, %struct.X_marker_writer*, %struct.X_color_converter*, %struct.X_downssr*, %struct.X_forward_D*, %struct.X_entropy_en*, %struct.X_scan_info*, i32 }
%struct.X_destination_mgr = type { i8*, i32, void (%struct.X_Y*)*, i32 (%struct.X_Y*)*, void (%struct.X_Y*)* }
%struct.X_downssr = type { void (%struct.X_Y*)*, void (%struct.X_Y*, i8***, i32, i8***, i32)*, i32 }
%struct.X_entropy_en = type { void (%struct.X_Y*, i32)*, i32 (%struct.X_Y*, [64 x i16]**)*, void (%struct.X_Y*)* }
%struct.X_error_mgr = type { void (%struct.X_common_struct*)*, void (%struct.X_common_struct*, i32)*, void (%struct.X_common_struct*)*, void (%struct.X_common_struct*, i8*)*, void (%struct.X_common_struct*)*, i32, %struct.anon, i32, i32, i8**, i32, i8**, i32, i32 }
%struct.X_forward_D = type { void (%struct.X_Y*)*, void (%struct.X_Y*, %struct.X_component_info*, i8**, [64 x i16]*, i32, i32, i32)* }
%struct.X_marker_writer = type { void (%struct.X_Y*)*, void (%struct.X_Y*)*, void (%struct.X_Y*)*, void (%struct.X_Y*)*, void (%struct.X_Y*)*, void (%struct.X_Y*, i32, i32)*, void (%struct.X_Y*, i32)* }
%struct.X_memory_mgr = type { i8* (%struct.X_common_struct*, i32, i32)*, i8* (%struct.X_common_struct*, i32, i32)*, i8** (%struct.X_common_struct*, i32, i32, i32)*, [64 x i16]** (%struct.X_common_struct*, i32, i32, i32)*, %struct.jvirt_sAY_cc* (%struct.X_common_struct*, i32, i32, i32, i32, i32)*, %struct.jvirt_bAY_cc* (%struct.X_common_struct*, i32, i32, i32, i32, i32)*, void (%struct.X_common_struct*)*, i8** (%struct.X_common_struct*, %struct.jvirt_sAY_cc*, i32, i32, i32)*, [64 x i16]** (%struct.X_common_struct*, %struct.jvirt_bAY_cc*, i32, i32, i32)*, void (%struct.X_common_struct*, i32)*, void (%struct.X_common_struct*)*, i32, i32 }
%struct.X_progress_mgr = type { void (%struct.X_common_struct*)*, i32, i32, i32, i32 }
%struct.X_scan_info = type { i32, [4 x i32], i32, i32, i32, i32 }
%struct.jvirt_bAY_cc = type opaque
%struct.jvirt_sAY_cc = type opaque
define void @test(%struct.X_Y* %cinfo) {
entry:
br i1 false, label %bb.preheader, label %return
bb.preheader: ; preds = %entry
%tbl.014.us = load i32, i32* null ; <i32> [#uses=1]
br i1 false, label %cond_next.us, label %bb
cond_next51.us: ; preds = %cond_next.us, %cond_true33.us.cond_true46.us_crit_edge
%htblptr.019.1.us = phi %struct.H_TBL** [ %tmp37.us, %cond_true33.us.cond_true46.us_crit_edge ], [ %tmp37.us, %cond_next.us ] ; <%struct.H_TBL**> [#uses=0]
ret void
cond_true33.us.cond_true46.us_crit_edge: ; preds = %cond_next.us
call void @_C_X_a_HT( )
br label %cond_next51.us
cond_next.us: ; preds = %bb.preheader
%tmp37.us = getelementptr %struct.X_Y, %struct.X_Y* %cinfo, i32 0, i32 17, i32 %tbl.014.us ; <%struct.H_TBL**> [#uses=3]
%tmp4524.us = load %struct.H_TBL*, %struct.H_TBL** %tmp37.us ; <%struct.H_TBL*> [#uses=1]
icmp eq %struct.H_TBL* %tmp4524.us, null ; <i1>:0 [#uses=1]
br i1 %0, label %cond_true33.us.cond_true46.us_crit_edge, label %cond_next51.us
bb: ; preds = %bb.preheader
ret void
return: ; preds = %entry
ret void
}
declare void @_C_X_a_HT()

15
external/llvm/test/CodeGen/ARM/2007-04-03-PEIBug.ll vendored Normal file
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@@ -0,0 +1,15 @@
; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
define i32 @foo() {
entry:
%A = alloca [1123 x i32], align 16 ; <[1123 x i32]*> [#uses=1]
%B = alloca [3123 x i32], align 16 ; <[3123 x i32]*> [#uses=1]
%C = alloca [12312 x i32], align 16 ; <[12312 x i32]*> [#uses=1]
%tmp = call i32 (...) @bar( [3123 x i32]* %B, [1123 x i32]* %A, [12312 x i32]* %C ) ; <i32> [#uses=0]
ret i32 undef
}
declare i32 @bar(...)
; CHECK-NOT: add{{.*}}#0

101
external/llvm/test/CodeGen/ARM/2007-04-03-UndefinedSymbol.ll vendored Normal file
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@@ -0,0 +1,101 @@
; RUN: llc -mtriple arm-apple-darwin -relocation-model pic -filetype asm -o - %s | FileCheck %s
%struct.B = type { i32 }
%struct.anon = type { void (%struct.B*)*, i32 }
@str = internal constant [7 x i8] c"i, %d\0A\00"
@str1 = internal constant [7 x i8] c"j, %d\0A\00"
define internal void @_ZN1B1iEv(%struct.B* %this) {
entry:
%tmp1 = getelementptr %struct.B, %struct.B* %this, i32 0, i32 0
%tmp2 = load i32, i32* %tmp1
%tmp4 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([7 x i8], [7 x i8]* @str, i32 0, i32 0), i32 %tmp2)
ret void
}
declare i32 @printf(i8*, ...)
define internal void @_ZN1B1jEv(%struct.B* %this) {
entry:
%tmp1 = getelementptr %struct.B, %struct.B* %this, i32 0, i32 0
%tmp2 = load i32, i32* %tmp1
%tmp4 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([7 x i8], [7 x i8]* @str1, i32 0, i32 0), i32 %tmp2)
ret void
}
define i32 @main() {
entry:
%b.i29 = alloca %struct.B, align 4
%b.i1 = alloca %struct.B, align 4
%b.i = alloca %struct.B, align 4
%tmp2.i = getelementptr %struct.B, %struct.B* %b.i, i32 0, i32 0
store i32 4, i32* %tmp2.i
br i1 icmp eq (i64 and (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 4294967296), i64 0), label %_Z3fooiM1BFvvE.exit, label %cond_true.i
cond_true.i:
%b2.i = bitcast %struct.B* %b.i to i8*
%ctg23.i = getelementptr i8, i8* %b2.i, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 32) to i32), i32 1)
%tmp121314.i = bitcast i8* %ctg23.i to i32 (...)***
%tmp15.i = load i32 (...)**, i32 (...)*** %tmp121314.i
%tmp151.i = bitcast i32 (...)** %tmp15.i to i8*
%ctg2.i = getelementptr i8, i8* %tmp151.i, i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32)
%tmp2021.i = bitcast i8* %ctg2.i to i32 (...)**
%tmp22.i = load i32 (...)*, i32 (...)** %tmp2021.i
%tmp2223.i = bitcast i32 (...)* %tmp22.i to void (%struct.B*)*
br label %_Z3fooiM1BFvvE.exit
_Z3fooiM1BFvvE.exit:
%iftmp.2.0.i = phi void (%struct.B*)* [ %tmp2223.i, %cond_true.i ], [ inttoptr (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to void (%struct.B*)*), %entry ]
%b4.i = bitcast %struct.B* %b.i to i8*
%ctg25.i = getelementptr i8, i8* %b4.i, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 32) to i32), i32 1)
%tmp3031.i = bitcast i8* %ctg25.i to %struct.B*
call void %iftmp.2.0.i(%struct.B* %tmp3031.i)
%tmp2.i30 = getelementptr %struct.B, %struct.B* %b.i29, i32 0, i32 0
store i32 6, i32* %tmp2.i30
br i1 icmp eq (i64 and (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1jEv to i32) to i64), i64 4294967296), i64 0), label %_Z3fooiM1BFvvE.exit56, label %cond_true.i46
cond_true.i46:
%b2.i35 = bitcast %struct.B* %b.i29 to i8*
%ctg23.i36 = getelementptr i8, i8* %b2.i35, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1jEv to i32) to i64), i64 32) to i32), i32 1)
%tmp121314.i37 = bitcast i8* %ctg23.i36 to i32 (...)***
%tmp15.i38 = load i32 (...)**, i32 (...)*** %tmp121314.i37
%tmp151.i41 = bitcast i32 (...)** %tmp15.i38 to i8*
%ctg2.i42 = getelementptr i8, i8* %tmp151.i41, i32 ptrtoint (void (%struct.B*)* @_ZN1B1jEv to i32)
%tmp2021.i43 = bitcast i8* %ctg2.i42 to i32 (...)**
%tmp22.i44 = load i32 (...)*, i32 (...)** %tmp2021.i43
%tmp2223.i45 = bitcast i32 (...)* %tmp22.i44 to void (%struct.B*)*
br label %_Z3fooiM1BFvvE.exit56
_Z3fooiM1BFvvE.exit56:
%iftmp.2.0.i49 = phi void (%struct.B*)* [ %tmp2223.i45, %cond_true.i46 ], [ inttoptr (i32 ptrtoint (void (%struct.B*)* @_ZN1B1jEv to i32) to void (%struct.B*)*), %_Z3fooiM1BFvvE.exit ]
%b4.i53 = bitcast %struct.B* %b.i29 to i8*
%ctg25.i54 = getelementptr i8, i8* %b4.i53, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1jEv to i32) to i64), i64 32) to i32), i32 1)
%tmp3031.i55 = bitcast i8* %ctg25.i54 to %struct.B*
call void %iftmp.2.0.i49(%struct.B* %tmp3031.i55)
%tmp2.i2 = getelementptr %struct.B, %struct.B* %b.i1, i32 0, i32 0
store i32 -1, i32* %tmp2.i2
br i1 icmp eq (i64 and (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 4294967296), i64 0), label %_Z3fooiM1BFvvE.exit28, label %cond_true.i18
cond_true.i18:
%b2.i7 = bitcast %struct.B* %b.i1 to i8*
%ctg23.i8 = getelementptr i8, i8* %b2.i7, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 32) to i32), i32 1)
%tmp121314.i9 = bitcast i8* %ctg23.i8 to i32 (...)***
%tmp15.i10 = load i32 (...)**, i32 (...)*** %tmp121314.i9
%tmp151.i13 = bitcast i32 (...)** %tmp15.i10 to i8*
%ctg2.i14 = getelementptr i8, i8* %tmp151.i13, i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32)
%tmp2021.i15 = bitcast i8* %ctg2.i14 to i32 (...)**
%tmp22.i16 = load i32 (...)*, i32 (...)** %tmp2021.i15
%tmp2223.i17 = bitcast i32 (...)* %tmp22.i16 to void (%struct.B*)*
br label %_Z3fooiM1BFvvE.exit28
_Z3fooiM1BFvvE.exit28:
%iftmp.2.0.i21 = phi void (%struct.B*)* [ %tmp2223.i17, %cond_true.i18 ], [ inttoptr (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to void (%struct.B*)*), %_Z3fooiM1BFvvE.exit56 ]
%b4.i25 = bitcast %struct.B* %b.i1 to i8*
%ctg25.i26 = getelementptr i8, i8* %b4.i25, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 32) to i32), i32 1)
%tmp3031.i27 = bitcast i8* %ctg25.i26 to %struct.B*
call void %iftmp.2.0.i21(%struct.B* %tmp3031.i27)
ret i32 0
}
; CHECK-NOT: LPC9

32
external/llvm/test/CodeGen/ARM/2007-04-30-CombinerCrash.ll vendored Normal file
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@@ -0,0 +1,32 @@
; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6,+vfp2
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
target triple = "arm-apple-darwin8"
%struct.CHESS_POSITION = type { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32, i32, i8, i8, [64 x i8], i8, i8, i8, i8, i8 }
@search = external global %struct.CHESS_POSITION ; <%struct.CHESS_POSITION*> [#uses=3]
@file_mask = external global [8 x i64] ; <[8 x i64]*> [#uses=1]
@rank_mask.1.b = external global i1 ; <i1*> [#uses=1]
define fastcc void @EvaluateDevelopment() {
entry:
%tmp7 = load i64, i64* getelementptr (%struct.CHESS_POSITION, %struct.CHESS_POSITION* @search, i32 0, i32 7) ; <i64> [#uses=1]
%tmp50 = load i64, i64* getelementptr (%struct.CHESS_POSITION, %struct.CHESS_POSITION* @search, i32 0, i32 0) ; <i64> [#uses=1]
%tmp52 = load i64, i64* getelementptr (%struct.CHESS_POSITION, %struct.CHESS_POSITION* @search, i32 0, i32 1) ; <i64> [#uses=1]
%tmp53 = or i64 %tmp52, %tmp50 ; <i64> [#uses=1]
%tmp57.b = load i1, i1* @rank_mask.1.b ; <i1> [#uses=1]
%tmp57 = select i1 %tmp57.b, i64 71776119061217280, i64 0 ; <i64> [#uses=1]
%tmp58 = and i64 %tmp57, %tmp7 ; <i64> [#uses=1]
%tmp59 = lshr i64 %tmp58, 8 ; <i64> [#uses=1]
%tmp63 = load i64, i64* getelementptr ([8 x i64], [8 x i64]* @file_mask, i32 0, i32 4) ; <i64> [#uses=1]
%tmp64 = or i64 %tmp63, 0 ; <i64> [#uses=1]
%tmp65 = and i64 %tmp59, %tmp53 ; <i64> [#uses=1]
%tmp66 = and i64 %tmp65, %tmp64 ; <i64> [#uses=1]
%tmp67 = icmp eq i64 %tmp66, 0 ; <i1> [#uses=1]
br i1 %tmp67, label %cond_next145, label %cond_true70
cond_true70: ; preds = %entry
ret void
cond_next145: ; preds = %entry
ret void
}

113
external/llvm/test/CodeGen/ARM/2007-05-03-BadPostIndexedLd.ll vendored Normal file
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@@ -0,0 +1,113 @@
; RUN: llc < %s -mtriple=arm-apple-darwin
%struct.Connection = type { i32, [10 x i8], i32 }
%struct.IntChunk = type { %struct.cppobjtype, i32, i32*, i32 }
%struct.Point = type { i8*, %struct.cppobjtype, i16 (%struct.Point*) *, i16 (%struct.Point*) *, double (%struct.Point*)*, double (%struct.Point*)* }
%struct.RefPoint = type { %struct.Point*, %struct.cppobjtype }
%struct.ShortArray = type { %struct.cppobjtype, i32, i16* }
%struct.TestObj = type { i8*, %struct.cppobjtype, i8, [32 x i8], i8*, i8**, i16, i16, i32, i32, i32, i32, float, double, %struct.cppobjtype, i32, i16*, i16**, i8**, i32, %struct.XyPoint, [3 x %struct.Connection], %struct.Point*, %struct.XyPoint*, i32, i8*, i8*, i16*, %struct.ShortArray, %struct.IntChunk, %struct.cppobjtype, %struct.cppobjtype, %struct.RefPoint, i32, %struct.cppobjtype, %struct.cppobjtype }
%struct.XyPoint = type { i16, i16 }
%struct.cppobjtype = type { i32, i16, i16 }
@Msg = external global [256 x i8] ; <[256 x i8]*> [#uses=1]
@.str53615 = external constant [48 x i8] ; <[48 x i8]*> [#uses=1]
@FirstTime.4637.b = external global i1 ; <i1*> [#uses=1]
define fastcc void @Draw7(i32 %Option, i32* %Status) {
entry:
%tmp115.b = load i1, i1* @FirstTime.4637.b ; <i1> [#uses=1]
br i1 %tmp115.b, label %cond_next239, label %cond_next.i
cond_next.i: ; preds = %entry
ret void
cond_next239: ; preds = %entry
%tmp242 = icmp eq i32 0, 0 ; <i1> [#uses=1]
br i1 %tmp242, label %cond_next253, label %cond_next296
cond_next253: ; preds = %cond_next239
switch i32 %Option, label %bb1326 [
i32 3, label %cond_true258
i32 4, label %cond_true268
i32 2, label %cond_true279
i32 1, label %cond_next315
]
cond_true258: ; preds = %cond_next253
ret void
cond_true268: ; preds = %cond_next253
ret void
cond_true279: ; preds = %cond_next253
ret void
cond_next296: ; preds = %cond_next239
ret void
cond_next315: ; preds = %cond_next253
%tmp1140 = icmp eq i32 0, 0 ; <i1> [#uses=1]
br i1 %tmp1140, label %cond_true1143, label %bb1326
cond_true1143: ; preds = %cond_next315
%tmp1148 = icmp eq i32 0, 0 ; <i1> [#uses=4]
br i1 %tmp1148, label %cond_next1153, label %cond_true1151
cond_true1151: ; preds = %cond_true1143
ret void
cond_next1153: ; preds = %cond_true1143
%tmp8.i.i185 = icmp eq i32 0, 0 ; <i1> [#uses=1]
br i1 %tmp8.i.i185, label %TestObj_new1.exit, label %cond_true.i.i187
cond_true.i.i187: ; preds = %cond_next1153
ret void
TestObj_new1.exit: ; preds = %cond_next1153
%tmp1167 = icmp eq i16 0, 0 ; <i1> [#uses=1]
%tmp1178 = icmp eq i32 0, 0 ; <i1> [#uses=1]
%bothcond = and i1 %tmp1167, %tmp1178 ; <i1> [#uses=1]
br i1 %bothcond, label %bb1199, label %bb1181
bb1181: ; preds = %TestObj_new1.exit
ret void
bb1199: ; preds = %TestObj_new1.exit
br i1 %tmp1148, label %cond_next1235, label %Object_Dump.exit302
Object_Dump.exit302: ; preds = %bb1199
ret void
cond_next1235: ; preds = %bb1199
%bothcond10485 = or i1 false, %tmp1148 ; <i1> [#uses=1]
br i1 %bothcond10485, label %cond_next1267, label %cond_true1248
cond_true1248: ; preds = %cond_next1235
ret void
cond_next1267: ; preds = %cond_next1235
br i1 %tmp1148, label %cond_next1275, label %cond_true1272
cond_true1272: ; preds = %cond_next1267
%tmp1273 = load %struct.TestObj*, %struct.TestObj** null ; <%struct.TestObj*> [#uses=2]
%tmp2930.i = ptrtoint %struct.TestObj* %tmp1273 to i32 ; <i32> [#uses=1]
%tmp42.i348 = sub i32 0, %tmp2930.i ; <i32> [#uses=1]
%tmp45.i = getelementptr %struct.TestObj, %struct.TestObj* %tmp1273, i32 0, i32 0 ; <i8**> [#uses=2]
%tmp48.i = load i8*, i8** %tmp45.i ; <i8*> [#uses=1]
%tmp50.i350 = call i32 (i8*, i8*, ...) @sprintf( i8* getelementptr ([256 x i8], [256 x i8]* @Msg, i32 0, i32 0), i8* getelementptr ([48 x i8], [48 x i8]* @.str53615, i32 0, i32 0), i8* null, i8** %tmp45.i, i8* %tmp48.i ) ; <i32> [#uses=0]
br i1 false, label %cond_true.i632.i, label %Ut_TraceMsg.exit648.i
cond_true.i632.i: ; preds = %cond_true1272
ret void
Ut_TraceMsg.exit648.i: ; preds = %cond_true1272
%tmp57.i = getelementptr i8, i8* null, i32 %tmp42.i348 ; <i8*> [#uses=0]
ret void
cond_next1275: ; preds = %cond_next1267
ret void
bb1326: ; preds = %cond_next315, %cond_next253
ret void
}
declare i32 @sprintf(i8*, i8*, ...)

68
external/llvm/test/CodeGen/ARM/2007-05-07-tailmerge-1.ll vendored Normal file
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@@ -0,0 +1,68 @@
; RUN: llc < %s -enable-tail-merge | FileCheck %s
; Check that calls to baz and quux are tail-merged.
; PR1628
; CHECK: bl _baz
; CHECK-NOT: bl _baz
; CHECK: bl _quux
; CHECK-NOT: bl _quux
; ModuleID = 'tail.c'
target triple = "arm-apple-darwin8"
define i32 @f(i32 %i, i32 %q) {
entry:
%i_addr = alloca i32 ; <i32*> [#uses=2]
%q_addr = alloca i32 ; <i32*> [#uses=2]
%retval = alloca i32, align 4 ; <i32*> [#uses=1]
store i32 %i, i32* %i_addr
store i32 %q, i32* %q_addr
%tmp = load i32, i32* %i_addr ; <i32> [#uses=1]
%tmp1 = icmp ne i32 %tmp, 0 ; <i1> [#uses=1]
%tmp12 = zext i1 %tmp1 to i8 ; <i8> [#uses=1]
%toBool = icmp ne i8 %tmp12, 0 ; <i1> [#uses=1]
br i1 %toBool, label %cond_true, label %cond_false
cond_true: ; preds = %entry
%tmp3 = call i32 (...) @bar( ) ; <i32> [#uses=0]
%tmp4 = call i32 (...) @baz( i32 5, i32 6 ) ; <i32> [#uses=0]
br label %cond_next
cond_false: ; preds = %entry
%tmp5 = call i32 (...) @foo( ) ; <i32> [#uses=0]
%tmp6 = call i32 (...) @baz( i32 5, i32 6 ) ; <i32> [#uses=0]
br label %cond_next
cond_next: ; preds = %cond_false, %cond_true
%tmp7 = load i32, i32* %q_addr ; <i32> [#uses=1]
%tmp8 = icmp ne i32 %tmp7, 0 ; <i1> [#uses=1]
%tmp89 = zext i1 %tmp8 to i8 ; <i8> [#uses=1]
%toBool10 = icmp ne i8 %tmp89, 0 ; <i1> [#uses=1]
br i1 %toBool10, label %cond_true11, label %cond_false15
cond_true11: ; preds = %cond_next
%tmp13 = call i32 (...) @foo( ) ; <i32> [#uses=0]
%tmp14 = call i32 (...) @quux( i32 3, i32 4 ) ; <i32> [#uses=0]
br label %cond_next18
cond_false15: ; preds = %cond_next
%tmp16 = call i32 (...) @bar( ) ; <i32> [#uses=0]
%tmp17 = call i32 (...) @quux( i32 3, i32 4 ) ; <i32> [#uses=0]
br label %cond_next18
cond_next18: ; preds = %cond_false15, %cond_true11
%tmp19 = call i32 (...) @bar( ) ; <i32> [#uses=0]
br label %return
return: ; preds = %cond_next18
%retval20 = load i32, i32* %retval ; <i32> [#uses=1]
ret i32 %retval20
}
declare i32 @bar(...)
declare i32 @baz(...)
declare i32 @foo(...)
declare i32 @quux(...)

71
external/llvm/test/CodeGen/ARM/2007-05-09-tailmerge-2.ll vendored Normal file
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@@ -0,0 +1,71 @@
; RUN: llc < %s | FileCheck %s
; Check that calls to baz and quux are tail-merged.
; CHECK: bl _baz
; CHECK-NOT: bl _baz
; CHECK: bl _quux
; CHECK-NOT: bl _quux
; PR1628
; ModuleID = 'tail.c'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
target triple = "arm-apple-darwin8"
define i32 @f(i32 %i, i32 %q) {
entry:
%i_addr = alloca i32 ; <i32*> [#uses=2]
%q_addr = alloca i32 ; <i32*> [#uses=2]
%retval = alloca i32, align 4 ; <i32*> [#uses=1]
store i32 %i, i32* %i_addr
store i32 %q, i32* %q_addr
%tmp = load i32, i32* %i_addr ; <i32> [#uses=1]
%tmp1 = icmp ne i32 %tmp, 0 ; <i1> [#uses=1]
%tmp12 = zext i1 %tmp1 to i8 ; <i8> [#uses=1]
%toBool = icmp ne i8 %tmp12, 0 ; <i1> [#uses=1]
br i1 %toBool, label %cond_true, label %cond_false
cond_true: ; preds = %entry
%tmp3 = call i32 (...) @bar( ) ; <i32> [#uses=0]
%tmp4 = call i32 (...) @baz( i32 5, i32 6 ) ; <i32> [#uses=0]
%tmp7 = load i32, i32* %q_addr ; <i32> [#uses=1]
%tmp8 = icmp ne i32 %tmp7, 0 ; <i1> [#uses=1]
%tmp89 = zext i1 %tmp8 to i8 ; <i8> [#uses=1]
%toBool10 = icmp ne i8 %tmp89, 0 ; <i1> [#uses=1]
br i1 %toBool10, label %cond_true11, label %cond_false15
cond_false: ; preds = %entry
%tmp5 = call i32 (...) @foo( ) ; <i32> [#uses=0]
%tmp6 = call i32 (...) @baz( i32 5, i32 6 ) ; <i32> [#uses=0]
%tmp27 = load i32, i32* %q_addr ; <i32> [#uses=1]
%tmp28 = icmp ne i32 %tmp27, 0 ; <i1> [#uses=1]
%tmp289 = zext i1 %tmp28 to i8 ; <i8> [#uses=1]
%toBool210 = icmp ne i8 %tmp289, 0 ; <i1> [#uses=1]
br i1 %toBool210, label %cond_true11, label %cond_false15
cond_true11: ; preds = %cond_next
%tmp13 = call i32 (...) @foo( ) ; <i32> [#uses=0]
%tmp14 = call i32 (...) @quux( i32 3, i32 4 ) ; <i32> [#uses=0]
br label %cond_next18
cond_false15: ; preds = %cond_next
%tmp16 = call i32 (...) @bar( ) ; <i32> [#uses=0]
%tmp17 = call i32 (...) @quux( i32 3, i32 4 ) ; <i32> [#uses=0]
br label %cond_next18
cond_next18: ; preds = %cond_false15, %cond_true11
%tmp19 = call i32 (...) @bar( ) ; <i32> [#uses=0]
br label %return
return: ; preds = %cond_next18
%retval20 = load i32, i32* %retval ; <i32> [#uses=1]
ret i32 %retval20
}
declare i32 @bar(...)
declare i32 @baz(...)
declare i32 @foo(...)
declare i32 @quux(...)

6
external/llvm/test/CodeGen/ARM/2007-05-14-InlineAsmCstCrash.ll vendored Normal file
View File

@@ -0,0 +1,6 @@
; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o /dev/null
define i32 @test3() {
tail call void asm sideeffect "/* number: ${0:c} */", "i"( i32 1 )
ret i32 11
}

30
external/llvm/test/CodeGen/ARM/2007-05-14-RegScavengerAssert.ll vendored Normal file
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@@ -0,0 +1,30 @@
; RUN: llc < %s -mtriple=arm-linux-gnueabi
; PR1406
%struct.AVClass = type { i8*, i8* (i8*)*, %struct.AVOption* }
%struct.AVCodec = type { i8*, i32, i32, i32, i32 (%struct.AVCodecContext*)*, i32 (%struct.AVCodecContext*, i8*, i32, i8*)*, i32 (%struct.AVCodecContext*)*, i32 (%struct.AVCodecContext*, i8*, i32*, i8*, i32)*, i32, %struct.AVCodec*, void (%struct.AVCodecContext*)*, %struct.AVRational*, i32* }
%struct.AVCodecContext = type { %struct.AVClass*, i32, i32, i32, i32, i32, i8*, i32, %struct.AVRational, i32, i32, i32, i32, i32, void (%struct.AVCodecContext*, %struct.AVFrame*, i32*, i32, i32, i32)*, i32, i32, i32, i32, i32, i32, i32, float, float, i32, i32, i32, i32, float, i32, i32, i32, %struct.AVCodec*, i8*, i32, i32, void (%struct.AVCodecContext*, i8*, i32, i32)*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8*, [32 x i8], i32, i32, i32, i32, i32, i32, i32, float, i32, i32 (%struct.AVCodecContext*, %struct.AVFrame*)*, void (%struct.AVCodecContext*, %struct.AVFrame*)*, i32, i32, i32, i32, i8*, i8*, float, float, i32, %struct.RcOverride*, i32, i8*, i32, i32, i32, float, float, float, float, i32, float, float, float, float, float, i32, i32, i32, i32*, i32, i32, i32, i32, %struct.AVRational, %struct.AVFrame*, i32, i32, [4 x i64], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 (%struct.AVCodecContext*, i32*)*, i32, i32, i32, i32, i32, i32, i8*, i32, i32, i32, i32, i32, i32, i16*, i16*, i32, i32, i32, i32, %struct.AVPaletteControl*, i32, i32 (%struct.AVCodecContext*, %struct.AVFrame*)*, i32, i32, i32, i32, i32, i32, i32, i32 (%struct.AVCodecContext*, i32 (%struct.AVCodecContext*, i8*)*, i8**, i32*, i32)*, i8*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64 }
%struct.AVFrame = type { [4 x i8*], [4 x i32], [4 x i8*], i32, i32, i64, i32, i32, i32, i32, i32, i8*, i32, i8*, [2 x [2 x i16]*], i32*, i8, i8*, [4 x i64], i32, i32, i32, i32, i32, %struct.AVPanScan*, i32, i32, i16*, [2 x i8*] }
%struct.AVOption = type opaque
%struct.AVPaletteControl = type { i32, [256 x i32] }
%struct.AVPanScan = type { i32, i32, i32, [3 x [2 x i16]] }
%struct.AVRational = type { i32, i32 }
%struct.RcOverride = type { i32, i32, i32, float }
define i32 @decode_init(%struct.AVCodecContext* %avctx) {
entry:
br i1 false, label %bb, label %cond_next789
bb: ; preds = %bb, %entry
br i1 false, label %bb59, label %bb
bb59: ; preds = %bb
%tmp68 = sdiv i64 0, 0 ; <i64> [#uses=1]
%tmp6869 = trunc i64 %tmp68 to i32 ; <i32> [#uses=2]
%tmp81 = call i32 asm "smull $0, $1, $2, $3 \0A\09mov $0, $0, lsr $4\0A\09add $1, $0, $1, lsl $5\0A\09", "=&r,=*&r,r,r,i,i"( i32* null, i32 %tmp6869, i32 13316085, i32 23, i32 9 ) ; <i32> [#uses=0]
%tmp90 = call i32 asm "smull $0, $1, $2, $3 \0A\09mov $0, $0, lsr $4\0A\09add $1, $0, $1, lsl $5\0A\09", "=&r,=*&r,r,r,i,i"( i32* null, i32 %tmp6869, i32 10568984, i32 23, i32 9 ) ; <i32> [#uses=0]
unreachable
cond_next789: ; preds = %entry
ret i32 0
}

80
external/llvm/test/CodeGen/ARM/2007-05-22-tailmerge-3.ll vendored Normal file
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@@ -0,0 +1,80 @@
; RUN: llc < %s | FileCheck %s
; RUN: llc < %s -enable-tail-merge=0 | FileCheck --check-prefix=NOMERGE %s
; Check that tail merging is the default on ARM, and that -enable-tail-merge=0
; works.
; PR1628
; CHECK: bl _baz
; CHECK-NOT: bl _baz
; CHECK: bl _quux
; CHECK-NOT: bl _quux
; NOMERGE-DAG: bl _baz
; NOMERGE-DAG: bl _baz
; NOMERGE-DAG: bl _quux
; NOMERGE-DAG: bl _quux
; ModuleID = 'tail.c'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
target triple = "arm-apple-darwin8"
define i32 @f(i32 %i, i32 %q) {
entry:
%i_addr = alloca i32 ; <i32*> [#uses=2]
%q_addr = alloca i32 ; <i32*> [#uses=2]
%retval = alloca i32, align 4 ; <i32*> [#uses=1]
store i32 %i, i32* %i_addr
store i32 %q, i32* %q_addr
%tmp = load i32, i32* %i_addr ; <i32> [#uses=1]
%tmp1 = icmp ne i32 %tmp, 0 ; <i1> [#uses=1]
%tmp12 = zext i1 %tmp1 to i8 ; <i8> [#uses=1]
%toBool = icmp ne i8 %tmp12, 0 ; <i1> [#uses=1]
br i1 %toBool, label %cond_true, label %cond_false
cond_true: ; preds = %entry
%tmp3 = call i32 (...) @bar( ) ; <i32> [#uses=0]
%tmp4 = call i32 (...) @baz( i32 5, i32 6 ) ; <i32> [#uses=0]
%tmp7 = load i32, i32* %q_addr ; <i32> [#uses=1]
%tmp8 = icmp ne i32 %tmp7, 0 ; <i1> [#uses=1]
%tmp89 = zext i1 %tmp8 to i8 ; <i8> [#uses=1]
%toBool10 = icmp ne i8 %tmp89, 0 ; <i1> [#uses=1]
br i1 %toBool10, label %cond_true11, label %cond_false15
cond_false: ; preds = %entry
%tmp5 = call i32 (...) @foo( ) ; <i32> [#uses=0]
%tmp6 = call i32 (...) @baz( i32 5, i32 6 ) ; <i32> [#uses=0]
%tmp27 = load i32, i32* %q_addr ; <i32> [#uses=1]
%tmp28 = icmp ne i32 %tmp27, 0 ; <i1> [#uses=1]
%tmp289 = zext i1 %tmp28 to i8 ; <i8> [#uses=1]
%toBool210 = icmp ne i8 %tmp289, 0 ; <i1> [#uses=1]
br i1 %toBool210, label %cond_true11, label %cond_false15
cond_true11: ; preds = %cond_next
%tmp13 = call i32 (...) @foo( ) ; <i32> [#uses=0]
%tmp14 = call i32 (...) @quux( i32 3, i32 4 ) ; <i32> [#uses=0]
br label %cond_next18
cond_false15: ; preds = %cond_next
%tmp16 = call i32 (...) @bar( ) ; <i32> [#uses=0]
%tmp17 = call i32 (...) @quux( i32 3, i32 4 ) ; <i32> [#uses=0]
br label %cond_next18
cond_next18: ; preds = %cond_false15, %cond_true11
%tmp19 = call i32 (...) @bar( ) ; <i32> [#uses=0]
br label %return
return: ; preds = %cond_next18
%retval20 = load i32, i32* %retval ; <i32> [#uses=1]
ret i32 %retval20
}
declare i32 @bar(...)
declare i32 @baz(...)
declare i32 @foo(...)
declare i32 @quux(...)

37
external/llvm/test/CodeGen/ARM/2007-05-23-BadPreIndexedStore.ll vendored Normal file
View File

@@ -0,0 +1,37 @@
; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
%struct.shape_edge_t = type { %struct.shape_edge_t*, %struct.shape_edge_t*, i32, i32, i32, i32 }
%struct.shape_path_t = type { %struct.shape_edge_t*, %struct.shape_edge_t*, i32, i32, i32, i32, i32, i32 }
%struct.shape_pool_t = type { i8* (%struct.shape_pool_t*, i8*, i32)*, i8* (%struct.shape_pool_t*, i32)*, void (%struct.shape_pool_t*, i8*)* }
define %struct.shape_path_t* @shape_path_alloc(%struct.shape_pool_t* %pool, i32* %shape) {
entry:
br i1 false, label %cond_false, label %bb45
bb45: ; preds = %entry
ret %struct.shape_path_t* null
cond_false: ; preds = %entry
br i1 false, label %bb140, label %bb174
bb140: ; preds = %bb140, %cond_false
%indvar = phi i32 [ 0, %cond_false ], [ %indvar.next, %bb140 ] ; <i32> [#uses=2]
%edge.230.0.rec = shl i32 %indvar, 1 ; <i32> [#uses=3]
%edge.230.0 = getelementptr %struct.shape_edge_t, %struct.shape_edge_t* null, i32 %edge.230.0.rec ; <%struct.shape_edge_t*> [#uses=1]
%edge.230.0.sum6970 = or i32 %edge.230.0.rec, 1 ; <i32> [#uses=2]
%tmp154 = getelementptr %struct.shape_edge_t, %struct.shape_edge_t* null, i32 %edge.230.0.sum6970 ; <%struct.shape_edge_t*> [#uses=1]
%tmp11.i5 = getelementptr %struct.shape_edge_t, %struct.shape_edge_t* null, i32 %edge.230.0.sum6970, i32 0 ; <%struct.shape_edge_t**> [#uses=1]
store %struct.shape_edge_t* %edge.230.0, %struct.shape_edge_t** %tmp11.i5
store %struct.shape_edge_t* %tmp154, %struct.shape_edge_t** null
%tmp16254.0.rec = add i32 %edge.230.0.rec, 2 ; <i32> [#uses=1]
%xp.350.sum = add i32 0, %tmp16254.0.rec ; <i32> [#uses=1]
%tmp168 = icmp slt i32 %xp.350.sum, 0 ; <i1> [#uses=1]
%indvar.next = add i32 %indvar, 1 ; <i32> [#uses=1]
br i1 %tmp168, label %bb140, label %bb174
bb174: ; preds = %bb140, %cond_false
ret %struct.shape_path_t* null
}
; CHECK-NOT: str{{.*}}!

106
external/llvm/test/CodeGen/ARM/2007-08-15-ReuseBug.ll vendored Normal file
View File

@@ -0,0 +1,106 @@
; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic -mattr=+v6
; PR1609
%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
%struct.__sFILEX = type opaque
%struct.__sbuf = type { i8*, i32 }
@_C_nextcmd = external global i32 ; <i32*> [#uses=2]
@_C_cmds = external global [100 x i8*] ; <[100 x i8*]*> [#uses=2]
@.str44 = external constant [2 x i8] ; <[2 x i8]*> [#uses=1]
define i32 @main(i32 %argc, i8** %argv) {
entry:
br label %cond_next212.i
bb21.i: ; preds = %cond_next212.i
br label %cond_next212.i
bb24.i: ; preds = %cond_next212.i
ret i32 0
bb27.i: ; preds = %cond_next212.i
ret i32 0
bb30.i: ; preds = %cond_next212.i
%tmp205399.i = add i32 %argc_addr.2358.0.i, -1 ; <i32> [#uses=1]
br label %cond_next212.i
bb33.i: ; preds = %cond_next212.i
ret i32 0
cond_next73.i: ; preds = %cond_next212.i
ret i32 0
bb75.i: ; preds = %cond_next212.i
ret i32 0
bb77.i: ; preds = %cond_next212.i
ret i32 0
bb79.i: ; preds = %cond_next212.i
ret i32 0
bb102.i: ; preds = %cond_next212.i
br i1 false, label %cond_true110.i, label %cond_next123.i
cond_true110.i: ; preds = %bb102.i
%tmp116.i = getelementptr i8*, i8** %argv_addr.2321.0.i, i32 2 ; <i8**> [#uses=1]
%tmp117.i = load i8*, i8** %tmp116.i ; <i8*> [#uses=1]
%tmp126425.i = call %struct.FILE* @fopen( i8* %tmp117.i, i8* getelementptr ([2 x i8], [2 x i8]* @.str44, i32 0, i32 0) ) ; <%struct.FILE*> [#uses=0]
ret i32 0
cond_next123.i: ; preds = %bb102.i
%tmp122.i = getelementptr i8, i8* %tmp215.i, i32 2 ; <i8*> [#uses=0]
ret i32 0
bb162.i: ; preds = %cond_next212.i
ret i32 0
C_addcmd.exit120.i: ; preds = %cond_next212.i
%tmp3.i.i.i.i105.i = call i8* @calloc( i32 15, i32 1 ) ; <i8*> [#uses=1]
%tmp1.i108.i = getelementptr [100 x i8*], [100 x i8*]* @_C_cmds, i32 0, i32 0 ; <i8**> [#uses=1]
store i8* %tmp3.i.i.i.i105.i, i8** %tmp1.i108.i, align 4
%tmp.i91.i = load i32, i32* @_C_nextcmd, align 4 ; <i32> [#uses=1]
store i32 0, i32* @_C_nextcmd, align 4
%tmp3.i.i.i.i95.i = call i8* @calloc( i32 15, i32 1 ) ; <i8*> [#uses=1]
%tmp1.i98.i = getelementptr [100 x i8*], [100 x i8*]* @_C_cmds, i32 0, i32 %tmp.i91.i ; <i8**> [#uses=1]
store i8* %tmp3.i.i.i.i95.i, i8** %tmp1.i98.i, align 4
br label %cond_next212.i
bb174.i: ; preds = %cond_next212.i
ret i32 0
bb192.i: ; preds = %cond_next212.i
br label %cond_next212.i
cond_next212.i: ; preds = %cond_next212.i, %cond_next212.i, %cond_next212.i, %cond_next212.i, %bb192.i, %C_addcmd.exit120.i, %bb30.i, %bb21.i, %entry
%max_d.3 = phi i32 [ -1, %entry ], [ %max_d.3, %bb30.i ], [ %max_d.3, %bb21.i ], [ %max_d.3, %C_addcmd.exit120.i ], [ 0, %bb192.i ], [ %max_d.3, %cond_next212.i ], [ %max_d.3, %cond_next212.i ], [ %max_d.3, %cond_next212.i ], [ %max_d.3, %cond_next212.i ] ; <i32> [#uses=7]
%argv_addr.2321.0.i = phi i8** [ %argv, %entry ], [ %tmp214.i, %bb192.i ], [ %tmp214.i, %C_addcmd.exit120.i ], [ %tmp214.i, %bb30.i ], [ %tmp214.i, %bb21.i ], [ %tmp214.i, %cond_next212.i ], [ %tmp214.i, %cond_next212.i ], [ %tmp214.i, %cond_next212.i ], [ %tmp214.i, %cond_next212.i ] ; <i8**> [#uses=2]
%argc_addr.2358.0.i = phi i32 [ %argc, %entry ], [ %tmp205399.i, %bb30.i ], [ 0, %bb21.i ], [ 0, %C_addcmd.exit120.i ], [ 0, %bb192.i ], [ 0, %cond_next212.i ], [ 0, %cond_next212.i ], [ 0, %cond_next212.i ], [ 0, %cond_next212.i ] ; <i32> [#uses=1]
%tmp214.i = getelementptr i8*, i8** %argv_addr.2321.0.i, i32 1 ; <i8**> [#uses=9]
%tmp215.i = load i8*, i8** %tmp214.i ; <i8*> [#uses=1]
%tmp1314.i = sext i8 0 to i32 ; <i32> [#uses=1]
switch i32 %tmp1314.i, label %bb192.i [
i32 76, label %C_addcmd.exit120.i
i32 77, label %bb174.i
i32 83, label %bb162.i
i32 97, label %bb33.i
i32 98, label %bb21.i
i32 99, label %bb24.i
i32 100, label %bb27.i
i32 101, label %cond_next212.i
i32 102, label %bb102.i
i32 105, label %bb75.i
i32 109, label %bb30.i
i32 113, label %cond_next212.i
i32 114, label %cond_next73.i
i32 115, label %bb79.i
i32 116, label %cond_next212.i
i32 118, label %bb77.i
i32 119, label %cond_next212.i
]
}
declare %struct.FILE* @fopen(i8*, i8*)
declare i8* @calloc(i32, i32)

19
external/llvm/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll vendored Normal file
View File

@@ -0,0 +1,19 @@
; RUN: llc < %s -mtriple=arm-linux-gnueabi -regalloc=fast -optimize-regalloc=0
; PR1925
%struct.encode_aux_nearestmatch = type { i32*, i32*, i32*, i32*, i32, i32 }
%struct.encode_aux_pigeonhole = type { float, float, i32, i32, i32*, i32, i32*, i32*, i32* }
%struct.encode_aux_threshmatch = type { float*, i32*, i32, i32 }
%struct.oggpack_buffer = type { i32, i32, i8*, i8*, i32 }
%struct.static_codebook = type { i32, i32, i32*, i32, i32, i32, i32, i32, i32*, %struct.encode_aux_nearestmatch*, %struct.encode_aux_threshmatch*, %struct.encode_aux_pigeonhole*, i32 }
define i32 @vorbis_staticbook_pack(%struct.static_codebook* %c, %struct.oggpack_buffer* %opb) {
entry:
%opb_addr = alloca %struct.oggpack_buffer* ; <%struct.oggpack_buffer**> [#uses=1]
%tmp1 = load %struct.oggpack_buffer*, %struct.oggpack_buffer** %opb_addr, align 4 ; <%struct.oggpack_buffer*> [#uses=1]
call void @oggpack_write( %struct.oggpack_buffer* %tmp1, i32 5653314, i32 24 ) nounwind
call void @oggpack_write( %struct.oggpack_buffer* null, i32 0, i32 24 ) nounwind
unreachable
}
declare void @oggpack_write(%struct.oggpack_buffer*, i32, i32)

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