Imported Upstream version 6.0.0.172

Former-commit-id: f3cc9b82f3e5bd8f0fd3ebc098f789556b44e9cd

external/llvm/test/CodeGen/ARC/alu.ll

@@ -0,0 +1,255 @@
+; RUN: llc -march=arc < %s | FileCheck %s
+
+; CHECK-LABEL: add_r
+; CHECK: add %r0, %r{{[01]}}, %r{{[01]}}
+define i32 @add_r(i32 %a, i32 %b) nounwind {
+entry:
+  %v = add i32 %a, %b
+  ret i32 %v
+}
+
+; CHECK-LABEL: add_u6
+; CHECK: add %r0, %r0, 15
+define i32 @add_u6(i32 %a) nounwind {
+  %v = add i32 %a, 15
+  ret i32 %v
+}
+
+; CHECK-LABEL: add_limm
+; CHECK: add %r0, %r0, 12345
+define i32 @add_limm(i32 %a) nounwind {
+  %v = add i32 %a, 12345
+  ret i32 %v
+}
+
+; CHECK-LABEL: mpy_r
+; CHECK: mpy %r0, %r{{[01]}}, %r{{[01]}}
+define i32 @mpy_r(i32 %a, i32 %b) nounwind {
+entry:
+  %v = mul i32 %a, %b
+  ret i32 %v
+}
+
+; CHECK-LABEL: mpy_u6
+; CHECK: mpy %r0, %r0, 10
+define i32 @mpy_u6(i32 %a) nounwind {
+  %v = mul i32 %a, 10
+  ret i32 %v
+}
+
+; CHECK-LABEL: mpy_limm
+; CHECK: mpy %r0, %r0, 12345
+define i32 @mpy_limm(i32 %a) nounwind {
+  %v = mul i32 %a, 12345
+  ret i32 %v
+}
+
+; CHECK-LABEL: max_r
+; CHECK: max %r0, %r{{[01]}}, %r{{[01]}}
+define i32 @max_r(i32 %a, i32 %b) nounwind {
+  %i = icmp sgt i32 %a, %b
+  %v = select i1 %i, i32 %a, i32 %b
+  ret i32 %v
+}
+
+; CHECK-LABEL: max_u6
+; CHECK: max %r0, %r0, 12
+define i32 @max_u6(i32 %a) nounwind {
+  %i = icmp sgt i32 %a, 12
+  %v = select i1 %i, i32 %a, i32 12
+  ret i32 %v
+}
+
+; CHECK-LABEL: max_limm
+; CHECK: max %r0, %r0, 2345
+define i32 @max_limm(i32 %a) nounwind {
+  %i = icmp sgt i32 %a, 2345
+  %v = select i1 %i, i32 %a, i32 2345
+  ret i32 %v
+}
+
+; CHECK-LABEL: min_r
+; CHECK: min %r0, %r{{[01]}}, %r{{[01]}}
+define i32 @min_r(i32 %a, i32 %b) nounwind {
+  %i = icmp slt i32 %a, %b
+  %v = select i1 %i, i32 %a, i32 %b
+  ret i32 %v
+}
+
+; CHECK-LABEL: min_u6
+; CHECK: min %r0, %r0, 20
+define i32 @min_u6(i32 %a) nounwind {
+  %i = icmp slt i32 %a, 20
+  %v = select i1 %i, i32 %a, i32 20
+  ret i32 %v
+}
+
+; CHECK-LABEL: min_limm
+; CHECK: min %r0, %r0, 2040
+define i32 @min_limm(i32 %a) nounwind {
+  %i = icmp slt i32 %a, 2040
+  %v = select i1 %i, i32 %a, i32 2040
+  ret i32 %v
+}
+
+; CHECK-LABEL: and_r
+; CHECK: and %r0, %r{{[01]}}, %r{{[01]}}
+define i32 @and_r(i32 %a, i32 %b) nounwind {
+  %v = and i32 %a, %b
+  ret i32 %v
+}
+
+; CHECK-LABEL: and_u6
+; CHECK: and %r0, %r0, 7
+define i32 @and_u6(i32 %a) nounwind {
+  %v = and i32 %a, 7
+  ret i32 %v
+}
+
+; 0xfffff == 1048575
+; CHECK-LABEL: and_limm
+; CHECK: and %r0, %r0, 1048575 
+define i32 @and_limm(i32 %a) nounwind {
+  %v = and i32 %a, 1048575
+  ret i32 %v
+}
+
+; CHECK-LABEL: or_r
+; CHECK: or %r0, %r{{[01]}}, %r{{[01]}}
+define i32 @or_r(i32 %a, i32 %b) nounwind {
+  %v = or i32 %a, %b
+  ret i32 %v
+}
+
+; CHECK-LABEL: or_u6
+; CHECK: or %r0, %r0, 7
+define i32 @or_u6(i32 %a) nounwind {
+  %v = or i32 %a, 7
+  ret i32 %v
+}
+
+; 0xf0f0f == 986895
+; CHECK-LABEL: or_limm
+define i32 @or_limm(i32 %a) nounwind {
+  %v = or i32 %a, 986895
+  ret i32 %v
+}
+
+; CHECK-LABEL: xor_r
+; CHECK: xor %r0, %r{{[01]}}, %r{{[01]}}
+define i32 @xor_r(i32 %a, i32 %b) nounwind {
+  %v = xor i32 %a, %b
+  ret i32 %v
+}
+
+; CHECK-LABEL: xor_u6
+; CHECK: xor %r0, %r0, 3
+define i32 @xor_u6(i32 %a) nounwind {
+  %v = xor i32 %a, 3
+  ret i32 %v
+}
+
+; CHECK-LABEL: xor_limm
+; CHECK: xor %r0, %r0, 986895
+define i32 @xor_limm(i32 %a) nounwind {
+  %v = xor i32 %a, 986895
+  ret i32 %v
+}
+
+; CHECK-LABEL: asl_r
+; CHECK: asl %r0, %r{{[01]}}, %r{{[01]}}
+define i32 @asl_r(i32 %a, i32 %b) nounwind {
+  %v = shl i32 %a, %b
+  ret i32 %v
+}
+
+; CHECK-LABEL: asl_u6
+; CHECK: asl %r0, %r0, 4
+define i32 @asl_u6(i32 %a) nounwind {
+  %v = shl i32 %a, 4
+  ret i32 %v
+}
+
+; CHECK-LABEL: lsr_r
+; CHECK: lsr %r0, %r{{[01]}}, %r{{[01]}}
+define i32 @lsr_r(i32 %a, i32 %b) nounwind {
+  %v = lshr i32 %a, %b
+  ret i32 %v
+}
+
+; CHECK-LABEL: lsr_u6
+; CHECK: lsr %r0, %r0, 6
+define i32 @lsr_u6(i32 %a) nounwind {
+  %v = lshr i32 %a, 6
+  ret i32 %v
+}
+
+; CHECK-LABEL: asr_r
+; CHECK: asr %r0, %r{{[01]}}, %r{{[01]}}
+define i32 @asr_r(i32 %a, i32 %b) nounwind {
+  %v = ashr i32 %a, %b
+  ret i32 %v
+}
+
+; CHECK-LABEL: asr_u6
+; CHECK: asr %r0, %r0, 8
+define i32 @asr_u6(i32 %a) nounwind {
+  %v = ashr i32 %a, 8
+  ret i32 %v
+}
+
+; CHECK-LABEL: ror_r
+; CHECK: ror %r0, %r{{[01]}}, %r{{[01]}}
+define i32 @ror_r(i32 %a, i32 %b) nounwind {
+  %v1 = lshr i32 %a, %b
+  %ls = sub i32 32, %b
+  %v2 = shl i32 %a, %ls
+  %v = or i32 %v1, %v2
+  ret i32 %v
+}
+
+; CHECK-LABEL: ror_u6
+; CHECK: ror %r0, %r0, 10
+define i32 @ror_u6(i32 %a) nounwind {
+  %v1 = lshr i32 %a, 10
+  %v2 = shl i32 %a, 22
+  %v = or i32 %v1, %v2
+  ret i32 %v
+}
+
+; CHECK-LABEL: sexh_r
+; CHECK: sexh %r0, %r0
+define i32 @sexh_r(i32 %a) nounwind {
+  %v1 = shl i32 %a, 16
+  %v = ashr i32 %v1, 16
+  ret i32 %v
+}
+
+; CHECK-LABEL: sexb_r
+; CHECK: sexb %r0, %r0
+define i32 @sexb_r(i32 %a) nounwind {
+  %v1 = shl i32 %a, 24
+  %v = ashr i32 %v1, 24
+  ret i32 %v
+}
+
+; CHECK-LABEL: mulu64
+; CHECK-DAG: mpy %r[[REG:[0-9]+]], %r{{[01]}}, %r{{[01]}}
+; CHECK-DAG: mpymu %r[[REG:[0-9]+]], %r{{[01]}}, %r{{[01]}}
+define i64 @mulu64(i32 %a, i32 %b) nounwind {
+  %a64 = zext i32 %a to i64
+  %b64 = zext i32 %b to i64
+  %v = mul i64 %a64, %b64
+  ret i64 %v
+}
+
+; CHECK-LABEL: muls64
+; CHECK-DAG: mpy %r[[REG:[0-9]+]], %r{{[01]}}, %r{{[01]}}
+; CHECK-DAG: mpym %r[[REG:[0-9]+]], %r{{[01]}}, %r{{[01]}}
+define i64 @muls64(i32 %a, i32 %b) nounwind {
+  %a64 = sext i32 %a to i64
+  %b64 = sext i32 %b to i64
+  %v = mul i64 %a64, %b64
+  ret i64 %v
+}
+

external/llvm/test/CodeGen/ARC/brcc.ll

@@ -0,0 +1,37 @@
+; RUN: llc -march=arc < %s | FileCheck %s
+
+; CHECK-LABEL: brcc1
+; CHECK: brne %r0, %r1
+define i32 @brcc1(i32 %a, i32 %b) nounwind {
+entry:
+  %wb = icmp eq i32 %a, %b
+  br i1 %wb, label %t1, label %t2
+t1:
+  %t1v = add i32 %a, 4
+  br label %exit
+t2:
+  %t2v = add i32 %b, 8
+  br label %exit
+exit:
+  %v = phi i32 [ %t1v, %t1 ], [ %t2v, %t2 ]
+  ret i32 %v
+}
+
+; CHECK-LABEL: brcc2
+; CHECK: breq %r0, %r1
+define i32 @brcc2(i32 %a, i32 %b) nounwind {
+entry:
+  %wb = icmp ne i32 %a, %b
+  br i1 %wb, label %t1, label %t2
+t1:
+  %t1v = add i32 %a, 4
+  br label %exit
+t2:
+  %t2v = add i32 %b, 8
+  br label %exit
+exit:
+  %v = phi i32 [ %t1v, %t1 ], [ %t2v, %t2 ]
+  ret i32 %v
+}
+
+

external/llvm/test/CodeGen/ARC/call.ll

@@ -0,0 +1,88 @@
+; RUN: llc -march=arc < %s | FileCheck %s
+
+
+declare i32 @goo1(i32) nounwind
+
+; CHECK-LABEL: call1
+; CHECK: bl @goo1
+define i32 @call1(i32 %a) nounwind {
+entry:
+  %x = call i32 @goo1(i32 %a)
+  ret i32 %x
+}
+
+declare i32 @goo2(i32, i32, i32, i32, i32, i32, i32, i32) nounwind
+
+; CHECK-LABEL: call2
+; CHECK-DAG: mov %r0, 0
+; CHECK-DAG: mov %r1, 1
+; CHECK-DAG: mov %r2, 2
+; CHECK-DAG: mov %r3, 3
+; CHECK-DAG: mov %r4, 4
+; CHECK-DAG: mov %r5, 5
+; CHECK-DAG: mov %r6, 6
+; CHECK-DAG: mov %r7, 7
+; CHECK: bl @goo2
+define i32 @call2() nounwind {
+entry:
+  %x = call i32 @goo2(i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7)
+  ret i32 %x
+}
+
+declare i32 @goo3(i64, i32, i64) nounwind
+; call goo3(0xEEEEEEEE77777777, 0x55555555, 0xAAAAAAAA33333333)
+; 0xEEEEEEEE == -286331154
+; 0x77777777 == 2004318071
+; 0x55555555 == 1431655765
+; 0xAAAAAAAA == -1431655766
+; 0x33333333 == 858993459
+; CHECK-LABEL: call3
+; CHECK-DAG: mov %r0, 2004318071
+; CHECK-DAG: mov %r1, -286331154
+; CHECK-DAG: mov %r2, 1431655765
+; CHECK-DAG: mov %r3, 858993459
+; CHECK-DAG: mov %r4, -1431655766
+; CHECK: bl @goo3
+define i32 @call3() nounwind {
+entry:
+  %x = call i32 @goo3(i64 17216961133457930103,
+                      i32 1431655765,
+                      i64 12297829380468716339)
+  ret i32 %x
+}
+
+declare i64 @goo4()
+
+; 64-bit values are returned in r0r1
+; CHECK-LABEL: call4
+; CHECK: bl @goo4
+; CHECK: lsr %r0, %r1, 16
+define i32 @call4() nounwind {
+  %x = call i64 @goo4()
+  %v1 = lshr i64 %x, 48
+  %v = trunc i64 %v1 to i32
+  ret i32 %v
+}
+
+; 0x0000ffff00ff00ff=281470698455295
+; returned as r0=0x00ff00ff=16711935, r1=0x0000ffff=65535
+; CHECK-LABEL: ret1
+; CHECK-DAG: mov %r1, 65535
+; CHECK-DAG: mov %r0, 16711935
+define i64 @ret1() nounwind {
+  ret i64 281470698455295
+}
+
+@funcptr = external global i32 (i32)*, align 4
+; Indirect calls use JL
+; CHECK-LABEL: call_indirect
+; CHECK-DAG: ld %r[[REG:[0-9]+]], [@funcptr]
+; CHECK-DAG: mov %r0, 12
+; CHECK:     jl [%r[[REG]]]
+define i32 @call_indirect(i32 %x) nounwind {
+  %f = load i32 (i32)*, i32 (i32)** @funcptr, align 4
+  %call = call i32 %f(i32 12)
+  %add = add nsw i32 %call, %x
+  ret i32 %add
+}
+

external/llvm/test/CodeGen/ARC/ldst.ll

@@ -0,0 +1,272 @@
+; RUN: llc -march=arc < %s | FileCheck %s
+
+; CHECK-LABEL: load32
+; CHECK: ld %r0, [%r0,16000]
+
+define i32 @load32(i32* %bp) nounwind {
+entry:
+  %gep = getelementptr i32, i32* %bp, i32 4000
+  %v = load i32, i32* %gep, align 4
+  ret i32 %v
+}
+
+; CHECK-LABEL: load16
+; CHECK: ldh %r0, [%r0,8000]
+
+define i16 @load16(i16* %bp) nounwind {
+entry:
+  %gep = getelementptr i16, i16* %bp, i32 4000
+  %v = load i16, i16* %gep, align 2
+  ret i16 %v
+}
+
+; CHECK-LABEL: load8
+; CHECK: ldb %r0, [%r0,4000]
+
+define i8 @load8(i8* %bp) nounwind {
+entry:
+  %gep = getelementptr i8, i8* %bp, i32 4000
+  %v = load i8, i8* %gep, align 1
+  ret i8 %v
+}
+
+; CHECK-LABEL: sextload16
+; CHECK: ldh.x %r0, [%r0,8000]
+
+define i32 @sextload16(i16* %bp) nounwind {
+entry:
+  %gep = getelementptr i16, i16* %bp, i32 4000
+  %vl = load i16, i16* %gep, align 2
+  %v = sext i16 %vl to i32
+  ret i32 %v
+}
+
+; CHECK-LABEL: sextload8
+; CHECK: ldb.x %r0, [%r0,4000]
+
+define i32 @sextload8(i8* %bp) nounwind {
+entry:
+  %gep = getelementptr i8, i8* %bp, i32 4000
+  %vl = load i8, i8* %gep, align 1
+  %v = sext i8 %vl to i32
+  ret i32 %v
+}
+
+; CHECK-LABEL: s_sextload16
+; CHECK: ldh.x %r0, [%r0,32]
+
+define i32 @s_sextload16(i16* %bp) nounwind {
+entry:
+  %gep = getelementptr i16, i16* %bp, i32 16
+  %vl = load i16, i16* %gep, align 2
+  %v = sext i16 %vl to i32
+  ret i32 %v
+}
+
+; CHECK-LABEL: s_sextload8
+; CHECK: ldb.x %r0, [%r0,16]
+
+define i32 @s_sextload8(i8* %bp) nounwind {
+entry:
+  %gep = getelementptr i8, i8* %bp, i32 16
+  %vl = load i8, i8* %gep, align 1
+  %v = sext i8 %vl to i32
+  ret i32 %v
+}
+
+; CHECK-LABEL: store32
+; CHECK: add %r[[REG:[0-9]+]], %r1, 16000
+; CHECK: st %r0, [%r[[REG]],0]
+
+; Long range stores (offset does not fit in s9) must be add followed by st.
+define void @store32(i32 %val, i32* %bp) nounwind {
+entry:
+  %gep = getelementptr i32, i32* %bp, i32 4000
+  store i32 %val, i32* %gep, align 4
+  ret void
+}
+
+; CHECK-LABEL: store16
+; CHECK: add %r[[REG:[0-9]+]], %r1, 8000
+; CHECK: sth %r0, [%r[[REG]],0]
+
+define void @store16(i16 zeroext %val, i16* %bp) nounwind {
+entry:
+  %gep = getelementptr i16, i16* %bp, i32 4000
+  store i16 %val, i16* %gep, align 2
+  ret void
+}
+
+; CHECK-LABEL: store8
+; CHECK: add %r[[REG:[0-9]+]], %r1, 4000
+; CHECK: stb %r0, [%r[[REG]],0]
+
+define void @store8(i8 zeroext %val, i8* %bp) nounwind {
+entry:
+  %gep = getelementptr i8, i8* %bp, i32 4000
+  store i8 %val, i8* %gep, align 1
+  ret void
+}
+
+; Short range stores can be done with [reg, s9].
+; CHECK-LABEL: s_store32
+; CHECK-NOT: add
+; CHECK: st %r0, [%r1,64]
+define void @s_store32(i32 %val, i32* %bp) nounwind {
+entry:
+  %gep = getelementptr i32, i32* %bp, i32 16
+  store i32 %val, i32* %gep, align 4
+  ret void
+}
+
+; CHECK-LABEL: s_store16
+; CHECK-NOT: add
+; CHECK: sth %r0, [%r1,32]
+define void @s_store16(i16 zeroext %val, i16* %bp) nounwind {
+entry:
+  %gep = getelementptr i16, i16* %bp, i32 16
+  store i16 %val, i16* %gep, align 2
+  ret void
+}
+
+; CHECK-LABEL: s_store8
+; CHECK-NOT: add
+; CHECK: stb %r0, [%r1,16]
+define void @s_store8(i8 zeroext %val, i8* %bp) nounwind {
+entry:
+  %gep = getelementptr i8, i8* %bp, i32 16
+  store i8 %val, i8* %gep, align 1
+  ret void
+}
+
+
+@aaaa = internal global [128 x i32] zeroinitializer
+@bbbb = internal global [128 x i16] zeroinitializer
+@cccc = internal global [128 x i8]  zeroinitializer
+
+; CHECK-LABEL: g_store32
+; CHECK-NOT: add
+; CHECK: st %r0, [@aaaa+64]
+define void @g_store32(i32 %val) nounwind {
+entry:
+  store i32 %val, i32* getelementptr inbounds ([128 x i32], [128 x i32]* @aaaa, i32 0, i32 16), align 4
+  ret void
+}
+
+; CHECK-LABEL: g_load32
+; CHECK-NOT: add
+; CHECK: ld %r0, [@aaaa+64]
+define i32 @g_load32() nounwind {
+  %gep = getelementptr inbounds [128 x i32], [128 x i32]* @aaaa, i32 0, i32 16
+  %v = load i32, i32* %gep, align 4
+  ret i32 %v
+}
+
+; CHECK-LABEL: g_store16
+; CHECK-NOT: add
+; CHECK: sth %r0, [@bbbb+32]
+define void @g_store16(i16 %val) nounwind {
+entry:
+  store i16 %val, i16* getelementptr inbounds ([128 x i16], [128 x i16]* @bbbb, i16 0, i16 16), align 2
+  ret void
+}
+
+; CHECK-LABEL: g_load16
+; CHECK-NOT: add
+; CHECK: ldh %r0, [@bbbb+32]
+define i16 @g_load16() nounwind {
+  %gep = getelementptr inbounds [128 x i16], [128 x i16]* @bbbb, i16 0, i16 16
+  %v = load i16, i16* %gep, align 2
+  ret i16 %v
+}
+
+; CHECK-LABEL: g_store8
+; CHECK-NOT: add
+; CHECK: stb %r0, [@cccc+16]
+define void @g_store8(i8 %val) nounwind {
+entry:
+  store i8 %val, i8* getelementptr inbounds ([128 x i8], [128 x i8]* @cccc, i8 0, i8 16), align 1
+  ret void
+}
+
+; CHECK-LABEL: g_load8
+; CHECK-NOT: add
+; CHECK: ldb %r0, [@cccc+16]
+define i8 @g_load8() nounwind {
+  %gep = getelementptr inbounds [128 x i8], [128 x i8]* @cccc, i8 0, i8 16
+  %v = load i8, i8* %gep, align 1
+  ret i8 %v
+}
+
+; CHECK-LABEL: align2_load32
+; CHECK-DAG: ldh %r[[REG0:[0-9]+]], [%r0,0]
+; CHECK-DAG: ldh %r[[REG1:[0-9]+]], [%r0,2]
+; CHECK-DAG: asl %r[[REG2:[0-9]+]], %r[[REG1]], 16
+define i32 @align2_load32(i8* %p) nounwind {
+entry:
+  %bp = bitcast i8* %p to i32*
+  %v = load i32, i32* %bp, align 2
+  ret i32 %v
+}
+
+; CHECK-LABEL: align1_load32
+; CHECK-DAG: ldb %r[[REG0:[0-9]+]], [%r0,0]
+; CHECK-DAG: ldb %r[[REG1:[0-9]+]], [%r0,1]
+; CHECK-DAG: ldb %r[[REG2:[0-9]+]], [%r0,2]
+; CHECK-DAG: ldb %r[[REG3:[0-9]+]], [%r0,3]
+; CHECK-DAG: asl %r[[AREG1:[0-9]+]], %r[[REG1]], 8
+; CHECK-DAG: asl %r[[AREG3:[0-9]+]], %r[[REG3]], 8
+define i32 @align1_load32(i8* %p) nounwind {
+entry:
+  %bp = bitcast i8* %p to i32*
+  %v = load i32, i32* %bp, align 1
+  ret i32 %v
+}
+
+; CHECK-LABEL: align1_load16
+; CHECK-DAG: ldb %r[[REG0:[0-9]+]], [%r0,0]
+; CHECK-DAG: ldb %r[[REG1:[0-9]+]], [%r0,1]
+; CHECK-DAG: asl %r[[REG2:[0-9]+]], %r[[REG1]], 8
+define i16 @align1_load16(i8* %p) nounwind {
+entry:
+  %bp = bitcast i8* %p to i16*
+  %v = load i16, i16* %bp, align 1
+  ret i16 %v
+}
+
+; CHECK-LABEL: align2_store32
+; CHECK-DAG: lsr %r[[REG:[0-9]+]], %r1, 16
+; CHECK-DAG: sth %r1, [%r0,0]
+; CHECK-DAG: sth %r[[REG:[0-9]+]], [%r0,2]
+define void @align2_store32(i8* %p, i32 %v) nounwind {
+entry:
+  %bp = bitcast i8* %p to i32*
+  store i32 %v, i32* %bp, align 2
+  ret void
+}
+
+; CHECK-LABEL: align1_store16
+; CHECK-DAG: lsr %r[[REG:[0-9]+]], %r1, 8
+; CHECK-DAG: stb %r1, [%r0,0]
+; CHECK-DAG: stb %r[[REG:[0-9]+]], [%r0,1]
+define void @align1_store16(i8* %p, i16 %v) nounwind {
+entry:
+  %bp = bitcast i8* %p to i16*
+  store i16 %v, i16* %bp, align 1
+  ret void
+}
+
+; CHECK-LABEL: align1_store32
+; CHECK-DAG: lsr %r[[REG0:[0-9]+]], %r1, 8
+; CHECK-DAG: lsr %r[[REG1:[0-9]+]], %r1, 16
+; CHECK-DAG: lsr %r[[REG2:[0-9]+]], %r1, 24
+; CHECK-DAG: stb %r1, [%r0,0]
+; CHECK-DAG: stb %r[[REG0]], [%r0,1]
+; CHECK-DAG: stb %r[[REG1]], [%r0,2]
+; CHECK-DAG: stb %r[[REG2]], [%r0,3]
+define void @align1_store32(i8* %p, i32 %v) nounwind {
+entry:
+  %bp = bitcast i8* %p to i32*
+  store i32 %v, i32* %bp, align 1
+  ret void
+}

external/llvm/test/CodeGen/ARC/lit.local.cfg

@@ -0,0 +1,3 @@
+if not 'ARC' in config.root.targets:
+    config.unsupported = True
+