Imported Upstream version 6.10.0.49

Former-commit-id: 1d6753294b2993e1fbf92de9366bb9544db4189b

external/llvm-project/llvm/test/MC/Hexagon/PacketRules/endloop_branches.s

@@ -0,0 +1,17 @@
+# RUN: not llvm-mc -triple=hexagon -filetype=asm %s 2>&1 | FileCheck %s
+
+{ jump unknown
+}:endloop0
+# CHECK: 4:1: error: Branches cannot be in a packet with hardware loops
+
+{ jump unknown
+}:endloop1
+# CHECK: 8:1: error: Branches cannot be in a packet with hardware loops
+
+{ call unknown
+}:endloop0
+# CHECK: 12:1: error: Branches cannot be in a packet with hardware loops
+
+{ dealloc_return
+}:endloop0
+# CHECK: 16:1: error: Branches cannot be in a packet with hardware loops

external/llvm-project/llvm/test/MC/Hexagon/PacketRules/registers_readonly.s

@@ -0,0 +1,5 @@
+# RUN: not llvm-mc -arch=hexagon -filetype=obj %s 2>&1 | FileCheck %s
+
+# CHECK: 4:3: error: Cannot write to read-only register `PC'
+{ pc = r0
+  r0 = r0 }

external/llvm-project/llvm/test/MC/Hexagon/PacketRules/restrict_ax.s

@@ -0,0 +1,4 @@
+{ r0=memw_locked(r0)
+  r1=-mpyi(r0,#0) }
+# RUN: not llvm-mc -arch=hexagon -filetype=asm %s 2>%t; FileCheck %s --check-prefix=CHECK00 <%t
+# CHECK00: 1:3: error: Instruction can only be in a packet with ALU or non-FPU XTYPE instructions

external/llvm-project/llvm/test/MC/Hexagon/PacketRules/solo.s

@@ -0,0 +1,5 @@
+# RUN: not llvm-mc -arch=hexagon -filetype=asm %s 2>%t; FileCheck %s <%t
+
+{ brkpt
+  r0 = r0 }
+# CHECK: 3:3: error: Instruction is marked `isSolo' and cannot have other instructions in the same packet