Imported Upstream version 6.10.0.49

Former-commit-id: 1d6753294b2993e1fbf92de9366bb9544db4189b

external/llvm-project/llvm/test/MC/Hexagon/PacketRules/endloop_branches.s

@@ -0,0 +1,17 @@
+# RUN: not llvm-mc -triple=hexagon -filetype=asm %s 2>&1 | FileCheck %s
+
+{ jump unknown
+}:endloop0
+# CHECK: 4:1: error: Branches cannot be in a packet with hardware loops
+
+{ jump unknown
+}:endloop1
+# CHECK: 8:1: error: Branches cannot be in a packet with hardware loops
+
+{ call unknown
+}:endloop0
+# CHECK: 12:1: error: Branches cannot be in a packet with hardware loops
+
+{ dealloc_return
+}:endloop0
+# CHECK: 16:1: error: Branches cannot be in a packet with hardware loops

external/llvm-project/llvm/test/MC/Hexagon/PacketRules/registers_readonly.s

@@ -0,0 +1,5 @@
+# RUN: not llvm-mc -arch=hexagon -filetype=obj %s 2>&1 | FileCheck %s
+
+# CHECK: 4:3: error: Cannot write to read-only register `PC'
+{ pc = r0
+  r0 = r0 }

external/llvm-project/llvm/test/MC/Hexagon/PacketRules/restrict_ax.s

@@ -0,0 +1,4 @@
+{ r0=memw_locked(r0)
+  r1=-mpyi(r0,#0) }
+# RUN: not llvm-mc -arch=hexagon -filetype=asm %s 2>%t; FileCheck %s --check-prefix=CHECK00 <%t
+# CHECK00: 1:3: error: Instruction can only be in a packet with ALU or non-FPU XTYPE instructions

external/llvm-project/llvm/test/MC/Hexagon/PacketRules/solo.s

@@ -0,0 +1,5 @@
+# RUN: not llvm-mc -arch=hexagon -filetype=asm %s 2>%t; FileCheck %s <%t
+
+{ brkpt
+  r0 = r0 }
+# CHECK: 3:3: error: Instruction is marked `isSolo' and cannot have other instructions in the same packet

external/llvm-project/llvm/test/MC/Hexagon/align.s

@@ -0,0 +1,60 @@
+# RUN: llvm-mc -triple=hexagon -filetype=obj -mhvx %s | llvm-objdump -mhvx -d - | FileCheck %s
+
+# Verify that the .align directive emits the proper insn packets.
+
+{ r1 = sub(#1, r1) }
+# CHECK: 76414021 { r1 = sub(#1,r1)
+# CHECK-NEXT: 7f004000   nop
+# CHECK-NEXT: 7f004000   nop
+# CHECK-NEXT: 7f00c000   nop }
+
+.align 16
+{ r1 = sub(#1, r1)
+  r2 = sub(#1, r2) }
+# CHECK: 76414021 { r1 = sub(#1,r1)
+# CHECK-NEXT: 76424022   r2 = sub(#1,r2)
+# CHECK-NEXT: 7f004000  nop
+# CHECK-NEXT: 7f00c000   nop }
+
+.p2align 5
+{ r1 = sub(#1, r1)
+  r2 = sub(#1, r2)
+  r3 = sub(#1, r3) }
+# CHECK: 76434023   r3 = sub(#1,r3)
+# CHECK-NEXT: 7f00c000 nop }
+
+.align 16
+{ r1 = sub(#1, r1)
+  r2 = sub(#1, r2)
+  r3 = sub(#1, r3)
+  r4 = sub(#1, r4) }
+
+# Don't pad packets that can't be padded e.g. solo insts
+# CHECK: 9200c020 {  r0 = vextract(v0,r0) }
+r0 = vextract(v0, r0)
+.align 128
+# CHECK: 76414021 { r1 = sub(#1,r1)
+# CHECK-NEXT: 7f00c000   nop }
+{ r1 = sub(#1, r1) }
+
+#CHECK: { r1 = sub(#1,r1)
+#CHECK:   r2 = sub(#1,r2)
+#CHECK:   r3 = sub(#1,r3) }
+.falign
+.align 8
+{ r1 = sub(#1, r1)
+  r2 = sub(#1, r2)
+  r3 = sub(#1, r3)  }
+
+# CHECK: { immext(#0)
+# CHECK:   r0 = sub(##1,r0)
+# CHECK:   immext(#0)
+# CHECK:   r1 = sub(##1,r1) }
+# CHECK: { nop
+# CHECK:   nop
+# CHECK:   nop }
+# CHECK: { r0 = sub(#1,r0) }
+{ r0 = sub (##1, r0)
+  r1 = sub (##1, r1) }
+.align 16
+{ r0 = sub (#1, r0) }

external/llvm-project/llvm/test/MC/Hexagon/basic.ll

@@ -0,0 +1,7 @@
+;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
+;; RUN: | llvm-readobj -h -r | FileCheck -check-prefix=OBJ %s
+
+; OBJ: Format: ELF32-hexagon
+; OBJ: Arch: hexagon
+; OBJ: AddressSize: 32bit
+; OBJ: Machine: EM_HEXAGON (0xA4)

external/llvm-project/llvm/test/MC/Hexagon/bug20416.s

@@ -0,0 +1,13 @@
+# RUN: not llvm-mc -triple=hexagon -mv60 -mhvx -filetype=asm %s 2>%t; FileCheck %s --check-prefix=CHECK-V60-ERROR <%t
+# RUN:     llvm-mc -triple=hexagon -mv62 -mhvx -filetype=asm %s | FileCheck %s
+
+// for this a v60+/hvx instruction sequence, make sure fails with v60
+// but passes with v62.  this is because this instruction uses different
+// itinerary between v60 and v62
+{
+  v0.h=vsat(v5.w,v9.w)
+  v16.h=vsat(v6.w,v26.w)
+}
+# CHECK-V60-ERROR: rror: invalid instruction packet: slot error
+# CHECK: v0.h = vsat(v5.w,v9.w)
+# CHECK: v16.h = vsat(v6.w,v26.w)

external/llvm-project/llvm/test/MC/Hexagon/capitalizedEndloop.s

@@ -0,0 +1,29 @@
+# RUN: llvm-mc -triple=hexagon -filetype=obj %s | llvm-objdump -d -r - | FileCheck %s
+#
+
+# Verify that capitaizled endloops work
+
+	{ R0 = mpyi(R0,R0) } : endloop0
+	{ R0 = mpyi(R0,R0) } : ENDLOOP0
+	{ R0 = mpyi(R0,R0) }:endloop0
+
+	{ R0 = mpyi(R0,R0) } : endloop1
+	{ R0 = mpyi(R0,R0) } : ENDLOOP1
+	{ R0 = mpyi(R0,R0) }:endloop1
+
+	{ R0 = mpyi(R0,R0) } : endloop0 : endloop1
+	{ R0 = mpyi(R0,R0) } : ENDLOOP0 : ENDLOOP1
+	{ R0 = mpyi(R0,R0) }:endloop0:endloop1
+
+# CHECK: r0 = mpyi(r0,r0)
+# CHECK: :endloop0
+# CHECK: :endloop0
+# CHECK: :endloop0
+# CHECK: :endloop1
+# CHECK: :endloop1
+# CHECK: :endloop1
+# CHECK: :endloop0 :endloop1
+# CHECK: :endloop0 :endloop1
+# CHECK: :endloop0 :endloop1
+
+

external/llvm-project/llvm/test/MC/Hexagon/common-redeclare.s

@@ -0,0 +1,6 @@
+# RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump -t - | FileCheck %s
+
+# CHECK: 00000062 g       *COM*  00000008 quartet_table_isqrt
+
+.common quartet_table_isqrt, 98, 8
+.common quartet_table_isqrt, 98, 8

external/llvm-project/llvm/test/MC/Hexagon/dcfetch-symbol.s

@@ -0,0 +1,8 @@
+# RUN: not llvm-mc -arch=hexagon -filetype=obj %s
+
+#CHECK: 9400c000 { dcfetch(r0 + #0) }
+
+junk:
+{
+  dcfetch(r0 + #junk)
+}

external/llvm-project/llvm/test/MC/Hexagon/dcfetch.s

@@ -0,0 +1,15 @@
+# RUN: llvm-mc -triple=hexagon -filetype=obj -mno-pairing %s -o %t; llvm-objdump -d %t | FileCheck %s
+
+# Check that DCFETCH is correctly shuffled.
+
+	{ dcfetch(r2 + #0); r1 = memw(r2) }
+# CHECK: 9402c000
+
+# Bug 17424: This should be a legal packet
+{
+  P3 = SP1LOOP0(#8,R18)
+  R7:6 = MEMUBH(R4++#4)
+  R13:12 = VALIGNB(R11:10,R9:8,P2)
+  DCFETCH(R5+#(8+0))
+}
+# CHECK-NOT: error:

external/llvm-project/llvm/test/MC/Hexagon/dealloc-return-jump.s

@@ -0,0 +1,7 @@
+# RUN: not llvm-mc -arch=hexagon -mcpu=hexagonv62 -filetype=obj -o - %s
+# Check that a duplex involving dealloc_return is correctly checked
+# dealloc_return cannot be involved in a double jump packet
+
+{ r0=add(r0,#-1)
+  p0=cmp.eq(r0,r0); if (p0.new) jump:nt 0
+  if (p0) dealloc_return }

external/llvm-project/llvm/test/MC/Hexagon/decode_acc_type.s

@@ -0,0 +1,150 @@
+# RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump -d - | FileCheck %s
+#
+
+# Currently ignore if there is one or two #'s
+
+		r7 = memw(gp+#192)
+# CHECK:	r7 = memw(gp+#192)
+
+		r3:2 = memd(gp+#64)
+# CHECK: 	r3:2 = memd(gp+#64)
+
+		{ p3 = p1; r8 = #2; if (p3.new) memw(##8) = r8.new }
+# CHECK:	if (p3.new) memw({{..}}8) = r8
+
+		{ p3 = p1; r8 = #2; if (!p3.new) memw(##8) = r8.new }
+# CHECK:	if (!p3.new) memw({{..}}8) = r8.new
+
+		{ r8 = #2; if (p3) memw(##8) = r8.new }
+# CHECK:	if (p3) memw({{..}}8) = r8.new
+
+		{ r8 = #2; if (!p3) memw(##8) = r8.new }
+# CHECK:	if (!p3) memw({{..}}8) = r8.new
+
+		{ p3 = p1; r8 = #2; if (p3.new) memh(##8) = r8.new }
+# CHECK:	if (p3.new) memh({{..}}8) = r8.new
+
+		{ p3 = p1; r8 = #2; if (!p3.new) memh(##8) = r8.new }
+# CHECK:	if (!p3.new) memh({{..}}8) = r8.new
+
+		{ r8 = #2; if (p3) memh(##8) = r8.new }
+# CHECK:	memh({{..}}8) = r8.new
+
+		{ r8 = #2; if (!p3) memh(##8) = r8.new }
+# CHECK:	if (!p3) memh({{..}}8) = r8.new
+
+		{ p3 = p1; r8 = #2; if (p3.new) memb(##8) = r8.new }
+# CHECK:	if (p3.new) memb({{..}}8) = r8.new
+
+		{ p3 = p1; r8 = #2; if (!p3.new) memb(##8) = r8.new }
+# CHECK:	if (!p3.new) memb({{..}}8) = r8.new
+
+		{ r8 = #2; if (p3) memb(##8) = r8.new }
+# CHECK:	if (p3) memb({{..}}8) = r8.new
+
+		{ r8 = #2; if (!p3) memb(##8) = r8.new }
+# CHECK:	if (!p3) memb({{..}}8) = r8.new
+
+		{ if (p3) memw(##8) = r8 }
+# CHECK:	if (p3) memw({{..}}8) = r8
+
+		{ if (!p3) memw(##8) = r8 }
+# CHECK:	if (!p3) memw({{..}}8) = r8
+
+		{ p3 = p1; if (p3.new) memw(##8) = r8 }
+# CHECK:	if (p3.new) memw({{..}}8) = r8
+
+		{ p3 = p1; if (!p3.new) memw(##8) = r8 }
+# CHECK:	if (!p3.new) memw({{..}}8) = r8
+
+
+		if (!p2) r14 = memb(##48)
+# CHECK:	if (!p2) r14 = memb({{..}}48)
+
+		if (p2) r14 = memb(##48)
+# CHECK:	if (p2) r14 = memb({{..}}48)
+
+		{p2 = p0; if (!p2.new) r14 = memb(##48) }
+# CHECK:	if (!p2.new) r14 = memb({{..}}48)
+
+		{p3 = p2; if (p3.new) r14 = memb(##48) }
+# CHECK:	if (p3.new) r14 = memb({{..}}48)
+
+
+		if (!p2) r14 = memh(##48)
+# CHECK:	if (!p2) r14 = memh({{..}}48)
+
+		if (p2) r14 = memh(##48)
+# CHECK:	if (p2) r14 = memh({{..}}48)
+
+		{p2 = p0; if (!p2.new) r14 = memh(##48) }
+# CHECK:	if (!p2.new) r14 = memh({{..}}48)
+
+		{p3 = p2; if (p3.new) r14 = memh(##48) }
+# CHECK:	if (p3.new) r14 = memh({{..}}48)
+
+
+		if (!p2) r14 = memub(##48)
+# CHECK:	if (!p2) r14 = memub({{..}}48)
+
+		if (p2) r14 = memub(##48)
+# CHECK:	if (p2) r14 = memub({{..}}48)
+
+		{p2 = p0; if (!p2.new) r14 = memub(##48) }
+# CHECK:	if (!p2.new) r14 = memub({{..}}48)
+
+		{p3 = p2; if (p3.new) r14 = memub(##48) }
+# CHECK:	if (p3.new) r14 = memub({{..}}48)
+
+
+		if (!p2) r14 = memuh(##48)
+# CHECK:	if (!p2) r14 = memuh({{..}}48)
+
+		if (p2) r14 = memuh(##48)
+# CHECK:	if (p2) r14 = memuh({{..}}48)
+
+		{p2 = p0; if (!p2.new) r14 = memuh(##48) }
+# CHECK:	if (!p2.new) r14 = memuh({{..}}48)
+
+		{p3 = p2; if (p3.new) r14 = memuh(##48) }
+# CHECK:	r14 = memuh({{..}}48)
+
+
+		if (!p2) r14 = memw(##48)
+# CHECK:	if (!p2) r14 = memw({{..}}48)
+
+		if (p2) r14 = memw(##48)
+# CHECK:	if (p2) r14 = memw({{..}}48)
+
+		{p2 = p0; if (!p2.new) r14 = memw(##48) }
+# CHECK:	if (!p2.new) r14 = memw({{..}}48)
+
+		{p3 = p2; if (p3.new) r14 = memw(##48) }
+# CHECK:	if (p3.new) r14 = memw({{..}}48)
+
+		r7 = memh(##32)
+# CHECK: 	r7 = memh(##32)
+		r7 = memuh(##32)
+# CHECK: 	r7 = memuh(##32)
+
+		memd(##32) = r15:14
+# CHECK: 	memd(##32) = r15:14
+
+		{r2 = #9; memw(##32) = r2.new}
+# CHECK:	memw(##32) = r2.new
+
+		{r2 = #9; memb(##32) = r2.new}
+# CHECK:	memb(##32) = r2.new
+
+		memw(##32) = r15
+# CHECK: 	memw(##32) = r15
+
+		memh(##32) = r16
+# CHECK: 	memh(##32) = r16
+
+		memb(##32) = r17
+# CHECK: 	memb(##32) = r17
+
+
+		r3:2 = interleave(r31:30)
+# CHECK:	r3:2 = interleave(r31:30)

external/llvm-project/llvm/test/MC/Hexagon/dis-duplex-p0.s

@@ -0,0 +1,10 @@
+// RUN: llvm-mc -arch=hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s
+
+{ r7 = #-1
+  r6 = #-1 }
+// CHECK: { r7 = #-1; r6 = #-1 }
+
+{ p0 = r0
+  if (p0.new) r7 = #0
+  if (!p0.new) r7 = #0 }
+// CHECK: if (p0.new) r7 = #0; if (!p0.new) r7 = #0

external/llvm-project/llvm/test/MC/Hexagon/double-vector-producer.s

@@ -0,0 +1,12 @@
+# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv60 -mhvx -filetype=obj %s | llvm-objdump -d - | FileCheck %s
+{
+  v1:0 = vshuff(v1,v0,r7)
+  v2.w = vadd(v13.w,v15.w)
+  v3.w = vadd(v8.w,v14.w)
+  vmem(r2+#-2) = v0.new
+}
+
+# CHECK: 60 61 07 1b
+# CHECK: 02 4d 4f 1c
+# CHECK: 03 48 4e 1c
+# CHECK: 26 e6 22 28

external/llvm-project/llvm/test/MC/Hexagon/duplex-addi-global-imm.s

@@ -0,0 +1,15 @@
+# RUN: llvm-mc -arch=hexagon -show-encoding %s | FileCheck %s
+# Check that we generate a duplex for this packet.
+# CHECK: encoding: [A,0x40'A',A,A,0x01'B',0x28'B',B,0x20'B']
+
+.data
+g:
+.long 0
+
+.text
+  {
+    r0 = add(r0,##g)
+    r1 = #0
+  }
+
+

external/llvm-project/llvm/test/MC/Hexagon/duplex-registers.s

@@ -0,0 +1,10 @@
+#RUN: llvm-mc -triple=hexagon -filetype=obj %s | llvm-objdump -d - | FileCheck %s
+
+.text
+{
+  r16 = memuh(r17 + #0)
+  r18 = memuh(r19 + #0)
+}
+
+# CHECK: 289808ba
+# CHECK: r16 = memuh(r17+#0);{{ *}}r18 = memuh(r19+#0)

external/llvm-project/llvm/test/MC/Hexagon/elf-flags.s

@@ -0,0 +1,11 @@
+# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv4 --filetype=obj %s -o - | llvm-readobj -file-headers -elf-output-style=GNU | FileCheck --check-prefix=CHECK-V4 %s
+# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv5 --filetype=obj %s -o - | llvm-readobj -file-headers -elf-output-style=GNU | FileCheck --check-prefix=CHECK-V5 %s
+# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv55 --filetype=obj %s -o - | llvm-readobj -file-headers -elf-output-style=GNU | FileCheck --check-prefix=CHECK-V55 %s
+# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv60 --filetype=obj %s -o - | llvm-readobj -file-headers -elf-output-style=GNU | FileCheck --check-prefix=CHECK-V60 %s
+# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv62 --filetype=obj %s -o - | llvm-readobj -file-headers -elf-output-style=GNU | FileCheck --check-prefix=CHECK-V62 %s
+
+# CHECK-V4: Flags: 0x3
+# CHECK-V5: Flags: 0x4
+# CHECK-V55: Flags: 0x5
+# CHECK-V60: Flags: 0x60
+# CHECK-V62: Flags: 0x62

external/llvm-project/llvm/test/MC/Hexagon/empty_asm.s

@@ -0,0 +1,15 @@
+# RUN: llvm-mc -triple=hexagon -filetype=asm %s -o - | FileCheck %s
+
+# Verify empty packets aren't printed
+barrier
+{}
+barrier
+# CHECK: {
+# CHECK-NEXT: barrier
+# CHECK-NEXT: }
+# CHECK-NOT: }
+# CHECK: {
+# CHECK-NEXT: barrier
+# CHECK-NEXT: }
+
+