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Imported Upstream version 6.10.0.49

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Former-commit-id: 1d6753294b2993e1fbf92de9366bb9544db4189b
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Xamarin Public Jenkins (auto-signing)
2020-01-16 16:38:04 +00:00
parent d94e79959b
commit 468663ddbb
48518 changed files with 2789335 additions and 61176 deletions
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42
external/llvm-project/llvm/test/MC/ARM/thumb-invalid-crypto.txt vendored Normal file
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@ RUN: not llvm-mc -triple thumbv8 -mattr=+neon,+crypto -show-encoding < %s 2>&1 | FileCheck %s
iteee lo
aesdlo.8 q0, q1
@ CHECK: error: instruction 'aesd' is not predicable, but condition code specified
aesimchs.8 q0, q1
@ CHECK: error: instruction 'aesimc' is not predicable, but condition code specified
aesmchs.8 q0, q1
@ CHECK: error: instruction 'aesmc' is not predicable, but condition code specified
aesehs.8 q0, q1
@ CHECK: error: instruction 'aese' is not predicable, but condition code specified
itee hs
sha1hhs.32 q0, q1
@ CHECK: error: instruction 'sha1h' is not predicable, but condition code specified
sha1su1lo.32 q0, q1
@ CHECK: error: instruction 'sha1su1' is not predicable, but condition code specified
sha256su0lo.32 q0, q1
@ CHECK: error: instruction 'sha256su0' is not predicable, but condition code specified
iteee lo
sha1clo.32 s0, d1, q2
@ CHECK: error: instruction 'sha1c' is not predicable, but condition code specified
sha1mhs.32 q0, s1, q2
@ CHECK: error: instruction 'sha1m' is not predicable, but condition code specified
sha1phs.32 s0, q1, q2
@ CHECK: error: instruction 'sha1p' is not predicable, but condition code specified
sha1su0hs.32 d0, q1, q2
@ CHECK: error: instruction 'sha1su0' is not predicable, but condition code specified
itee hs
sha256hhs.32 q0, s1, q2
@ CHECK: error: instruction 'sha256h' is not predicable, but condition code specified
sha256h2lo.32 q0, q1, s2
@ CHECK: error: instruction 'sha256h2' is not predicable, but condition code specified
sha256su1lo.32 s0, d1, q2
@ CHECK: error: instruction 'sha256su1' is not predicable, but condition code specified
ite lo
vmulllo.p64 q0, s1, s3
@ CHECK: error: instruction 'vmull' is not predicable, but condition code specified
vmullhs.p64 q0, d16, d17
@ CHECK: error: instruction 'vmull' is not predicable, but condition code specified