Imported Upstream version 6.10.0.49

Former-commit-id: 1d6753294b2993e1fbf92de9366bb9544db4189b
2020-01-16 16:38:04 +00:00
parent d94e79959b
commit 468663ddbb
48518 changed files with 2789335 additions and 61176 deletions
--- a/external/llvm-project/llvm/test/MC/AArch64/SVE/add-diagnostics.s
+++ b/external/llvm-project/llvm/test/MC/AArch64/SVE/add-diagnostics.s
@@ -0,0 +1,19 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// Register z32 does not exist.
+add z22.h, z10.h, z32.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: add z22.h, z10.h, z32.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Invalid element kind.
+add z20.h, z2.h, z31.x
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid sve vector kind qualifier
+// CHECK-NEXT: add z20.h, z2.h, z31.x
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Element size specifiers should match.
+add z27.h, z11.h, z27.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: add z27.h, z11.h, z27.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
--- a/external/llvm-project/llvm/test/MC/AArch64/SVE/add.s
+++ b/external/llvm-project/llvm/test/MC/AArch64/SVE/add.s
@@ -0,0 +1,104 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+add     z31.s, z31.s, z31.s
+// CHECK-INST: add     z31.s, z31.s, z31.s
+// CHECK-ENCODING: [0xff,0x03,0xbf,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 03 bf 04 <unknown>
+
+add     z23.d, z13.d, z8.d
+// CHECK-INST: add     z23.d, z13.d, z8.d
+// CHECK-ENCODING: [0xb7,0x01,0xe8,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 01 e8 04 <unknown>
+
+add     z0.s, z0.s, z0.s
+// CHECK-INST: add     z0.s, z0.s, z0.s
+// CHECK-ENCODING: [0x00,0x00,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 00 a0 04 <unknown>
+
+add     z31.d, z31.d, z31.d
+// CHECK-INST: add     z31.d, z31.d, z31.d
+// CHECK-ENCODING: [0xff,0x03,0xff,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 03 ff 04 <unknown>
+
+add     z21.b, z10.b, z21.b
+// CHECK-INST: add     z21.b, z10.b, z21.b
+// CHECK-ENCODING: [0x55,0x01,0x35,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 01 35 04 <unknown>
+
+add     z31.b, z31.b, z31.b
+// CHECK-INST: add     z31.b, z31.b, z31.b
+// CHECK-ENCODING: [0xff,0x03,0x3f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 03 3f 04 <unknown>
+
+add     z0.h, z0.h, z0.h
+// CHECK-INST: add     z0.h, z0.h, z0.h
+// CHECK-ENCODING: [0x00,0x00,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 00 60 04 <unknown>
+
+add     z23.b, z13.b, z8.b
+// CHECK-INST: add     z23.b, z13.b, z8.b
+// CHECK-ENCODING: [0xb7,0x01,0x28,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 01 28 04 <unknown>
+
+add     z0.d, z0.d, z0.d
+// CHECK-INST: add     z0.d, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x00,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 00 e0 04 <unknown>
+
+add     z31.h, z31.h, z31.h
+// CHECK-INST: add     z31.h, z31.h, z31.h
+// CHECK-ENCODING: [0xff,0x03,0x7f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 03 7f 04 <unknown>
+
+add     z0.b, z0.b, z0.b
+// CHECK-INST: add     z0.b, z0.b, z0.b
+// CHECK-ENCODING: [0x00,0x00,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 00 20 04 <unknown>
+
+add     z21.d, z10.d, z21.d
+// CHECK-INST: add     z21.d, z10.d, z21.d
+// CHECK-ENCODING: [0x55,0x01,0xf5,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 01 f5 04 <unknown>
+
+add     z21.h, z10.h, z21.h
+// CHECK-INST: add     z21.h, z10.h, z21.h
+// CHECK-ENCODING: [0x55,0x01,0x75,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 01 75 04 <unknown>
+
+add     z21.s, z10.s, z21.s
+// CHECK-INST: add     z21.s, z10.s, z21.s
+// CHECK-ENCODING: [0x55,0x01,0xb5,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 01 b5 04 <unknown>
+
+add     z23.h, z13.h, z8.h
+// CHECK-INST: add     z23.h, z13.h, z8.h
+// CHECK-ENCODING: [0xb7,0x01,0x68,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 01 68 04 <unknown>
+
+add     z23.s, z13.s, z8.s
+// CHECK-INST: add     z23.s, z13.s, z8.s
+// CHECK-ENCODING: [0xb7,0x01,0xa8,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 01 a8 04 <unknown>
--- a/external/llvm-project/llvm/test/MC/AArch64/SVE/dot-req-diagnostics.s
+++ b/external/llvm-project/llvm/test/MC/AArch64/SVE/dot-req-diagnostics.s
@@ -0,0 +1,20 @@
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+sve < %s 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-ERROR %s
+
+foo:
+// CHECK: error: sve predicate register without type specifier expected
+  pbarb .req p1.b
+// CHECK: error: sve predicate register without type specifier expected
+  pbarh .req p1.h
+// CHECK: error: sve predicate register without type specifier expected
+  pbars .req p1.s
+// CHECK: error: sve predicate register without type specifier expected
+  pbard .req p1.d
+
+// CHECK: error: sve vector register without type specifier expected
+  zbarb .req z1.b
+// CHECK: error: sve vector register without type specifier expected
+  zbarh .req z1.h
+// CHECK: error: sve vector register without type specifier expected
+  zbars .req z1.s
+// CHECK: error: sve vector register without type specifier expected
+  zbard .req z1.d
--- a/external/llvm-project/llvm/test/MC/AArch64/SVE/dot-req.s
+++ b/external/llvm-project/llvm/test/MC/AArch64/SVE/dot-req.s
@@ -0,0 +1,9 @@
+// RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+sve -show-encoding < %s 2>&1 | FileCheck %s
+
+foo:
+// CHECK-NOT: error:
+  pbar .req p1
+
+// CHECK: add z0.s, z1.s, z2.s
+  zbar .req z1
+  add  z0.s, zbar.s, z2.s
--- a/external/llvm-project/llvm/test/MC/AArch64/SVE/sub-diagnostics.s
+++ b/external/llvm-project/llvm/test/MC/AArch64/SVE/sub-diagnostics.s
@@ -0,0 +1,19 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// Register z32 does not exist.
+sub z3.h, z26.h, z32.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: sub z3.h, z26.h, z32.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Invalid element kind.
+sub z4.h, z27.h, z31.x
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid sve vector kind qualifier
+// CHECK-NEXT: sub z4.h, z27.h, z31.x
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Element size specifiers should match.
+sub z0.h, z8.h, z8.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: sub z0.h, z8.h, z8.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
--- a/external/llvm-project/llvm/test/MC/AArch64/SVE/sub.s
+++ b/external/llvm-project/llvm/test/MC/AArch64/SVE/sub.s
@@ -0,0 +1,104 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+sub     z0.h, z0.h, z0.h
+// CHECK-INST: sub     z0.h, z0.h, z0.h
+// CHECK-ENCODING: [0x00,0x04,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 04 60 04 <unknown>
+
+sub     z21.b, z10.b, z21.b
+// CHECK-INST: sub     z21.b, z10.b, z21.b
+// CHECK-ENCODING: [0x55,0x05,0x35,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 05 35 04 <unknown>
+
+sub     z31.h, z31.h, z31.h
+// CHECK-INST: sub     z31.h, z31.h, z31.h
+// CHECK-ENCODING: [0xff,0x07,0x7f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 07 7f 04 <unknown>
+
+sub     z21.h, z10.h, z21.h
+// CHECK-INST: sub     z21.h, z10.h, z21.h
+// CHECK-ENCODING: [0x55,0x05,0x75,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 05 75 04 <unknown>
+
+sub     z31.b, z31.b, z31.b
+// CHECK-INST: sub     z31.b, z31.b, z31.b
+// CHECK-ENCODING: [0xff,0x07,0x3f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 07 3f 04 <unknown>
+
+sub     z0.s, z0.s, z0.s
+// CHECK-INST: sub     z0.s, z0.s, z0.s
+// CHECK-ENCODING: [0x00,0x04,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 04 a0 04 <unknown>
+
+sub     z23.b, z13.b, z8.b
+// CHECK-INST: sub     z23.b, z13.b, z8.b
+// CHECK-ENCODING: [0xb7,0x05,0x28,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 05 28 04 <unknown>
+
+sub     z21.d, z10.d, z21.d
+// CHECK-INST: sub     z21.d, z10.d, z21.d
+// CHECK-ENCODING: [0x55,0x05,0xf5,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 05 f5 04 <unknown>
+
+sub     z21.s, z10.s, z21.s
+// CHECK-INST: sub     z21.s, z10.s, z21.s
+// CHECK-ENCODING: [0x55,0x05,0xb5,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 05 b5 04 <unknown>
+
+sub     z0.b, z0.b, z0.b
+// CHECK-INST: sub     z0.b, z0.b, z0.b
+// CHECK-ENCODING: [0x00,0x04,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 04 20 04 <unknown>
+
+sub     z23.d, z13.d, z8.d
+// CHECK-INST: sub     z23.d, z13.d, z8.d
+// CHECK-ENCODING: [0xb7,0x05,0xe8,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 05 e8 04 <unknown>
+
+sub     z23.s, z13.s, z8.s
+// CHECK-INST: sub     z23.s, z13.s, z8.s
+// CHECK-ENCODING: [0xb7,0x05,0xa8,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 05 a8 04 <unknown>
+
+sub     z31.d, z31.d, z31.d
+// CHECK-INST: sub     z31.d, z31.d, z31.d
+// CHECK-ENCODING: [0xff,0x07,0xff,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 07 ff 04 <unknown>
+
+sub     z23.h, z13.h, z8.h
+// CHECK-INST: sub     z23.h, z13.h, z8.h
+// CHECK-ENCODING: [0xb7,0x05,0x68,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 05 68 04 <unknown>
+
+sub     z0.d, z0.d, z0.d
+// CHECK-INST: sub     z0.d, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x04,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 04 e0 04 <unknown>
+
+sub     z31.s, z31.s, z31.s
+// CHECK-INST: sub     z31.s, z31.s, z31.s
+// CHECK-ENCODING: [0xff,0x07,0xbf,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 07 bf 04 <unknown>
--- a/external/llvm-project/llvm/test/MC/AArch64/SVE/zip1-diagnostics.s
+++ b/external/llvm-project/llvm/test/MC/AArch64/SVE/zip1-diagnostics.s
@@ -0,0 +1,43 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// Invalid element kind.
+zip1 z10.h, z22.h, z31.x
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid sve vector kind qualifier
+// CHECK-NEXT: zip1 z10.h, z22.h, z31.x
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Element size specifiers should match.
+zip1 z10.h, z3.h, z15.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: zip1 z10.h, z3.h, z15.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Too few operands
+zip1 z1.h, z2.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction
+// CHECK-NEXT: zip1 z1.h, z2.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// z32 is not a valid SVE data register
+zip1 z1.s, z2.s, z32.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: zip1 z1.s, z2.s, z32.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// p16 is not a valid SVE predicate register
+zip1 p1.s, p2.s, p16.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: zip1 p1.s, p2.s, p16.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Combining data and predicate registers as operands
+zip1 z1.s, z2.s, p3.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: zip1 z1.s, z2.s, p3.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Combining predicate and data registers as operands
+zip1 p1.s, p2.s, z3.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: zip1 p1.s, p2.s, z3.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
--- a/external/llvm-project/llvm/test/MC/AArch64/SVE/zip1.s
+++ b/external/llvm-project/llvm/test/MC/AArch64/SVE/zip1.s
@@ -0,0 +1,104 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+zip1    z0.b, z0.b, z0.b
+// CHECK-INST: zip1    z0.b, z0.b, z0.b
+// CHECK-ENCODING: [0x00,0x60,0x20,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 60 20 05 <unknown>
+
+zip1    z0.h, z0.h, z0.h
+// CHECK-INST: zip1    z0.h, z0.h, z0.h
+// CHECK-ENCODING: [0x00,0x60,0x60,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 60 60 05 <unknown>
+
+zip1    z0.s, z0.s, z0.s
+// CHECK-INST: zip1    z0.s, z0.s, z0.s
+// CHECK-ENCODING: [0x00,0x60,0xa0,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 60 a0 05 <unknown>
+
+zip1    z0.d, z0.d, z0.d
+// CHECK-INST: zip1    z0.d, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x60,0xe0,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 60 e0 05 <unknown>
+
+zip1    z31.b, z31.b, z31.b
+// CHECK-INST: zip1    z31.b, z31.b, z31.b
+// CHECK-ENCODING: [0xff,0x63,0x3f,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 63 3f 05 <unknown>
+
+zip1    z31.h, z31.h, z31.h
+// CHECK-INST: zip1    z31.h, z31.h, z31.h
+// CHECK-ENCODING: [0xff,0x63,0x7f,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 63 7f 05 <unknown>
+
+zip1    z31.s, z31.s, z31.s
+// CHECK-INST: zip1    z31.s, z31.s, z31.s
+// CHECK-ENCODING: [0xff,0x63,0xbf,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 63 bf 05 <unknown>
+
+zip1    z31.d, z31.d, z31.d
+// CHECK-INST: zip1    z31.d, z31.d, z31.d
+// CHECK-ENCODING: [0xff,0x63,0xff,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 63 ff 05 <unknown>
+
+zip1    p0.b, p0.b, p0.b
+// CHECK-INST: zip1    p0.b, p0.b, p0.b
+// CHECK-ENCODING: [0x00,0x40,0x20,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 20 05 <unknown>
+
+zip1    p0.h, p0.h, p0.h
+// CHECK-INST: zip1    p0.h, p0.h, p0.h
+// CHECK-ENCODING: [0x00,0x40,0x60,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 60 05 <unknown>
+
+zip1    p0.s, p0.s, p0.s
+// CHECK-INST: zip1    p0.s, p0.s, p0.s
+// CHECK-ENCODING: [0x00,0x40,0xa0,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 a0 05 <unknown>
+
+zip1    p0.d, p0.d, p0.d
+// CHECK-INST: zip1    p0.d, p0.d, p0.d
+// CHECK-ENCODING: [0x00,0x40,0xe0,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 e0 05 <unknown>
+
+zip1    p15.b, p15.b, p15.b
+// CHECK-INST: zip1    p15.b, p15.b, p15.b
+// CHECK-ENCODING: [0xef,0x41,0x2f,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 41 2f 05 <unknown>
+
+zip1    p15.s, p15.s, p15.s
+// CHECK-INST: zip1    p15.s, p15.s, p15.s
+// CHECK-ENCODING: [0xef,0x41,0xaf,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 41 af 05 <unknown>
+
+zip1    p15.h, p15.h, p15.h
+// CHECK-INST: zip1    p15.h, p15.h, p15.h
+// CHECK-ENCODING: [0xef,0x41,0x6f,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 41 6f 05 <unknown>
+
+zip1    p15.d, p15.d, p15.d
+// CHECK-INST: zip1    p15.d, p15.d, p15.d
+// CHECK-ENCODING: [0xef,0x41,0xef,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 41 ef 05 <unknown>
--- a/external/llvm-project/llvm/test/MC/AArch64/SVE/zip2-diagnostics.s
+++ b/external/llvm-project/llvm/test/MC/AArch64/SVE/zip2-diagnostics.s
@@ -0,0 +1,43 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// Invalid element kind.
+zip2 z6.h, z23.h, z31.x
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid sve vector kind qualifier
+// CHECK-NEXT: zip2 z6.h, z23.h, z31.x
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Element size specifiers should match.
+zip2 z0.h, z30.h, z24.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: zip2 z0.h, z30.h, z24.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Too few operands
+zip2 z1.h, z2.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction
+// CHECK-NEXT: zip2 z1.h, z2.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// z32 is not a valid SVE data register
+zip2 z1.s, z2.s, z32.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: zip2 z1.s, z2.s, z32.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// p16 is not a valid SVE predicate register
+zip2 p1.s, p2.s, p16.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: zip2 p1.s, p2.s, p16.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Combining data and predicate registers as operands
+zip2 z1.s, z2.s, p3.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: zip2 z1.s, z2.s, p3.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Combining predicate and data registers as operands
+zip2 p1.s, p2.s, z3.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: zip2 p1.s, p2.s, z3.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
--- a/external/llvm-project/llvm/test/MC/AArch64/SVE/zip2.s
+++ b/external/llvm-project/llvm/test/MC/AArch64/SVE/zip2.s
@@ -0,0 +1,104 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+zip2    z0.b, z0.b, z0.b
+// CHECK-INST: zip2    z0.b, z0.b, z0.b
+// CHECK-ENCODING: [0x00,0x64,0x20,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 64 20 05 <unknown>
+
+zip2    z0.h, z0.h, z0.h
+// CHECK-INST: zip2    z0.h, z0.h, z0.h
+// CHECK-ENCODING: [0x00,0x64,0x60,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 64 60 05 <unknown>
+
+zip2    z0.s, z0.s, z0.s
+// CHECK-INST: zip2    z0.s, z0.s, z0.s
+// CHECK-ENCODING: [0x00,0x64,0xa0,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 64 a0 05 <unknown>
+
+zip2    z0.d, z0.d, z0.d
+// CHECK-INST: zip2    z0.d, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x64,0xe0,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 64 e0 05 <unknown>
+
+zip2    z31.b, z31.b, z31.b
+// CHECK-INST: zip2    z31.b, z31.b, z31.b
+// CHECK-ENCODING: [0xff,0x67,0x3f,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 67 3f 05 <unknown>
+
+zip2    z31.h, z31.h, z31.h
+// CHECK-INST: zip2    z31.h, z31.h, z31.h
+// CHECK-ENCODING: [0xff,0x67,0x7f,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 67 7f 05 <unknown>
+
+zip2    z31.s, z31.s, z31.s
+// CHECK-INST: zip2    z31.s, z31.s, z31.s
+// CHECK-ENCODING: [0xff,0x67,0xbf,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 67 bf 05 <unknown>
+
+zip2    z31.d, z31.d, z31.d
+// CHECK-INST: zip2    z31.d, z31.d, z31.d
+// CHECK-ENCODING: [0xff,0x67,0xff,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 67 ff 05 <unknown>
+
+zip2    p0.b, p0.b, p0.b
+// CHECK-INST: zip2    p0.b, p0.b, p0.b
+// CHECK-ENCODING: [0x00,0x44,0x20,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 44 20 05 <unknown>
+
+zip2    p0.h, p0.h, p0.h
+// CHECK-INST: zip2    p0.h, p0.h, p0.h
+// CHECK-ENCODING: [0x00,0x44,0x60,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 44 60 05 <unknown>
+
+zip2    p0.s, p0.s, p0.s
+// CHECK-INST: zip2    p0.s, p0.s, p0.s
+// CHECK-ENCODING: [0x00,0x44,0xa0,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 44 a0 05 <unknown>
+
+zip2    p0.d, p0.d, p0.d
+// CHECK-INST: zip2    p0.d, p0.d, p0.d
+// CHECK-ENCODING: [0x00,0x44,0xe0,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 44 e0 05 <unknown>
+
+zip2    p15.b, p15.b, p15.b
+// CHECK-INST: zip2    p15.b, p15.b, p15.b
+// CHECK-ENCODING: [0xef,0x45,0x2f,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 45 2f 05 <unknown>
+
+zip2    p15.h, p15.h, p15.h
+// CHECK-INST: zip2    p15.h, p15.h, p15.h
+// CHECK-ENCODING: [0xef,0x45,0x6f,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 45 6f 05 <unknown>
+
+zip2    p15.s, p15.s, p15.s
+// CHECK-INST: zip2    p15.s, p15.s, p15.s
+// CHECK-ENCODING: [0xef,0x45,0xaf,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 45 af 05 <unknown>
+
+zip2    p15.d, p15.d, p15.d
+// CHECK-INST: zip2    p15.d, p15.d, p15.d
+// CHECK-ENCODING: [0xef,0x45,0xef,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 45 ef 05 <unknown>