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Imported Upstream version 6.10.0.49

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Former-commit-id: 1d6753294b2993e1fbf92de9366bb9544db4189b
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Xamarin Public Jenkins (auto-signing)
2020-01-16 16:38:04 +00:00
parent d94e79959b
commit 468663ddbb
48518 changed files with 2789335 additions and 61176 deletions
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20
external/llvm-project/llvm/test/CodeGen/X86/2010-02-23-DIV8rDefinesAX.ll vendored Normal file
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@@ -0,0 +1,20 @@
; RUN: llc < %s
; PR6374
;
; This test produces a DIV8r instruction and uses %AX instead of %AH and %AL.
; The DIV8r must have the right imp-defs for that to work.
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
target triple = "x86_64-apple-darwin10.0.0"
%struct._i386_state = type { %union.anon }
%union.anon = type { [0 x i8] }
define void @i386_aam(%struct._i386_state* nocapture %cpustate) nounwind ssp {
entry:
%call = tail call fastcc signext i8 @FETCH() ; <i8> [#uses=1]
%rem = urem i8 0, %call ; <i8> [#uses=1]
store i8 %rem, i8* undef
ret void
}
declare fastcc signext i8 @FETCH() nounwind readnone ssp