Imported Upstream version 6.10.0.49

Former-commit-id: 1d6753294b2993e1fbf92de9366bb9544db4189b

external/llvm-project/llvm/test/CodeGen/MIR/X86/auto-successor.mir

@@ -0,0 +1,61 @@
+# RUN: llc -mtriple=x86_64-- -o - %s -run-pass=none -verify-machineinstrs -simplify-mir | FileCheck %s
+---
+# We shouldn't need any explicit successor lists in these examples
+# CHECK-LABEL: name: func0
+# CHECK: bb.0:
+# CHECK-NOT: successors
+# CHECK: JE_1 %bb.1, implicit undef %eflags
+# CHECK: JMP_1 %bb.3
+# CHECK: bb.1:
+# CHECK-NOT: successors
+# CHECK: bb.2:
+# CHECK-NOT: successors
+# CHECK: JE_1 %bb.1, implicit undef %eflags
+# CHECK: bb.3:
+# CHECK: RETQ undef %eax
+name: func0
+body: |
+  bb.0:
+    JE_1 %bb.1, implicit undef %eflags
+    JMP_1 %bb.3
+
+  bb.1:
+
+  bb.2:
+    JE_1 %bb.1, implicit undef %eflags
+
+  bb.3:
+    JE_1 %bb.4, implicit undef %eflags   ; condjump+fallthrough to same block
+
+  bb.4:
+    RETQ undef %eax
+...
+---
+# Some cases that need explicit successors:
+# CHECK-LABEL: name: func1
+name: func1
+body: |
+  bb.0:
+    ; CHECK: bb.0:
+    ; CHECK: successors: %bb.3, %bb.1
+    successors: %bb.3, %bb.1   ; different order than operands
+    JE_1 %bb.1, implicit undef %eflags
+    JMP_1 %bb.3
+
+  bb.1:
+    ; CHECK: bb.1:
+    ; CHECK: successors: %bb.2, %bb.1
+    successors: %bb.2, %bb.1   ; different order (fallthrough variant)
+    JE_1 %bb.1, implicit undef %eflags
+
+  bb.2:
+    ; CHECK: bb.2:
+    ; CHECK: successors: %bb.1(0x60000000), %bb.3(0x20000000)
+    successors: %bb.1(3), %bb.3(1)  ; branch probabilities not normalized
+    JE_1 %bb.1, implicit undef %eflags
+
+  bb.3:
+    ; CHECK: bb.3:
+    ; CHECK: RETQ undef %eax
+    RETQ undef %eax
+...

external/llvm-project/llvm/test/CodeGen/MIR/X86/basic-block-liveins.mir

@@ -0,0 +1,65 @@
+# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# This test ensures that the MIR parser parses basic block liveins correctly.
+
+--- |
+
+  define i32 @test(i32 %a, i32 %b) {
+  body:
+    %c = add i32 %a, %b
+    ret i32 %c
+  }
+
+  define i32 @test2(i32 %a, i32 %b) {
+  body:
+    %c = add i32 %a, %b
+    ret i32 %c
+  }
+
+  define i32 @test3() {
+  body:
+    ret i32 0
+  }
+
+...
+---
+name: test
+tracksRegLiveness: true
+body: |
+  ; CHECK-LABEL: bb.0.body:
+  ; CHECK-NEXT:    liveins: %edi, %esi
+  bb.0.body:
+    liveins: %edi, %esi
+
+    %eax = LEA64_32r killed %rdi, 1, killed %rsi, 0, _
+    RETQ %eax
+...
+---
+name: test2
+tracksRegLiveness: true
+body: |
+  ; CHECK-LABEL: name: test2
+  ; Verify that we can have multiple lists of liveins that will be merged into
+  ; one.
+  ; CHECK:       bb.0.body:
+  ; CHECK-NEXT:    liveins: %edi, %esi
+  bb.0.body:
+    liveins: %edi
+    liveins: %esi
+
+    %eax = LEA64_32r killed %rdi, 1, killed %rsi, 0, _
+    RETQ %eax
+...
+---
+name: test3
+tracksRegLiveness: true
+body: |
+  ; Verify that we can have an empty list of liveins.
+  ; CHECK-LABEL: name: test3
+  ; CHECK:       bb.0.body:
+  ; CHECK-NEXT:    %eax = MOV32r0 implicit-def dead %eflags
+  bb.0.body:
+    liveins:
+
+    %eax = MOV32r0 implicit-def dead %eflags
+    RETQ killed %eax
+...

external/llvm-project/llvm/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir

@@ -0,0 +1,41 @@
+# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+
+--- |
+
+  define i32 @foo(i32 %a) {
+  entry:
+    %0 = icmp sle i32 %a, 10
+    br i1 %0, label %less, label %exit
+
+  less:                                             ; preds = %entry
+    ret i32 0
+
+  exit:                                             ; preds = %entry
+    ret i32 %a
+  }
+
+...
+---
+name:            foo
+tracksRegLiveness: true
+liveins:
+  - { reg: '%edi' }
+body: |
+  bb.0.entry:
+    successors: %bb.1.less, %bb.2.exit
+    liveins: %edi 44
+
+    CMP32ri8 %edi, 10, implicit-def %eflags
+    JG_1 %bb.2.exit, implicit killed %eflags
+
+  ; CHECK: [[@LINE+1]]:8: basic block definition should be located at the start of the line
+  less bb.1:
+    %eax = MOV32r0 implicit-def dead %eflags
+    RETQ killed %eax
+
+  bb.2.exit:
+    liveins: %edi
+
+    %eax = COPY killed %edi
+    RETQ killed %eax
+...

external/llvm-project/llvm/test/CodeGen/MIR/X86/block-address-operands.mir

@@ -0,0 +1,121 @@
+# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# This test ensures that the MIR parser parses the block address operands
+# correctly.
+
+--- |
+
+  @addr = global i8* null
+
+  define void @test() {
+  entry:
+    store volatile i8* blockaddress(@test, %block), i8** @addr
+    %val = load volatile i8*, i8** @addr
+    indirectbr i8* %val, [label %block]
+
+  block:
+    ret void
+  }
+
+  define void @test2() {
+  entry:
+    store volatile i8* blockaddress(@test2, %"quoted block"), i8** @addr
+    %val = load volatile i8*, i8** @addr
+    indirectbr i8* %val, [label %"quoted block"]
+
+  "quoted block":
+    ret void
+  }
+
+  define void @slot_in_other_function(i8** %addr) {
+  entry:
+    store volatile i8* blockaddress(@test3, %0), i8** %addr
+    ret void
+  }
+
+  define void @test3() {
+  entry:
+    store volatile i8* blockaddress(@test3, %0), i8** @addr
+    %val = load volatile i8*, i8** @addr
+    indirectbr i8* %val, [label %0]
+
+    ret void
+  }
+
+  define void @test4() {
+  entry:
+    store volatile i8* blockaddress(@test4, %block), i8** @addr
+    %val = load volatile i8*, i8** @addr
+    indirectbr i8* %val, [label %block]
+
+  block:
+    ret void
+  }
+
+...
+---
+name:            test
+body: |
+  bb.0.entry:
+    successors: %bb.1.block
+  ; CHECK: %rax = LEA64r %rip, 1, %noreg, blockaddress(@test, %ir-block.block), %noreg
+    %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block), _
+    MOV64mr %rip, 1, _, @addr, _, killed %rax
+    JMP64m %rip, 1, _, @addr, _
+
+  bb.1.block (address-taken):
+    RETQ
+...
+---
+name:            test2
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+    successors: %bb.1
+  ; CHECK: %rax = LEA64r %rip, 1, %noreg, blockaddress(@test2, %ir-block."quoted block"), %noreg
+    %rax = LEA64r %rip, 1, _, blockaddress(@test2, %ir-block."quoted block"), _
+    MOV64mr %rip, 1, _, @addr, _, killed %rax
+    JMP64m %rip, 1, _, @addr, _
+
+  bb.1 (address-taken):
+    RETQ
+...
+---
+name:            slot_in_other_function
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+    liveins: %rdi
+  ; CHECK-LABEL: name: slot_in_other_function
+  ; CHECK: %rax = LEA64r %rip, 1, %noreg, blockaddress(@test3, %ir-block.0), %noreg
+    %rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _
+    MOV64mr killed %rdi, 1, _, 0, _, killed %rax
+    RETQ
+...
+---
+name:            test3
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+    successors: %bb.1
+  ; CHECK-LABEL: name: test3
+  ; CHECK: %rax = LEA64r %rip, 1, %noreg, blockaddress(@test3, %ir-block.0), %noreg
+    %rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _
+    MOV64mr %rip, 1, _, @addr, _, killed %rax
+    JMP64m %rip, 1, _, @addr, _
+
+  bb.1 (address-taken):
+    RETQ
+...
+---
+name:            test4
+body: |
+  bb.0.entry:
+    successors: %bb.1.block
+  ; CHECK: %rax = LEA64r %rip, 1, %noreg, blockaddress(@test, %ir-block.block) + 2, %noreg
+    %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block) + 2, _
+    MOV64mr %rip, 1, _, @addr, _, killed %rax
+    JMP64m %rip, 1, _, @addr, _
+
+  bb.1.block (address-taken):
+    RETQ
+...

external/llvm-project/llvm/test/CodeGen/MIR/X86/branch-probabilities.mir

@@ -0,0 +1,18 @@
+# RUN: llc -o - %s -mtriple=x86_64-- -run-pass=none | FileCheck %s
+---
+# Check that branch probabilities are printed correctly as hex numbers.
+# CHECK-LABEL: name: test
+# CHECK: bb.0:
+# CHECK-NEXT: successors: %bb.1(0x66666666), %bb.2(0x1999999a)
+name: test
+body: |
+  bb.0:
+    successors: %bb.1(4), %bb.2(1)
+    JE_1 %bb.2, implicit undef %eflags
+
+  bb.1:
+    NOOP
+
+  bb.2:
+    RETQ undef %eax
+...

external/llvm-project/llvm/test/CodeGen/MIR/X86/callee-saved-info.mir

@@ -0,0 +1,96 @@
+# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# This test ensures that the MIR parser parses callee saved information in the
+# stack objects correctly.
+
+--- |
+
+  define i32 @compute(i32 %a) {
+  body:
+    ret i32 %a
+  }
+
+  define i32 @func(i32 %a) {
+  entry:
+    %b = alloca i32
+    store i32 %a, i32* %b
+    br label %check
+
+  check:
+    %comp = icmp sle i32 %a, 10
+    br i1 %comp, label %loop, label %exit
+
+  loop:
+    %c = load i32, i32* %b
+    %d = call i32 @compute(i32 %c)
+    %e = sub i32 %d, 1
+    store i32 %e, i32* %b
+    br label %check
+
+  exit:
+    ret i32 0
+  }
+
+...
+---
+name:            compute
+tracksRegLiveness: true
+body: |
+  bb.0.body:
+    liveins: %edi
+
+    %eax = COPY killed %edi
+    RETQ killed %eax
+...
+---
+name:            func
+tracksRegLiveness: true
+frameInfo:
+  stackSize:       24
+  maxAlignment:    4
+  adjustsStack:    true
+  hasCalls:        true
+# CHECK: fixedStack:
+# CHECK: callee-saved-register: '%rbx', callee-saved-restored: true }
+fixedStack:
+  - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '%rbx' }
+# CHECK: stack:
+# CHECK-NEXT: - { id: 0
+# CHECK: callee-saved-register: '%edi', callee-saved-restored: false
+stack:
+  - { id: 0, name: b, offset: -20, size: 4, alignment: 4 }
+  - { id: 1, offset: -24, size: 4, alignment: 4, callee-saved-register: '%edi',
+      callee-saved-restored: false }
+body: |
+  bb.0.entry:
+    successors: %bb.1.check
+    liveins: %edi, %rbx
+
+    frame-setup PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp
+    %rsp = frame-setup SUB64ri8 %rsp, 16, implicit-def dead %eflags
+    %ebx = COPY %edi
+    MOV32mr %rsp, 1, _, 12, _, %ebx
+
+  bb.1.check:
+    successors: %bb.2.loop, %bb.3.exit
+    liveins: %ebx
+
+    CMP32ri8 %ebx, 10, implicit-def %eflags
+    JG_1 %bb.3.exit, implicit killed %eflags
+    JMP_1 %bb.2.loop
+
+  bb.2.loop:
+    successors: %bb.1.check
+    liveins: %ebx
+
+    %edi = MOV32rm %rsp, 1, _, 12, _
+    CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax
+    %eax = DEC32r killed %eax, implicit-def dead %eflags
+    MOV32mr %rsp, 1, _, 12, _, killed %eax
+    JMP_1 %bb.1.check
+
+  bb.3.exit:
+    %eax = MOV32r0 implicit-def dead %eflags
+    %rsp = ADD64ri8 %rsp, 16, implicit-def dead %eflags
+    %rbx = POP64r implicit-def %rsp, implicit %rsp
+    RETQ %eax
+...

external/llvm-project/llvm/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir

@@ -0,0 +1,29 @@
+# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# This test ensures that the MIR parser parses the cfi offset operands
+# correctly.
+
+--- |
+
+  define void @test() {
+  entry:
+    %tmp = alloca [4168 x i8], align 4
+    ret void
+  }
+
+...
+---
+name:            test
+tracksRegLiveness: true
+frameInfo:
+  stackSize:       4040
+stack:
+  - { id: 0, name: tmp, offset: -4176, size: 4168, alignment: 4 }
+body: |
+  bb.0.entry:
+    %rsp = SUB64ri32 %rsp, 4040, implicit-def dead %eflags
+    ; CHECK: CFI_INSTRUCTION def_cfa_offset 4048
+    CFI_INSTRUCTION def_cfa_offset 4048
+    %rsp = ADD64ri32 %rsp, 4040, implicit-def dead %eflags
+    RETQ
+...
+

external/llvm-project/llvm/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir

@@ -0,0 +1,32 @@
+# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# This test ensures that the MIR parser parses the cfi def_cfa_register
+# operands correctly.
+
+--- |
+
+  define void @func() #0 {
+  entry:
+    unreachable
+  }
+
+  attributes #0 = { "no-frame-pointer-elim"="true" }
+
+...
+---
+name:            func
+tracksRegLiveness: true
+frameInfo:
+  stackSize:     8
+fixedStack:
+  - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 }
+body: |
+  bb.0.entry:
+    liveins: %rbp
+
+    PUSH64r killed %rbp, implicit-def %rsp, implicit %rsp
+    CFI_INSTRUCTION def_cfa_offset 16
+    CFI_INSTRUCTION offset %rbp, -16
+    %rbp = MOV64rr %rsp
+    ; CHECK: CFI_INSTRUCTION def_cfa_register %rbp
+    CFI_INSTRUCTION def_cfa_register %rbp
+...

external/llvm-project/llvm/test/CodeGen/MIR/X86/cfi-offset.mir

@@ -0,0 +1,47 @@
+# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# This test ensures that the MIR parser parses the cfi offset operands
+# correctly.
+
+--- |
+
+  declare void @foo(i32)
+
+  define i32 @test(i32 %a, i32 %b, i32 %c, i32 %d) {
+  entry:
+    %add = add nsw i32 %b, %a
+    %add1 = add nsw i32 %add, %c
+    %add2 = add nsw i32 %add1, %d
+    tail call void @foo(i32 %add2)
+    %add6 = add nsw i32 %add2, %add2
+    ret i32 %add6
+  }
+
+...
+---
+name:            test
+tracksRegLiveness: true
+frameInfo:
+  stackSize:       8
+  adjustsStack:    true
+  hasCalls:        true
+fixedStack:
+  - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 }
+body: |
+  bb.0.entry:
+    liveins: %ecx, %edi, %edx, %esi, %rbx
+
+    PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp
+    CFI_INSTRUCTION def_cfa_offset 16
+    ; CHECK: CFI_INSTRUCTION offset %rbx, -16
+    CFI_INSTRUCTION offset %rbx, -16
+    %ebx = COPY %edi, implicit-def %rbx
+    %ebx = ADD32rr %ebx, killed %esi, implicit-def dead %eflags
+    %ebx = ADD32rr %ebx, killed %edx, implicit-def dead %eflags
+    %ebx = ADD32rr %ebx, killed %ecx, implicit-def dead %eflags
+    %edi = COPY %ebx
+    CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp
+    %eax = LEA64_32r killed %rbx, 1, %rbx, 0, _
+    %rbx = POP64r implicit-def %rsp, implicit %rsp
+    RETQ %eax
+...
+

external/llvm-project/llvm/test/CodeGen/MIR/X86/constant-pool-item-redefinition-error.mir

@@ -0,0 +1,25 @@
+# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+
+--- |
+
+  define double @test(double %a, float %b) {
+  entry:
+    %c = fadd double %a, 3.250000e+00
+    ret double %c
+  }
+
+...
+---
+name:            test
+constants:
+  - id:          0
+    value:       'double 3.250000e+00'
+# CHECK: [[@LINE+1]]:18: redefinition of constant pool item '%const.0'
+  - id:          0
+    value:       'double 3.250000e+00'
+body: |
+  bb.0.entry:
+    %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
+    RETQ %xmm0
+...
+

external/llvm-project/llvm/test/CodeGen/MIR/X86/constant-pool.mir

@@ -0,0 +1,145 @@
+# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# This test ensures that the MIR parser parses constant pool constants and
+# constant pool operands correctly.
+
+--- |
+
+  define double @test(double %a, float %b) {
+  entry:
+    %c = fadd double %a, 3.250000e+00
+    %d = fadd float %b, 6.250000e+00
+    %e = fpext float %d to double
+    %f = fmul double %c, %e
+    ret double %f
+  }
+
+  define double @test2(double %a, float %b) {
+  entry:
+    %c = fadd double %a, 3.250000e+00
+    %d = fadd float %b, 6.250000e+00
+    %e = fpext float %d to double
+    %f = fmul double %c, %e
+    ret double %f
+  }
+
+  define double @test3(double %a, float %b) {
+  entry:
+    %c = fadd double %a, 3.250000e+00
+    %d = fadd float %b, 6.250000e+00
+    %e = fpext float %d to double
+    %f = fmul double %c, %e
+    ret double %f
+  }
+
+  define double @test4(double %a, float %b) {
+  entry:
+    %c = fadd double %a, 3.250000e+00
+    %d = fadd float %b, 6.250000e+00
+    %e = fpext float %d to double
+    %f = fmul double %c, %e
+    ret double %f
+  }
+...
+---
+# CHECK: name: test
+# CHECK: constants:
+# CHECK-NEXT: - id: 0
+# CHECK-NEXT:   value: 'double 3.250000e+00'
+# CHECK-NEXT:   alignment: 8
+# CHECK-NEXT:   isTargetSpecific: false
+# CHECK-NEXT: - id: 1
+# CHECK-NEXT:   value: 'float 6.250000e+00'
+# CHECK-NEXT:   alignment: 4
+# CHECK-NEXT:   isTargetSpecific: false
+name:            test
+constants:
+  - id:          0
+    value:       'double 3.250000e+00'
+    alignment:   8
+  - id:          1
+    value:       'float 6.250000e+00'
+    alignment:   4
+body: |
+  bb.0.entry:
+    ; CHECK:      %xmm0 = ADDSDrm killed %xmm0, %rip, 1, %noreg, %const.0, %noreg
+    ; CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, %noreg, %const.1, %noreg
+    %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
+    %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _
+    %xmm1 = CVTSS2SDrr killed %xmm1
+    %xmm0 = MULSDrr killed %xmm0, killed %xmm1
+    RETQ %xmm0
+...
+---
+# Verify that alignment can be inferred:
+# CHECK: name: test2
+# CHECK: constants:
+# CHECK-NEXT: - id: 0
+# CHECK-NEXT:   value: 'double 3.250000e+00'
+# CHECK-NEXT:   alignment: 8
+# CHECK-NEXT:   isTargetSpecific: false
+# CHECK-NEXT: - id: 1
+# CHECK-NEXT:   value: 'float 6.250000e+00'
+# CHECK-NEXT:   alignment: 4
+# CHECK-NEXT:   isTargetSpecific: false
+name:            test2
+constants:
+  - id:          0
+    value:       'double 3.250000e+00'
+  - id:          1
+    value:       'float 6.250000e+00'
+body: |
+  bb.0.entry:
+    %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
+    %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _
+    %xmm1 = CVTSS2SDrr killed %xmm1
+    %xmm0 = MULSDrr killed %xmm0, killed %xmm1
+    RETQ %xmm0
+...
+---
+# Verify that the non-standard alignments are respected:
+# CHECK: name: test3
+# CHECK: constants:
+# CHECK-NEXT: - id: 0
+# CHECK-NEXT:   value: 'double 3.250000e+00'
+# CHECK-NEXT:   alignment: 128
+# CHECK-NEXT:   isTargetSpecific: false
+# CHECK-NEXT: - id: 1
+# CHECK-NEXT:   value: 'float 6.250000e+00'
+# CHECK-NEXT:   alignment: 1
+# CHECK-NEXT:   isTargetSpecific: false
+name:            test3
+constants:
+  - id:          0
+    value:       'double 3.250000e+00'
+    alignment:   128
+  - id:          1
+    value:       'float 6.250000e+00'
+    alignment:   1
+body: |
+  bb.0.entry:
+    ; CHECK:      %xmm0 = ADDSDrm killed %xmm0, %rip, 1, %noreg, %const.0, %noreg
+    ; CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, %noreg, %const.1, %noreg
+    %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
+    %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _
+    %xmm1 = CVTSS2SDrr killed %xmm1
+    %xmm0 = MULSDrr killed %xmm0, killed %xmm1
+    RETQ %xmm0
+...
+---
+# CHECK:  name:  test4
+name:            test4
+constants:
+  - id:          0
+    value:       'double 3.250000e+00'
+  - id:          1
+    value:       'float 6.250000e+00'
+body: |
+  bb.0.entry:
+    ; CHECK:      %xmm0 = ADDSDrm killed %xmm0, %rip, 1, %noreg, %const.1 - 12, %noreg
+    ; CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, %noreg, %const.0 + 8, %noreg
+    %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.1 - 12, _
+    %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.0 + 8, _
+    %xmm1 = CVTSS2SDrr killed %xmm1
+    %xmm0 = MULSDrr killed %xmm0, killed %xmm1
+    RETQ %xmm0
+...

external/llvm-project/llvm/test/CodeGen/MIR/X86/constant-value-error.mir

@@ -0,0 +1,25 @@
+# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# This test ensures that the MIR parser reports an error when parsing an invalid
+# constant value.
+
+--- |
+
+  define double @test(double %a, float %b) {
+  entry:
+    %c = fadd double %a, 3.250000e+00
+    ret double %c
+  }
+
+...
+---
+name:            test
+constants:
+  - id:          0
+  # CHECK: [[@LINE+1]]:19: expected type
+    value:       'dub 3.250000e+00'
+body: |
+  bb.0.entry:
+    %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
+    RETQ %xmm0
+...
+

external/llvm-project/llvm/test/CodeGen/MIR/X86/dead-register-flag.mir

@@ -0,0 +1,24 @@
+# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# This test ensures that the MIR parser parses the 'dead' register flags
+# correctly.
+
+--- |
+
+  define i32 @foo(i32 %a) #0 {
+  body:
+    %c = mul i32 %a, 11
+    ret i32 %c
+  }
+
+  attributes #0 = { "no-frame-pointer-elim"="false" }
+
+...
+---
+name:            foo
+body: |
+  ; CHECK: bb.0.body:
+  bb.0.body:
+    ; CHECK: %eax = IMUL32rri8 %edi, 11, implicit-def dead %eflags
+    %eax = IMUL32rri8 %edi, 11, implicit-def dead %eflags
+    RETQ %eax
+...

external/llvm-project/llvm/test/CodeGen/MIR/X86/def-register-already-tied-error.mir

@@ -0,0 +1,24 @@
+# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+--- |
+  define i64 @test(i64 %x) #0 {
+  entry:
+    %asm = tail call i64 asm sideeffect "$foo", "=r,0"(i64 %x) nounwind
+    ret i64 %asm
+  }
+
+  attributes #0 = { nounwind }
+...
+---
+name:            test
+tracksRegLiveness: true
+liveins:
+  - { reg: '%rdi' }
+body: |
+  bb.0.entry:
+    liveins: %rdi
+
+  ; CHECK: [[@LINE+1]]:83: the tied-def operand #3 is already tied with another register operand
+    INLINEASM $"$foo", 1, 2818058, def %rdi, 2147483657, killed %rdi(tied-def 3), killed %rdi(tied-def 3)
+    %rax = COPY killed %rdi
+    RETQ killed %rax
+...

external/llvm-project/llvm/test/CodeGen/MIR/X86/diexpr-win32.mir

@@ -0,0 +1,253 @@
+# RUN: llc -filetype=obj -O0 %s -o - | llvm-readobj -codeview | FileCheck %s
+#
+# (DW_OP_plus_uconst 12)
+# CHECK: LocalSym {
+# CHECK-NEXT:   Kind: S_LOCAL (0x113E)
+# CHECK-NEXT:   Type: string* (0x
+# CHECK-NEXT:   Flags [ (0x0)
+# CHECK-NEXT:   ]
+# CHECK-NEXT:   VarName: Str
+# CHECK-NEXT: }
+# CHECK-NEXT: DefRangeRegisterRelSym {
+# CHECK-NEXT:   Kind: S_DEFRANGE_REGISTER_REL (0x1145)
+# CHECK-NEXT:   BaseRegister:
+# CHECK-NEXT:   HasSpilledUDTMember: No
+# CHECK-NEXT:   OffsetInParent: 0
+# CHECK-NEXT:   BasePointerOffset: 12
+# CHECK-NEXT:   LocalVariableAddrRange {
+# CHECK-NEXT:     OffsetStart:
+# CHECK-NEXT:     ISectStart:
+# CHECK-NEXT:     Range:
+# CHECK-NEXT:   }
+# CHECK-NEXT: }
+# (DW_OP_plus_uconst, 8, DW_OP_deref)
+# CHECK: LocalSym {
+# CHECK-NEXT:   Kind: S_LOCAL (0x113E)
+# CHECK-NEXT:   Type: string& (0x
+# CHECK-NEXT:   Flags [ (0x0)
+# CHECK-NEXT:   ]
+# CHECK-NEXT:   VarName: Result
+# CHECK-NEXT: }
+# CHECK-NEXT: DefRangeRegisterRelSym {
+# CHECK-NEXT:   Kind: S_DEFRANGE_REGISTER_REL (0x1145)
+# CHECK-NEXT:   BaseRegister:
+# CHECK-NEXT:   HasSpilledUDTMember: No
+# CHECK-NEXT:   OffsetInParent: 0
+# CHECK-NEXT:   BasePointerOffset: 8
+# CHECK-NEXT:   LocalVariableAddrRange {
+# CHECK-NEXT:     OffsetStart:
+# CHECK-NEXT:     ISectStart:
+# CHECK-NEXT:     Range:
+# CHECK-NEXT:   }
+# CHECK-NEXT: }
+# (DW_OP_constu, 4, DW_OP_minus)
+# CHECK: LocalSym {
+# CHECK-NEXT:   Kind: S_LOCAL (0x113E)
+# CHECK-NEXT:   Type: long (0x12)
+# CHECK-NEXT:   Flags [ (0x0)
+# CHECK-NEXT:   ]
+# CHECK-NEXT:   VarName: Bytes
+# CHECK-NEXT: }
+# CHECK-NEXT: DefRangeRegisterRelSym {
+# CHECK-NEXT:   Kind: S_DEFRANGE_REGISTER_REL (0x1145)
+# CHECK-NEXT:   BaseRegister:
+# CHECK-NEXT:   HasSpilledUDTMember: No
+# CHECK-NEXT:   OffsetInParent: 0
+# CHECK-NEXT:   BasePointerOffset: -4
+# CHECK-NEXT:   LocalVariableAddrRange {
+# CHECK-NEXT:     OffsetStart:
+# CHECK-NEXT:     ISectStart:
+# CHECK-NEXT:     Range:
+# CHECK-NEXT:   }
+# CHECK-NEXT: }
+--- |
+  ; ModuleID = '<stdin>'
+  source_filename = "<stdin>"
+  target datalayout = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"
+  target triple = "i386-pc-windows-msvc19.0.24215"
+
+  %struct.string = type { i32, i32, i8* }
+
+  define void @fun(%struct.string* noalias sret %agg.result, %struct.string* noalias %str) !dbg !12 {
+  entry:
+    call void @llvm.dbg.value(metadata %struct.string* %agg.result, metadata !23, metadata !24), !dbg !25
+    call void @llvm.dbg.value(metadata %struct.string* %str, metadata !26, metadata !28), !dbg !25
+    %call = call dereferenceable(12) %struct.string* @getString(), !dbg !29
+    %0 = bitcast %struct.string* %agg.result to i8*, !dbg !29
+    %1 = bitcast %struct.string* %call to i8*, !dbg !29
+    call void @llvm.memcpy.p0i8.p0i8.i32(i8* %0, i8* %1, i32 12, i32 4, i1 false), !dbg !29
+    ret void, !dbg !30
+  }
+
+  define i32 @len(%struct.string* %s, i32 %acc) !dbg !31 {
+  entry:
+    %0 = bitcast %struct.string* %s to i32*
+    %bytes = load i32, i32* %0, !dbg !34
+    call void @llvm.dbg.declare(metadata i32 %bytes, metadata !35, metadata !28), !dbg !34
+    %1 = add i32 %bytes, %acc, !dbg !36
+    ret i32 %1, !dbg !36
+  }
+
+  ; Function Attrs: nounwind readnone speculatable
+  declare void @llvm.dbg.declare(metadata, metadata, metadata) #0
+
+  ; Function Attrs: nounwind readnone speculatable
+  declare void @llvm.dbg.value(metadata, metadata, metadata) #0
+
+  declare dereferenceable(12) %struct.string* @getString()
+
+  ; Function Attrs: argmemonly nounwind
+  declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture writeonly, i8* nocapture readonly, i32, i32, i1) #1
+
+  ; Function Attrs: nounwind
+  declare void @llvm.stackprotector(i8*, i8**) #2
+
+  attributes #0 = { nounwind readnone speculatable }
+  attributes #1 = { argmemonly nounwind }
+  attributes #2 = { nounwind }
+
+  !llvm.dbg.cu = !{!0}
+  !llvm.linker.options = !{!3, !4}
+  !llvm.module.flags = !{!5, !6, !7, !8}
+  !llvm.ident = !{!9}
+
+  !0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !1, producer: "clang version 6.0.0 ", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2)
+  !1 = !DIFile(filename: "diexpr.ll", directory: "C:\5Csrc", checksumkind: CSK_MD5, checksum: "c547c362c610fa79e7abaddc76e1efe7")
+  !2 = !{}
+  !3 = !{!"/DEFAULTLIB:libcmt.lib"}
+  !4 = !{!"/DEFAULTLIB:oldnames.lib"}
+  !5 = !{i32 1, !"NumRegisterParameters", i32 0}
+  !6 = !{i32 2, !"CodeView", i32 1}
+  !7 = !{i32 2, !"Debug Info Version", i32 3}
+  !8 = !{i32 1, !"wchar_size", i32 2}
+  !9 = !{!"clang version 6.0.0 "}
+  !10 = !DIExpression(DW_OP_plus_uconst, 12)
+  !11 = !DIExpression(DW_OP_plus_uconst, 8, DW_OP_deref)
+  !12 = distinct !DISubprogram(name: "fun", linkageName: "fun", scope: !1, file: !1, line: 9, type: !13, isLocal: false, isDefinition: true, scopeLine: 9, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2)
+  !13 = !DISubroutineType(types: !14)
+  !14 = !{!15}
+  !15 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "string", file: !1, line: 1, size: 96, elements: !16, identifier: ".?AUstring@@")
+  !16 = !{!17, !19, !20}
+  !17 = !DIDerivedType(tag: DW_TAG_member, name: "length", scope: !15, file: !1, line: 2, baseType: !18, size: 32)
+  !18 = !DIBasicType(name: "long int", size: 32, encoding: DW_ATE_signed)
+  !19 = !DIDerivedType(tag: DW_TAG_member, name: "size", scope: !15, file: !1, line: 3, baseType: !18, size: 32, offset: 32)
+  !20 = !DIDerivedType(tag: DW_TAG_member, name: "data", scope: !15, file: !1, line: 4, baseType: !21, size: 32, offset: 64)
+  !21 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !22, size: 32)
+  !22 = !DIBasicType(name: "char", size: 8, encoding: DW_ATE_signed_char)
+  !23 = !DILocalVariable(name: "Result", scope: !12, file: !1, line: 10, type: !15)
+  !24 = !DIExpression(DW_OP_deref)
+  !25 = !DILocation(line: 10, scope: !12)
+  !26 = !DILocalVariable(name: "Str", scope: !12, file: !1, line: 10, type: !27)
+  !27 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !15, size: 32)
+  !28 = !DIExpression(DW_OP_constu, 4, DW_OP_minus)
+  !29 = !DILocation(line: 11, scope: !12)
+  !30 = !DILocation(line: 12, scope: !12)
+  !31 = distinct !DISubprogram(name: "len", linkageName: "len", scope: !1, file: !1, line: 14, type: !32, isLocal: false, isDefinition: true, scopeLine: 14, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2)
+  !32 = !DISubroutineType(types: !33)
+  !33 = !{!18}
+  !34 = !DILocation(line: 15, scope: !31)
+  !35 = !DILocalVariable(name: "Bytes", scope: !31, file: !1, line: 15, type: !18)
+  !36 = !DILocation(line: 16, scope: !31)
+
+...
+---
+name:            fun
+alignment:       4
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+liveins:
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       4
+  offsetAdjustment: 0
+  maxAlignment:    4
+  adjustsStack:    true
+  hasCalls:        true
+  stackProtector:  ''
+  maxCallFrameSize: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:
+  - { id: 0, type: spill-slot, offset: -8, size: 4, alignment: 4, stack-id: 0,
+      callee-saved-register: '%esi' }
+  - { id: 1, type: default, offset: 4, size: 4, alignment: 4, stack-id: 0,
+      isImmutable: true, isAliased: false, callee-saved-register: '' }
+  - { id: 2, type: default, offset: 0, size: 4, alignment: 4, stack-id: 0,
+      isImmutable: true, isAliased: false, callee-saved-register: '' }
+stack:
+constants:
+body:             |
+  bb.0.entry:
+    liveins: %esi
+
+    frame-setup PUSH32r killed %esi, implicit-def %esp, implicit %esp
+    CFI_INSTRUCTION def_cfa_offset 8
+    CFI_INSTRUCTION offset %esi, -8
+    %esi = MOV32rm %esp, 1, _, 8, _ :: (load 4 from %fixed-stack.2)
+    DBG_VALUE %esp, 0, !26, !10, debug-location !25
+    DBG_VALUE %esp, 0, !23, !DIExpression(DW_OP_plus_uconst, 8, DW_OP_deref), debug-location !25
+    CALLpcrel32 @getString, csr_32, implicit %esp, implicit-def %esp, implicit-def %eax, debug-location !29
+    %ecx = MOV32rm %eax, 1, _, 0, _, debug-location !29 :: (dereferenceable load 4 from %ir.1)
+    %edx = MOV32rm %eax, 1, _, 4, _, debug-location !29 :: (dereferenceable load 4 from %ir.1 + 4)
+    MOV32mr %esi, 1, _, 0, _, killed %ecx, debug-location !29 :: (store 4 into %ir.0)
+    MOV32mr %esi, 1, _, 4, _, killed %edx, debug-location !29 :: (store 4 into %ir.0 + 4)
+    %eax = MOV32rm killed %eax, 1, _, 8, _, debug-location !29 :: (dereferenceable load 4 from %ir.1 + 8)
+    MOV32mr %esi, 1, _, 8, _, killed %eax, debug-location !29 :: (store 4 into %ir.0 + 8)
+    %eax = COPY killed %esi, debug-location !30
+    %esi = POP32r implicit-def %esp, implicit %esp, debug-location !30
+    RET 0, %eax, debug-location !30
+
+...
+---
+name:            len
+alignment:       4
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+liveins:
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    4
+  adjustsStack:    false
+  hasCalls:        false
+  stackProtector:  ''
+  maxCallFrameSize: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:
+  - { id: 0, type: default, offset: 4, size: 4, alignment: 4, stack-id: 0,
+      isImmutable: true, isAliased: false, callee-saved-register: '' }
+  - { id: 1, type: default, offset: 0, size: 4, alignment: 4, stack-id: 0,
+      isImmutable: true, isAliased: false, callee-saved-register: '' }
+stack:
+constants:
+body:             |
+  bb.0.entry:
+    %eax = MOV32rm %esp, 1, _, 4, _ :: (load 4 from %fixed-stack.1)
+    %eax = MOV32rm killed %eax, 1, _, 0, _, debug-location !34 :: (load 4 from %ir.0)
+    DBG_VALUE debug-use %eax, 0, !35, !DIExpression(DW_OP_constu, 4, DW_OP_minus), debug-location !34
+    %eax = ADD32rm killed %eax, %esp, 1, _, 8, _, implicit-def dead %eflags, debug-location !36 :: (load 4 from %fixed-stack.0)
+    RET 0, %eax, debug-location !36
+
+...

external/llvm-project/llvm/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir

@@ -0,0 +1,27 @@
+# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+
+--- |
+
+  define i32 @volatile_inc(i32* %x) {
+  entry:
+    %0 = load volatile i32, i32* %x
+    %1 = add i32 %0, 1
+    store volatile i32 %1, i32* %x
+    ret i32 %1
+  }
+
+...
+---
+name:            volatile_inc
+tracksRegLiveness: true
+liveins:
+  - { reg: '%rdi' }
+body: |
+  bb.0.entry:
+    liveins: %rdi
+  ; CHECK: [[@LINE+1]]:50: duplicate 'volatile' memory operand flag
+    %eax = MOV32rm %rdi, 1, _, 0, _ :: (volatile volatile load 4 from %ir.x)
+    %eax = INC32r killed %eax, implicit-def dead %eflags
+    MOV32mr killed %rdi, 1, _, 0, _, %eax :: (volatile store 4 into %ir.x)
+    RETQ %eax
+...

external/llvm-project/llvm/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir

@@ -0,0 +1,35 @@
+# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+
+--- |
+
+  define i32 @foo(i32 %a) {
+  entry:
+    %0 = icmp sle i32 %a, 10
+    br i1 %0, label %less, label %exit
+
+  less:
+    ret i32 0
+
+  exit:
+    ret i32 %a
+  }
+
+...
+---
+name:            foo
+body: |
+  bb.0.entry:
+    successors: %bb.1.less, %bb.2.exit
+
+    CMP32ri8 %edi, 10, implicit-def %eflags
+  ; CHECK: [[@LINE+1]]:31: duplicate 'implicit' register flag
+    JG_1 %bb.2.exit, implicit implicit %eflags
+
+  bb.1.less:
+    %eax = MOV32r0 implicit-def %eflags
+    RETQ %eax
+
+  bb.2.exit:
+    %eax = COPY %edi
+    RETQ %eax
+...

external/llvm-project/llvm/test/CodeGen/MIR/X86/dynamic-regmask.ll

@@ -0,0 +1,30 @@
+; RUN: llc -mtriple=x86_64-pc-win32 -stop-after machine-sink %s -o %t.mir
+; RUN: FileCheck %s < %t.mir
+; RUN: llc %t.mir -mtriple=x86_64-pc-win32 -run-pass machine-sink
+; Check that callee saved registers are printed in a format that can then be parsed.
+
+declare x86_regcallcc i32 @callee(i32 %a0, i32 %b0, i32 %c0, i32 %d0, i32 %e0)
+
+define i32 @caller(i32 %a0) nounwind {
+  %b1 = call x86_regcallcc i32 @callee(i32 %a0, i32 %a0, i32 %a0, i32 %a0, i32 %a0)
+  %b2 = add i32 %b1, %a0
+  ret i32 %b2
+}
+; CHECK:    name: caller
+; CHECK:    CALL64pcrel32 @callee, CustomRegMask(%bh,%bl,%bp,%bpl,%bx,%ebp,%ebx,%esp,%rbp,%rbx,%rsp,%sp,%spl,%r10,%r11,%r12,%r13,%r14,%r15,%xmm8,%xmm9,%xmm10,%xmm11,%xmm12,%xmm13,%xmm14,%xmm15,%r10b,%r11b,%r12b,%r13b,%r14b,%r15b,%r10d,%r11d,%r12d,%r13d,%r14d,%r15d,%r10w,%r11w,%r12w,%r13w,%r14w,%r15w)
+; CHECK:    RET 0, %eax
+
+define x86_regcallcc {i32, i32, i32} @test_callee(i32 %a0, i32 %b0, i32 %c0, i32 %d0, i32 %e0) nounwind {
+  %b1 = mul i32 7, %e0
+  %b2 = udiv i32 5, %e0
+  %b3 = mul i32 7, %d0
+  %b4 = insertvalue {i32, i32, i32} undef, i32 %b1, 0
+  %b5 = insertvalue {i32, i32, i32} %b4, i32 %b2, 1
+  %b6 = insertvalue {i32, i32, i32} %b5, i32 %b3, 2
+  ret {i32, i32, i32} %b6
+}
+; CHECK: name:            test_callee
+; CHECK: calleeSavedRegisters: [ '%rbx', '%rbp', '%rsp', '%r10', '%r11', '%r12',
+; CHECK:                         '%r13', '%r14', '%r15', '%xmm8', '%xmm9', '%xmm10',
+; CHECK:                         '%xmm11', '%xmm12', '%xmm13', '%xmm14', '%xmm15' ]
+; CHECK: RET 0, %eax, %ecx, %edx

external/llvm-project/llvm/test/CodeGen/MIR/X86/early-clobber-register-flag.mir

@@ -0,0 +1,44 @@
+# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# This test ensures that the MIR parser parses the 'early-clobber' register
+# flags correctly.
+
+--- |
+
+  declare void @foo(i32)
+
+  define void @test(i32 %a, i32 %b) #0 {
+  entry:
+    %c = add i32 %a, %b
+    call void asm sideeffect "nop", "~{ax},~{di}"()
+    call void @foo(i32 %c)
+    ret void
+  }
+
+  attributes #0 = { optsize }
+
+...
+---
+name:            test
+tracksRegLiveness: true
+liveins:
+  - { reg: '%edi' }
+  - { reg: '%esi' }
+frameInfo:
+  stackSize:     8
+  adjustsStack:  true
+  hasCalls:      true
+body: |
+  bb.0.entry:
+    liveins: %edi, %esi
+
+    frame-setup PUSH64r undef %rax, implicit-def %rsp, implicit %rsp
+    CFI_INSTRUCTION def_cfa_offset 16
+    %ecx = COPY %edi
+    %ecx = ADD32rr killed %ecx, killed %esi, implicit-def dead %eflags
+  ; CHECK: INLINEASM $nop, 1, 12, implicit-def dead early-clobber %ax, 12, implicit-def dead early-clobber %di
+    INLINEASM $nop, 1, 12, implicit-def dead early-clobber %ax, 12, implicit-def dead early-clobber %di
+    %edi = COPY killed %ecx
+    CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp
+    %rax = POP64r implicit-def %rsp, implicit %rsp
+    RETQ
+...

external/llvm-project/llvm/test/CodeGen/MIR/X86/empty0.mir

@@ -0,0 +1,6 @@
+# RUN: llc -run-pass none -o - %s | FileCheck %s
+# Make sure empty files don't crash us
+# CHECK: --- |
+# ... moduleid, sourcefilename stuff here ..
+# CHECK: target datalayout =
+# CHECK: ...