Imported Upstream version 6.10.0.49

Former-commit-id: 1d6753294b2993e1fbf92de9366bb9544db4189b

external/llvm-project/llvm/test/CodeGen/AVR/pseudo/ADCWRdRr.mir

@@ -0,0 +1,24 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
+
+# This test checks the expansion of the 16-bit add with carry pseudo instruction.
+
+--- |
+  target triple = "avr--"
+  define void @test_adcwrdrr() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test_adcwrdrr
+body: |
+  bb.0.entry:
+
+    ; CHECK-LABEL: test_adcwrdrr
+
+    ; CHECK:       %r14 = ADCRdRr %r14, %r20, implicit-def %sreg, implicit %sreg
+    ; CHECK-LABEL: %r15 = ADCRdRr %r15, %r21, implicit-def %sreg, implicit killed %sreg
+
+    %r15r14 = ADCWRdRr %r15r14, %r21r20, implicit-def %sreg, implicit %sreg
+...

external/llvm-project/llvm/test/CodeGen/AVR/pseudo/ADDWRdRr.mir

@@ -0,0 +1,24 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
+
+# This test checks the expansion of the 16-bit add pseudo instruction.
+
+--- |
+  target triple = "avr--"
+  define void @test_addwrdrr() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test_addwrdrr
+body: |
+  bb.0.entry:
+
+    ; CHECK-LABEL: test_addwrdrr
+
+    ; CHECK:       %r14 = ADDRdRr %r14, %r20, implicit-def %sreg
+    ; CHECK-LABEL: %r15 = ADCRdRr %r15, %r21, implicit-def %sreg, implicit killed %sreg
+
+    %r15r14 = ADDWRdRr %r15r14, %r21r20, implicit-def %sreg
+...

external/llvm-project/llvm/test/CodeGen/AVR/pseudo/ANDIWRdK.mir

@@ -0,0 +1,24 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
+
+# This test checks the expansion of the 16-bit ANDO pseudo instruction.
+
+--- |
+  target triple = "avr--"
+  define void @test_andiwrdrr() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test_andiwrdrr
+body: |
+  bb.0.entry:
+
+    ; CHECK-LABEL: test_andiwrdrr
+
+    ; CHECK:      %r16 = ANDIRdK %r16, 175, implicit-def dead %sreg
+    ; CHECK-NEXT: %r17 = ANDIRdK %r17, 250, implicit-def %sreg
+
+    %r17r16 = ANDIWRdK %r17r16, 64175, implicit-def %sreg
+...

external/llvm-project/llvm/test/CodeGen/AVR/pseudo/ANDWRdRr.mir

@@ -0,0 +1,24 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
+
+# This test checks the expansion of the 16-bit AND pseudo instruction.
+
+--- |
+  target triple = "avr--"
+  define void @test_andwrdrr() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test_andwrdrr
+body: |
+  bb.0.entry:
+
+    ; CHECK-LABEL: test_andwrdrr
+
+    ; CHECK:      %r14 = ANDRdRr %r14, %r20, implicit-def dead %sreg
+    ; CHECK-NEXT: %r15 = ANDRdRr %r15, %r21, implicit-def %sreg
+
+    %r15r14 = ANDWRdRr %r15r14, %r21r20, implicit-def %sreg
+...

external/llvm-project/llvm/test/CodeGen/AVR/pseudo/ASRWRd.mir

@@ -0,0 +1,22 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
+
+--- |
+  target triple = "avr--"
+  define void @test() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test
+body: |
+  bb.0.entry:
+
+    ; CHECK-LABEL: test
+
+    ; CHECK:      %r15 = ASRRd %r15, implicit-def %sreg
+    ; CHECK-NEXT: %r14 = RORRd %r14, implicit-def %sreg, implicit killed %sreg
+
+    %r15r14 = ASRWRd %r15r14, implicit-def %sreg
+...

external/llvm-project/llvm/test/CodeGen/AVR/pseudo/COMWRd.mir

@@ -0,0 +1,24 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
+
+# This test checks the expansion of the 16-bit COM pseudo instruction.
+
+--- |
+  target triple = "avr--"
+  define void @test_comwrd() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test_comwrd
+body: |
+  bb.0.entry:
+
+    ; CHECK-LABEL: test_comwrd
+
+    ; CHECK:      %r14 = COMRd %r14, implicit-def dead %sreg
+    ; CHECK-NEXT: %r15 = COMRd %r15, implicit-def %sreg
+
+    %r15r14 = COMWRd %r15r14, implicit-def %sreg
+...

external/llvm-project/llvm/test/CodeGen/AVR/pseudo/CPCWRdRr.mir

@@ -0,0 +1,24 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
+
+# This test checks the expansion of the 16-bit CPCW pseudo instruction.
+
+--- |
+  target triple = "avr--"
+  define void @test_cpcwrdrr() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test_cpcwrdrr
+body: |
+  bb.0.entry:
+
+    ; CHECK-LABEL: test_cpcwrdrr
+
+    ; CHECK:      CPCRdRr %r20, %r22, implicit-def %sreg, implicit killed %sreg
+    ; CHECK-NEXT: CPCRdRr %r21, %r23, implicit-def %sreg, implicit killed %sreg
+
+    CPCWRdRr %r21r20, %r23r22, implicit-def %sreg, implicit %sreg
+...

external/llvm-project/llvm/test/CodeGen/AVR/pseudo/CPWRdRr.mir

@@ -0,0 +1,24 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
+
+# This test checks the expansion of the 16-bit CPW pseudo instruction.
+
+--- |
+  target triple = "avr--"
+  define void @test_cpwrdrr() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test_cpwrdrr
+body: |
+  bb.0.entry:
+
+    ; CHECK-LABEL: test_cpwrdrr
+
+    ; CHECK:      CPRdRr %r14, %r20, implicit-def %sreg
+    ; CHECK-NEXT: CPCRdRr %r15, %r21, implicit-def %sreg, implicit killed %sreg
+
+    CPWRdRr %r15r14, %r21r20, implicit-def %sreg
+...

external/llvm-project/llvm/test/CodeGen/AVR/pseudo/EORWRdRr.mir

@@ -0,0 +1,24 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
+
+# This test checks the expansion of the 16-bit EOR pseudo instruction.
+
+--- |
+  target triple = "avr--"
+  define void @test_eorwrdrr() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test_eorwrdrr
+body: |
+  bb.0.entry:
+
+    ; CHECK-LABEL: test_eorwrdrr
+
+    ; CHECK:      %r14 = EORRdRr %r14, %r20, implicit-def dead %sreg
+    ; CHECK-NEXT: %r15 = EORRdRr %r15, %r21, implicit-def %sreg
+
+    %r15r14 = EORWRdRr %r15r14, %r21r20, implicit-def %sreg
+...

external/llvm-project/llvm/test/CodeGen/AVR/pseudo/FRMIDX.mir

@@ -0,0 +1,25 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
+
+# TODO: Write this test.
+# This instruction isn't expanded by the pseudo expansion passs, but
+# rather AVRRegisterInfo::eliminateFrameIndex.
+
+--- |
+  target triple = "avr--"
+  define void @test() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test
+registers:
+  - { id: 0, class: _ }
+body: |
+  bb.0.entry:
+
+    ; CHECK-LABEL: test
+
+    %r29r28 = FRMIDX %r31r30, 0, implicit-def %sreg
+...

external/llvm-project/llvm/test/CodeGen/AVR/pseudo/INWRdA.mir

@@ -0,0 +1,22 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
+
+--- |
+  target triple = "avr--"
+  define void @test() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test
+body: |
+  bb.0.entry:
+
+    ; CHECK-LABEL: test
+
+    ; CHECK:      %r14 = INRdA 31
+    ; CHECK-NEXT: %r15 = INRdA 32
+
+    %r15r14 = INWRdA 31
+...

external/llvm-project/llvm/test/CodeGen/AVR/pseudo/LDDWRdPtrQ-same-src-dst.mir

@@ -0,0 +1,35 @@
+# RUN: llc -O0  %s -o - -march=avr | FileCheck %s
+
+# This test checks the expansion of the 16-bit 'LDDWRdPtrQ' pseudo instruction.
+#
+# This test ensures that the pseudo expander can correctly handle the case
+# where we are expanding a 16-bit LDD instruction where the source and
+# destination registers are the same.
+#
+# The instruction itself is earlyclobber and so ISel will never produce an
+# instruction like this, but the stack slot loading can and will.
+
+--- |
+  target triple = "avr--"
+  define void @test_lddwrdptrq() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test_lddwrdptrq
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+
+    ; CHECK-LABEL: test_lddwrdptrq
+
+    ; CHECK:      ldd [[SCRATCH:r[0-9]+]], Z+10
+    ; CHECK-NEXT: push [[SCRATCH]]
+    ; CHECK-NEXT: ldd [[SCRATCH]], Z+11
+    ; CHECK-NEXT: mov r31, [[SCRATCH]]
+    ; CHECK-NEXT: pop r30
+
+    early-clobber %r31r30 = LDDWRdPtrQ undef %r31r30, 10
+...

external/llvm-project/llvm/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir

@@ -0,0 +1,25 @@
+# RUN: llc -O0  %s -o - -march=avr | FileCheck %s
+
+# This test checks the expansion of the 16-bit 'LDDWRdPtrQ' pseudo instruction.
+
+--- |
+  target triple = "avr--"
+  define void @test_lddwrdptrq() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test_lddwrdptrq
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+
+    ; CHECK-LABEL: test_lddwrdptrq
+
+    ; CHECK:      ldd     r30, Y+10
+    ; CHECK-NEXT: ldd     r31, Y+11
+
+    early-clobber %r31r30 = LDDWRdPtrQ undef %r29r28, 10
+...

external/llvm-project/llvm/test/CodeGen/AVR/pseudo/LDDWRdYQ.mir

@@ -0,0 +1,25 @@
+# RUN: llc -O0  %s -o - -march=avr | FileCheck %s
+
+# This test checks the expansion of the 16-bit 'LDDWRdYQ instruction
+
+--- |
+  target triple = "avr--"
+  define void @test_lddwrdyq() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test_lddwrdyq
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+
+    ; CHECK-LABEL: test_lddwrdyq
+
+    ; CHECK:      ldd     r30, Y+1
+    ; CHECK-NEXT: ldd     r31, Y+2
+
+    early-clobber %r31r30 = LDDWRdYQ undef %r29r28, 1
+...

external/llvm-project/llvm/test/CodeGen/AVR/pseudo/LDIWRdK.mir

@@ -0,0 +1,24 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
+
+# This test checks the expansion of the 16-bit LDIWRdK pseudo instruction.
+
+--- |
+  target triple = "avr--"
+  define void @test_ldiwrdrr() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test_ldiwrdrr
+body: |
+  bb.0.entry:
+
+    ; CHECK-LABEL: test_ldiwrdrr
+
+    ; CHECK:      %r30 = LDIRdK 255
+    ; CHECK-NEXT: %r31 = LDIRdK 9
+
+    %r31r30 = LDIWRdK 2559
+...

external/llvm-project/llvm/test/CodeGen/AVR/pseudo/LDSWRdK.mir

@@ -0,0 +1,24 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
+
+# This test checks the expansion of the 16-bit LDSWRdK pseudo instruction.
+
+--- |
+  target triple = "avr--"
+  define void @test_ldswrdrr() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test_ldswrdrr
+body: |
+  bb.0.entry:
+
+    ; CHECK-LABEL: test_ldswrdrr
+
+    ; CHECK:      %r30 = LDSRdK 2559
+    ; CHECK-NEXT: %r31 = LDSRdK 2560
+
+    %r31r30 = LDSWRdK 2559
+...

external/llvm-project/llvm/test/CodeGen/AVR/pseudo/LDWRdPtr-same-src-dst.mir

@@ -0,0 +1,29 @@
+# RUN: llc -O0 %s -o - | FileCheck %s
+
+# This test checks the expansion of the 16-bit LDWRdPtr pseudo instruction.
+
+--- |
+  target triple = "avr--"
+  define void @test_ldwrdptr() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test_ldwrdptr
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+
+    ; CHECK-LABEL: test_ldwrdptr
+
+    ; CHECK:      ld [[SCRATCH:r[0-9]+]], Z+
+    ; CHECK-NEXT: push [[SCRATCH]]
+    ; CHECK-NEXT: ld [[SCRATCH]], Z
+    ; CHECK-NEXT: mov r31, [[SCRATCH]]
+    ; CHECK-NEXT: pop r30
+
+    early-clobber %r31r30 = LDWRdPtr undef %r31r30
+...
+

external/llvm-project/llvm/test/CodeGen/AVR/pseudo/LDWRdPtr.mir

@@ -0,0 +1,24 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
+
+# This test checks the expansion of the 16-bit LDWRdPtr pseudo instruction.
+
+--- |
+  target triple = "avr--"
+  define void @test_ldwrdptr() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test_ldwrdptr
+body: |
+  bb.0.entry:
+
+    ; CHECK-LABEL: test_ldwrdptr
+
+    ; CHECK:      %r0, %r31r30 = LDRdPtrPi %r31r30
+    ; CHECK-NEXT:          %r1 = LDRdPtr %r31r30
+
+    %r1r0 = LDWRdPtr %r31r30
+...

external/llvm-project/llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir

@@ -0,0 +1,24 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
+
+# This test checks the expansion of the 16-bit LDWRdPtrPd pseudo instruction.
+
+--- |
+  target triple = "avr--"
+  define void @test_ldwrdptrpd() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test_ldwrdptrpd
+body: |
+  bb.0.entry:
+
+    ; CHECK-LABEL: test_ldwrdptrpd
+
+    ; CHECK:      early-clobber %r1, %r31r30 = LDRdPtrPd killed %r31r30
+    ; CHECK-NEXT: early-clobber %r0, %r31r30 = LDRdPtrPd killed %r31r30
+
+    %r1r0, %r31r30 = LDWRdPtrPd %r31r30
+...

external/llvm-project/llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir

@@ -0,0 +1,24 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
+
+# This test checks the expansion of the 16-bit LDWRdPtrPi pseudo instruction.
+
+--- |
+  target triple = "avr--"
+  define void @test_ldwrdptrpi() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test_ldwrdptrpi
+body: |
+  bb.0.entry:
+
+    ; CHECK-LABEL: test_ldwrdptrpi
+
+    ; CHECK:      early-clobber %r0, %r31r30 = LDRdPtrPi killed %r31r30
+    ; CHECK-NEXT: early-clobber %r1, %r31r30 = LDRdPtrPi killed %r31r30
+
+    %r1r0, %r31r30 = LDWRdPtrPi %r31r30
+...