Imported Upstream version 6.10.0.49

Former-commit-id: 1d6753294b2993e1fbf92de9366bb9544db4189b

external/llvm-project/lldb/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.h

@@ -0,0 +1,231 @@
+//===-- DNBArchImplI386.h ---------------------------------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+//  Created by Greg Clayton on 6/25/07.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef __DNBArchImplI386_h__
+#define __DNBArchImplI386_h__
+
+#if defined(__i386__) || defined(__x86_64__)
+
+#include "DNBArch.h"
+#include "MachRegisterStatesI386.h"
+
+#include <map>
+
+class MachThread;
+
+class DNBArchImplI386 : public DNBArchProtocol {
+public:
+  DNBArchImplI386(MachThread *thread)
+      : DNBArchProtocol(), m_thread(thread), m_state(), m_2pc_dbg_checkpoint(),
+        m_2pc_trans_state(Trans_Done), m_saved_register_states() {}
+  virtual ~DNBArchImplI386() {}
+
+  static void Initialize();
+
+  virtual bool GetRegisterValue(uint32_t set, uint32_t reg,
+                                DNBRegisterValue *value);
+  virtual bool SetRegisterValue(uint32_t set, uint32_t reg,
+                                const DNBRegisterValue *value);
+  virtual nub_size_t GetRegisterContext(void *buf, nub_size_t buf_len);
+  virtual nub_size_t SetRegisterContext(const void *buf, nub_size_t buf_len);
+  virtual uint32_t SaveRegisterState();
+  virtual bool RestoreRegisterState(uint32_t save_id);
+
+  virtual kern_return_t GetRegisterState(int set, bool force);
+  virtual kern_return_t SetRegisterState(int set);
+  virtual bool RegisterSetStateIsValid(int set) const;
+
+  virtual uint64_t GetPC(uint64_t failValue); // Get program counter
+  virtual kern_return_t SetPC(uint64_t value);
+  virtual uint64_t GetSP(uint64_t failValue); // Get stack pointer
+  virtual void ThreadWillResume();
+  virtual bool ThreadDidStop();
+  virtual bool NotifyException(MachException::Data &exc);
+
+  virtual uint32_t NumSupportedHardwareWatchpoints();
+  virtual uint32_t EnableHardwareWatchpoint(nub_addr_t addr, nub_size_t size,
+                                            bool read, bool write,
+                                            bool also_set_on_task);
+  virtual bool DisableHardwareWatchpoint(uint32_t hw_break_index,
+                                         bool also_set_on_task);
+  virtual uint32_t GetHardwareWatchpointHit(nub_addr_t &addr);
+
+protected:
+  kern_return_t EnableHardwareSingleStep(bool enable);
+
+  typedef __i386_thread_state_t GPR;
+  typedef __i386_float_state_t FPU;
+  typedef __i386_exception_state_t EXC;
+  typedef __i386_avx_state_t AVX;
+  typedef __i386_debug_state_t DBG;
+
+  static const DNBRegisterInfo g_gpr_registers[];
+  static const DNBRegisterInfo g_fpu_registers_no_avx[];
+  static const DNBRegisterInfo g_fpu_registers_avx[];
+  static const DNBRegisterInfo g_exc_registers[];
+  static const DNBRegisterSetInfo g_reg_sets_no_avx[];
+  static const DNBRegisterSetInfo g_reg_sets_avx[];
+  static const size_t k_num_gpr_registers;
+  static const size_t k_num_fpu_registers_no_avx;
+  static const size_t k_num_fpu_registers_avx;
+  static const size_t k_num_exc_registers;
+  static const size_t k_num_all_registers_no_avx;
+  static const size_t k_num_all_registers_avx;
+  static const size_t k_num_register_sets;
+
+  typedef enum RegisterSetTag {
+    e_regSetALL = REGISTER_SET_ALL,
+    e_regSetGPR,
+    e_regSetFPU,
+    e_regSetEXC,
+    e_regSetDBG,
+    kNumRegisterSets
+  } RegisterSet;
+
+  typedef enum RegisterSetWordSizeTag {
+    e_regSetWordSizeGPR = sizeof(GPR) / sizeof(int),
+    e_regSetWordSizeFPU = sizeof(FPU) / sizeof(int),
+    e_regSetWordSizeEXC = sizeof(EXC) / sizeof(int),
+    e_regSetWordSizeAVX = sizeof(AVX) / sizeof(int),
+    e_regSetWordSizeDBG = sizeof(DBG) / sizeof(int)
+  } RegisterSetWordSize;
+
+  enum { Read = 0, Write = 1, kNumErrors = 2 };
+
+  struct Context {
+    GPR gpr;
+    union {
+      FPU no_avx;
+      AVX avx;
+    } fpu;
+    EXC exc;
+    DBG dbg;
+  };
+
+  struct State {
+    Context context;
+    kern_return_t gpr_errs[2]; // Read/Write errors
+    kern_return_t fpu_errs[2]; // Read/Write errors
+    kern_return_t exc_errs[2]; // Read/Write errors
+    kern_return_t dbg_errs[2]; // Read/Write errors
+
+    State() {
+      uint32_t i;
+      for (i = 0; i < kNumErrors; i++) {
+        gpr_errs[i] = -1;
+        fpu_errs[i] = -1;
+        exc_errs[i] = -1;
+        dbg_errs[i] = -1;
+      }
+    }
+    void InvalidateAllRegisterStates() { SetError(e_regSetALL, Read, -1); }
+    kern_return_t GetError(int flavor, uint32_t err_idx) const {
+      if (err_idx < kNumErrors) {
+        switch (flavor) {
+        // When getting all errors, just OR all values together to see if
+        // we got any kind of error.
+        case e_regSetALL:
+          return gpr_errs[err_idx] | fpu_errs[err_idx] | exc_errs[err_idx];
+        case e_regSetGPR:
+          return gpr_errs[err_idx];
+        case e_regSetFPU:
+          return fpu_errs[err_idx];
+        case e_regSetEXC:
+          return exc_errs[err_idx];
+        case e_regSetDBG:
+          return dbg_errs[err_idx];
+        default:
+          break;
+        }
+      }
+      return -1;
+    }
+    bool SetError(int flavor, uint32_t err_idx, kern_return_t err) {
+      if (err_idx < kNumErrors) {
+        switch (flavor) {
+        case e_regSetALL:
+          gpr_errs[err_idx] = fpu_errs[err_idx] = exc_errs[err_idx] =
+              dbg_errs[err_idx] = err;
+          return true;
+
+        case e_regSetGPR:
+          gpr_errs[err_idx] = err;
+          return true;
+
+        case e_regSetFPU:
+          fpu_errs[err_idx] = err;
+          return true;
+
+        case e_regSetEXC:
+          exc_errs[err_idx] = err;
+          return true;
+
+        case e_regSetDBG:
+          dbg_errs[err_idx] = err;
+          return true;
+
+        default:
+          break;
+        }
+      }
+      return false;
+    }
+    bool RegsAreValid(int flavor) const {
+      return GetError(flavor, Read) == KERN_SUCCESS;
+    }
+  };
+
+  kern_return_t GetGPRState(bool force);
+  kern_return_t GetFPUState(bool force);
+  kern_return_t GetEXCState(bool force);
+  kern_return_t GetDBGState(bool force);
+
+  kern_return_t SetGPRState();
+  kern_return_t SetFPUState();
+  kern_return_t SetEXCState();
+  kern_return_t SetDBGState(bool also_set_on_task);
+
+  static DNBArchProtocol *Create(MachThread *thread);
+
+  static const uint8_t *SoftwareBreakpointOpcode(nub_size_t byte_size);
+
+  static const DNBRegisterSetInfo *GetRegisterSetInfo(nub_size_t *num_reg_sets);
+
+  static uint32_t GetRegisterContextSize();
+
+  // Helper functions for watchpoint manipulations.
+  static void SetWatchpoint(DBG &debug_state, uint32_t hw_index,
+                            nub_addr_t addr, nub_size_t size, bool read,
+                            bool write);
+  static void ClearWatchpoint(DBG &debug_state, uint32_t hw_index);
+  static bool IsWatchpointVacant(const DBG &debug_state, uint32_t hw_index);
+  static void ClearWatchpointHits(DBG &debug_state);
+  static bool IsWatchpointHit(const DBG &debug_state, uint32_t hw_index);
+  static nub_addr_t GetWatchAddress(const DBG &debug_state, uint32_t hw_index);
+
+  virtual bool StartTransForHWP();
+  virtual bool RollbackTransForHWP();
+  virtual bool FinishTransForHWP();
+  DBG GetDBGCheckpoint();
+
+  MachThread *m_thread;
+  State m_state;
+  DBG m_2pc_dbg_checkpoint;
+  uint32_t m_2pc_trans_state; // Is transaction of DBG state change: Pedning
+                              // (0), Done (1), or Rolled Back (2)?
+  typedef std::map<uint32_t, Context> SaveRegisterStates;
+  SaveRegisterStates m_saved_register_states;
+};
+
+#endif // #if defined (__i386__) || defined (__x86_64__)
+#endif // #ifndef __DNBArchImplI386_h__

external/llvm-project/lldb/tools/debugserver/source/MacOSX/i386/MachRegisterStatesI386.h

@@ -0,0 +1,178 @@
+//===-- MachRegisterStatesI386.h --------------------------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+//  Created by Sean Callanan on 3/16/11.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef __MachRegisterStatesI386_h__
+#define __MachRegisterStatesI386_h__
+
+#include <inttypes.h>
+
+#define __i386_THREAD_STATE 1
+#define __i386_FLOAT_STATE 2
+#define __i386_EXCEPTION_STATE 3
+#define __i386_DEBUG_STATE 10
+#define __i386_AVX_STATE 16
+
+typedef struct {
+  uint32_t __eax;
+  uint32_t __ebx;
+  uint32_t __ecx;
+  uint32_t __edx;
+  uint32_t __edi;
+  uint32_t __esi;
+  uint32_t __ebp;
+  uint32_t __esp;
+  uint32_t __ss;
+  uint32_t __eflags;
+  uint32_t __eip;
+  uint32_t __cs;
+  uint32_t __ds;
+  uint32_t __es;
+  uint32_t __fs;
+  uint32_t __gs;
+} __i386_thread_state_t;
+
+typedef struct {
+  uint16_t __invalid : 1;
+  uint16_t __denorm : 1;
+  uint16_t __zdiv : 1;
+  uint16_t __ovrfl : 1;
+  uint16_t __undfl : 1;
+  uint16_t __precis : 1;
+  uint16_t __PAD1 : 2;
+  uint16_t __pc : 2;
+  uint16_t __rc : 2;
+  uint16_t __PAD2 : 1;
+  uint16_t __PAD3 : 3;
+} __i386_fp_control_t;
+
+typedef struct {
+  uint16_t __invalid : 1;
+  uint16_t __denorm : 1;
+  uint16_t __zdiv : 1;
+  uint16_t __ovrfl : 1;
+  uint16_t __undfl : 1;
+  uint16_t __precis : 1;
+  uint16_t __stkflt : 1;
+  uint16_t __errsumm : 1;
+  uint16_t __c0 : 1;
+  uint16_t __c1 : 1;
+  uint16_t __c2 : 1;
+  uint16_t __tos : 3;
+  uint16_t __c3 : 1;
+  uint16_t __busy : 1;
+} __i386_fp_status_t;
+
+typedef struct {
+  uint8_t __mmst_reg[10];
+  uint8_t __mmst_rsrv[6];
+} __i386_mmst_reg;
+
+typedef struct { uint8_t __xmm_reg[16]; } __i386_xmm_reg;
+
+typedef struct {
+  uint32_t __fpu_reserved[2];
+  __i386_fp_control_t __fpu_fcw;
+  __i386_fp_status_t __fpu_fsw;
+  uint8_t __fpu_ftw;
+  uint8_t __fpu_rsrv1;
+  uint16_t __fpu_fop;
+  uint32_t __fpu_ip;
+  uint16_t __fpu_cs;
+  uint16_t __fpu_rsrv2;
+  uint32_t __fpu_dp;
+  uint16_t __fpu_ds;
+  uint16_t __fpu_rsrv3;
+  uint32_t __fpu_mxcsr;
+  uint32_t __fpu_mxcsrmask;
+  __i386_mmst_reg __fpu_stmm0;
+  __i386_mmst_reg __fpu_stmm1;
+  __i386_mmst_reg __fpu_stmm2;
+  __i386_mmst_reg __fpu_stmm3;
+  __i386_mmst_reg __fpu_stmm4;
+  __i386_mmst_reg __fpu_stmm5;
+  __i386_mmst_reg __fpu_stmm6;
+  __i386_mmst_reg __fpu_stmm7;
+  __i386_xmm_reg __fpu_xmm0;
+  __i386_xmm_reg __fpu_xmm1;
+  __i386_xmm_reg __fpu_xmm2;
+  __i386_xmm_reg __fpu_xmm3;
+  __i386_xmm_reg __fpu_xmm4;
+  __i386_xmm_reg __fpu_xmm5;
+  __i386_xmm_reg __fpu_xmm6;
+  __i386_xmm_reg __fpu_xmm7;
+  uint8_t __fpu_rsrv4[14 * 16];
+  uint32_t __fpu_reserved1;
+} __i386_float_state_t;
+
+typedef struct {
+  uint32_t __fpu_reserved[2];
+  __i386_fp_control_t __fpu_fcw;
+  __i386_fp_status_t __fpu_fsw;
+  uint8_t __fpu_ftw;
+  uint8_t __fpu_rsrv1;
+  uint16_t __fpu_fop;
+  uint32_t __fpu_ip;
+  uint16_t __fpu_cs;
+  uint16_t __fpu_rsrv2;
+  uint32_t __fpu_dp;
+  uint16_t __fpu_ds;
+  uint16_t __fpu_rsrv3;
+  uint32_t __fpu_mxcsr;
+  uint32_t __fpu_mxcsrmask;
+  __i386_mmst_reg __fpu_stmm0;
+  __i386_mmst_reg __fpu_stmm1;
+  __i386_mmst_reg __fpu_stmm2;
+  __i386_mmst_reg __fpu_stmm3;
+  __i386_mmst_reg __fpu_stmm4;
+  __i386_mmst_reg __fpu_stmm5;
+  __i386_mmst_reg __fpu_stmm6;
+  __i386_mmst_reg __fpu_stmm7;
+  __i386_xmm_reg __fpu_xmm0;
+  __i386_xmm_reg __fpu_xmm1;
+  __i386_xmm_reg __fpu_xmm2;
+  __i386_xmm_reg __fpu_xmm3;
+  __i386_xmm_reg __fpu_xmm4;
+  __i386_xmm_reg __fpu_xmm5;
+  __i386_xmm_reg __fpu_xmm6;
+  __i386_xmm_reg __fpu_xmm7;
+  uint8_t __fpu_rsrv4[14 * 16];
+  uint32_t __fpu_reserved1;
+  uint8_t __avx_reserved1[64];
+  __i386_xmm_reg __fpu_ymmh0;
+  __i386_xmm_reg __fpu_ymmh1;
+  __i386_xmm_reg __fpu_ymmh2;
+  __i386_xmm_reg __fpu_ymmh3;
+  __i386_xmm_reg __fpu_ymmh4;
+  __i386_xmm_reg __fpu_ymmh5;
+  __i386_xmm_reg __fpu_ymmh6;
+  __i386_xmm_reg __fpu_ymmh7;
+} __i386_avx_state_t;
+
+typedef struct {
+  uint32_t __trapno;
+  uint32_t __err;
+  uint32_t __faultvaddr;
+} __i386_exception_state_t;
+
+typedef struct {
+  uint32_t __dr0;
+  uint32_t __dr1;
+  uint32_t __dr2;
+  uint32_t __dr3;
+  uint32_t __dr4;
+  uint32_t __dr5;
+  uint32_t __dr6;
+  uint32_t __dr7;
+} __i386_debug_state_t;
+
+#endif