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Imported Upstream version 5.18.0.246
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131
external/llvm/test/Transforms/InstCombine/PowerPC/aligned-altivec.ll
vendored
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131
external/llvm/test/Transforms/InstCombine/PowerPC/aligned-altivec.ll
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@ -0,0 +1,131 @@
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; RUN: opt -S -instcombine < %s | FileCheck %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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declare <4 x i32> @llvm.ppc.altivec.lvx(i8*) #1
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define <4 x i32> @test1(<4 x i32>* %h) #0 {
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entry:
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%h1 = getelementptr <4 x i32>, <4 x i32>* %h, i64 1
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%hv = bitcast <4 x i32>* %h1 to i8*
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%vl = call <4 x i32> @llvm.ppc.altivec.lvx(i8* %hv)
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; CHECK-LABEL: @test1
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; CHECK: @llvm.ppc.altivec.lvx
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; CHECK: ret <4 x i32>
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%v0 = load <4 x i32>, <4 x i32>* %h, align 8
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%a = add <4 x i32> %v0, %vl
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ret <4 x i32> %a
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}
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define <4 x i32> @test1a(<4 x i32>* align 16 %h) #0 {
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entry:
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%h1 = getelementptr <4 x i32>, <4 x i32>* %h, i64 1
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%hv = bitcast <4 x i32>* %h1 to i8*
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%vl = call <4 x i32> @llvm.ppc.altivec.lvx(i8* %hv)
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; CHECK-LABEL: @test1a
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; CHECK-NOT: @llvm.ppc.altivec.lvx
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; CHECK: ret <4 x i32>
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%v0 = load <4 x i32>, <4 x i32>* %h, align 8
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%a = add <4 x i32> %v0, %vl
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ret <4 x i32> %a
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}
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declare void @llvm.ppc.altivec.stvx(<4 x i32>, i8*) #0
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define <4 x i32> @test2(<4 x i32>* %h, <4 x i32> %d) #0 {
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entry:
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%h1 = getelementptr <4 x i32>, <4 x i32>* %h, i64 1
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%hv = bitcast <4 x i32>* %h1 to i8*
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call void @llvm.ppc.altivec.stvx(<4 x i32> %d, i8* %hv)
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%v0 = load <4 x i32>, <4 x i32>* %h, align 8
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ret <4 x i32> %v0
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; CHECK-LABEL: @test2
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; CHECK: @llvm.ppc.altivec.stvx
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; CHECK: ret <4 x i32>
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}
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define <4 x i32> @test2a(<4 x i32>* align 16 %h, <4 x i32> %d) #0 {
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entry:
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%h1 = getelementptr <4 x i32>, <4 x i32>* %h, i64 1
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%hv = bitcast <4 x i32>* %h1 to i8*
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call void @llvm.ppc.altivec.stvx(<4 x i32> %d, i8* %hv)
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%v0 = load <4 x i32>, <4 x i32>* %h, align 8
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ret <4 x i32> %v0
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; CHECK-LABEL: @test2
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; CHECK-NOT: @llvm.ppc.altivec.stvx
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; CHECK: ret <4 x i32>
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}
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declare <4 x i32> @llvm.ppc.altivec.lvxl(i8*) #1
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define <4 x i32> @test1l(<4 x i32>* %h) #0 {
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entry:
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%h1 = getelementptr <4 x i32>, <4 x i32>* %h, i64 1
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%hv = bitcast <4 x i32>* %h1 to i8*
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%vl = call <4 x i32> @llvm.ppc.altivec.lvxl(i8* %hv)
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; CHECK-LABEL: @test1l
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; CHECK: @llvm.ppc.altivec.lvxl
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; CHECK: ret <4 x i32>
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%v0 = load <4 x i32>, <4 x i32>* %h, align 8
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%a = add <4 x i32> %v0, %vl
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ret <4 x i32> %a
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}
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define <4 x i32> @test1la(<4 x i32>* align 16 %h) #0 {
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entry:
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%h1 = getelementptr <4 x i32>, <4 x i32>* %h, i64 1
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%hv = bitcast <4 x i32>* %h1 to i8*
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%vl = call <4 x i32> @llvm.ppc.altivec.lvxl(i8* %hv)
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; CHECK-LABEL: @test1la
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; CHECK-NOT: @llvm.ppc.altivec.lvxl
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; CHECK: ret <4 x i32>
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%v0 = load <4 x i32>, <4 x i32>* %h, align 8
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%a = add <4 x i32> %v0, %vl
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ret <4 x i32> %a
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}
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declare void @llvm.ppc.altivec.stvxl(<4 x i32>, i8*) #0
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define <4 x i32> @test2l(<4 x i32>* %h, <4 x i32> %d) #0 {
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entry:
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%h1 = getelementptr <4 x i32>, <4 x i32>* %h, i64 1
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%hv = bitcast <4 x i32>* %h1 to i8*
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call void @llvm.ppc.altivec.stvxl(<4 x i32> %d, i8* %hv)
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%v0 = load <4 x i32>, <4 x i32>* %h, align 8
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ret <4 x i32> %v0
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; CHECK-LABEL: @test2l
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; CHECK: @llvm.ppc.altivec.stvxl
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; CHECK: ret <4 x i32>
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}
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define <4 x i32> @test2la(<4 x i32>* align 16 %h, <4 x i32> %d) #0 {
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entry:
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%h1 = getelementptr <4 x i32>, <4 x i32>* %h, i64 1
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%hv = bitcast <4 x i32>* %h1 to i8*
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call void @llvm.ppc.altivec.stvxl(<4 x i32> %d, i8* %hv)
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%v0 = load <4 x i32>, <4 x i32>* %h, align 8
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ret <4 x i32> %v0
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; CHECK-LABEL: @test2l
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; CHECK-NOT: @llvm.ppc.altivec.stvxl
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; CHECK: ret <4 x i32>
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readonly }
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165
external/llvm/test/Transforms/InstCombine/PowerPC/aligned-qpx.ll
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165
external/llvm/test/Transforms/InstCombine/PowerPC/aligned-qpx.ll
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@ -0,0 +1,165 @@
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; RUN: opt -S -instcombine < %s | FileCheck %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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declare <4 x double> @llvm.ppc.qpx.qvlfs(i8*) #1
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define <4 x double> @test1(<4 x float>* %h) #0 {
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entry:
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%h1 = getelementptr <4 x float>, <4 x float>* %h, i64 1
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%hv = bitcast <4 x float>* %h1 to i8*
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%vl = call <4 x double> @llvm.ppc.qpx.qvlfs(i8* %hv)
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; CHECK-LABEL: @test1
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; CHECK: @llvm.ppc.qpx.qvlfs
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; CHECK: ret <4 x double>
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%v0 = load <4 x float>, <4 x float>* %h, align 8
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%v0e = fpext <4 x float> %v0 to <4 x double>
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%a = fadd <4 x double> %v0e, %vl
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ret <4 x double> %a
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}
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define <4 x double> @test1a(<4 x float>* align 16 %h) #0 {
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entry:
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%h1 = getelementptr <4 x float>, <4 x float>* %h, i64 1
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%hv = bitcast <4 x float>* %h1 to i8*
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%vl = call <4 x double> @llvm.ppc.qpx.qvlfs(i8* %hv)
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; CHECK-LABEL: @test1a
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; CHECK-NOT: @llvm.ppc.qpx.qvlfs
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; CHECK-NOT: load <4 x double>
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; CHECK: ret <4 x double>
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%v0 = load <4 x float>, <4 x float>* %h, align 8
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%v0e = fpext <4 x float> %v0 to <4 x double>
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%a = fadd <4 x double> %v0e, %vl
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ret <4 x double> %a
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}
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declare void @llvm.ppc.qpx.qvstfs(<4 x double>, i8*) #0
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define <4 x float> @test2(<4 x float>* %h, <4 x double> %d) #0 {
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entry:
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%h1 = getelementptr <4 x float>, <4 x float>* %h, i64 1
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%hv = bitcast <4 x float>* %h1 to i8*
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call void @llvm.ppc.qpx.qvstfs(<4 x double> %d, i8* %hv)
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%v0 = load <4 x float>, <4 x float>* %h, align 8
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ret <4 x float> %v0
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; CHECK-LABEL: @test2
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; CHECK: @llvm.ppc.qpx.qvstfs
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; CHECK: ret <4 x float>
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}
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define <4 x float> @test2a(<4 x float>* align 16 %h, <4 x double> %d) #0 {
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entry:
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%h1 = getelementptr <4 x float>, <4 x float>* %h, i64 1
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%hv = bitcast <4 x float>* %h1 to i8*
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call void @llvm.ppc.qpx.qvstfs(<4 x double> %d, i8* %hv)
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%v0 = load <4 x float>, <4 x float>* %h, align 8
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ret <4 x float> %v0
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; CHECK-LABEL: @test2
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; CHECK: fptrunc <4 x double> %d to <4 x float>
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; CHECK-NOT: @llvm.ppc.qpx.qvstfs
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; CHECK-NOT: store <4 x double>
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; CHECK: ret <4 x float>
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}
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declare <4 x double> @llvm.ppc.qpx.qvlfd(i8*) #1
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define <4 x double> @test1l(<4 x double>* %h) #0 {
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entry:
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%h1 = getelementptr <4 x double>, <4 x double>* %h, i64 1
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%hv = bitcast <4 x double>* %h1 to i8*
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%vl = call <4 x double> @llvm.ppc.qpx.qvlfd(i8* %hv)
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; CHECK-LABEL: @test1l
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; CHECK: @llvm.ppc.qpx.qvlfd
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; CHECK: ret <4 x double>
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%v0 = load <4 x double>, <4 x double>* %h, align 8
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%a = fadd <4 x double> %v0, %vl
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ret <4 x double> %a
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}
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define <4 x double> @test1ln(<4 x double>* align 16 %h) #0 {
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entry:
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%h1 = getelementptr <4 x double>, <4 x double>* %h, i64 1
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%hv = bitcast <4 x double>* %h1 to i8*
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%vl = call <4 x double> @llvm.ppc.qpx.qvlfd(i8* %hv)
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; CHECK-LABEL: @test1ln
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; CHECK: @llvm.ppc.qpx.qvlfd
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; CHECK: ret <4 x double>
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%v0 = load <4 x double>, <4 x double>* %h, align 8
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%a = fadd <4 x double> %v0, %vl
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ret <4 x double> %a
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}
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define <4 x double> @test1la(<4 x double>* align 32 %h) #0 {
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entry:
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%h1 = getelementptr <4 x double>, <4 x double>* %h, i64 1
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%hv = bitcast <4 x double>* %h1 to i8*
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%vl = call <4 x double> @llvm.ppc.qpx.qvlfd(i8* %hv)
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; CHECK-LABEL: @test1la
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; CHECK-NOT: @llvm.ppc.qpx.qvlfd
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; CHECK: ret <4 x double>
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%v0 = load <4 x double>, <4 x double>* %h, align 8
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%a = fadd <4 x double> %v0, %vl
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ret <4 x double> %a
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}
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declare void @llvm.ppc.qpx.qvstfd(<4 x double>, i8*) #0
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define <4 x double> @test2l(<4 x double>* %h, <4 x double> %d) #0 {
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entry:
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%h1 = getelementptr <4 x double>, <4 x double>* %h, i64 1
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%hv = bitcast <4 x double>* %h1 to i8*
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call void @llvm.ppc.qpx.qvstfd(<4 x double> %d, i8* %hv)
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%v0 = load <4 x double>, <4 x double>* %h, align 8
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ret <4 x double> %v0
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; CHECK-LABEL: @test2l
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; CHECK: @llvm.ppc.qpx.qvstfd
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; CHECK: ret <4 x double>
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}
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define <4 x double> @test2ln(<4 x double>* align 16 %h, <4 x double> %d) #0 {
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entry:
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%h1 = getelementptr <4 x double>, <4 x double>* %h, i64 1
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%hv = bitcast <4 x double>* %h1 to i8*
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call void @llvm.ppc.qpx.qvstfd(<4 x double> %d, i8* %hv)
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%v0 = load <4 x double>, <4 x double>* %h, align 8
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ret <4 x double> %v0
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; CHECK-LABEL: @test2ln
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; CHECK: @llvm.ppc.qpx.qvstfd
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; CHECK: ret <4 x double>
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}
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define <4 x double> @test2la(<4 x double>* align 32 %h, <4 x double> %d) #0 {
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entry:
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%h1 = getelementptr <4 x double>, <4 x double>* %h, i64 1
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%hv = bitcast <4 x double>* %h1 to i8*
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call void @llvm.ppc.qpx.qvstfd(<4 x double> %d, i8* %hv)
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%v0 = load <4 x double>, <4 x double>* %h, align 8
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ret <4 x double> %v0
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; CHECK-LABEL: @test2l
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; CHECK-NOT: @llvm.ppc.qpx.qvstfd
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; CHECK: ret <4 x double>
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readonly }
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3
external/llvm/test/Transforms/InstCombine/PowerPC/lit.local.cfg
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3
external/llvm/test/Transforms/InstCombine/PowerPC/lit.local.cfg
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if not 'PowerPC' in config.root.targets:
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config.unsupported = True
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44
external/llvm/test/Transforms/InstCombine/PowerPC/vsx-unaligned.ll
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Normal file
44
external/llvm/test/Transforms/InstCombine/PowerPC/vsx-unaligned.ll
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@ -0,0 +1,44 @@
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; Verify that we can create unaligned loads and stores from VSX intrinsics.
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; RUN: opt < %s -instcombine -S | FileCheck %s
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target triple = "powerpc64-unknown-linux-gnu"
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@vf = common global <4 x float> zeroinitializer, align 1
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@res_vf = common global <4 x float> zeroinitializer, align 1
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@vd = common global <2 x double> zeroinitializer, align 1
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@res_vd = common global <2 x double> zeroinitializer, align 1
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define void @test1() {
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entry:
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%t1 = alloca <4 x float>*, align 8
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%t2 = alloca <2 x double>*, align 8
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store <4 x float>* @vf, <4 x float>** %t1, align 8
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%0 = load <4 x float>*, <4 x float>** %t1, align 8
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%1 = bitcast <4 x float>* %0 to i8*
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%2 = call <4 x i32> @llvm.ppc.vsx.lxvw4x(i8* %1)
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store <4 x float>* @res_vf, <4 x float>** %t1, align 8
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%3 = load <4 x float>*, <4 x float>** %t1, align 8
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%4 = bitcast <4 x float>* %3 to i8*
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call void @llvm.ppc.vsx.stxvw4x(<4 x i32> %2, i8* %4)
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store <2 x double>* @vd, <2 x double>** %t2, align 8
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%5 = load <2 x double>*, <2 x double>** %t2, align 8
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%6 = bitcast <2 x double>* %5 to i8*
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%7 = call <2 x double> @llvm.ppc.vsx.lxvd2x(i8* %6)
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store <2 x double>* @res_vd, <2 x double>** %t2, align 8
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%8 = load <2 x double>*, <2 x double>** %t2, align 8
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%9 = bitcast <2 x double>* %8 to i8*
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call void @llvm.ppc.vsx.stxvd2x(<2 x double> %7, i8* %9)
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ret void
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}
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; CHECK-LABEL: @test1
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; CHECK: %0 = load <4 x i32>, <4 x i32>* bitcast (<4 x float>* @vf to <4 x i32>*), align 1
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; CHECK: store <4 x i32> %0, <4 x i32>* bitcast (<4 x float>* @res_vf to <4 x i32>*), align 1
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; CHECK: %1 = load <2 x double>, <2 x double>* @vd, align 1
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; CHECK: store <2 x double> %1, <2 x double>* @res_vd, align 1
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declare <4 x i32> @llvm.ppc.vsx.lxvw4x(i8*)
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declare void @llvm.ppc.vsx.stxvw4x(<4 x i32>, i8*)
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declare <2 x double> @llvm.ppc.vsx.lxvd2x(i8*)
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declare void @llvm.ppc.vsx.stxvd2x(<2 x double>, i8*)
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