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Imported Upstream version 5.18.0.246

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Former-commit-id: 0c7ce5b1a7851e13f22acfd379b7f9fb304e4833
This commit is contained in:
Xamarin Public Jenkins (auto-signing)
2019-01-23 08:21:40 +00:00
parent a7724cd563
commit 279aa8f685
28482 changed files with 3866972 additions and 44 deletions
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12
external/llvm/test/MC/Disassembler/ARM/addrmode2-reencoding.txt vendored Normal file
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# RUN: llvm-mc -triple armv7 -show-encoding -disassemble < %s | FileCheck %s
0x00 0x10 0xb0 0xe4
0x00 0x10 0xf0 0xe4
0x00 0x10 0xa0 0xe4
0x00 0x10 0xe0 0xe4
# CHECK: ldrt r1, [r0], #0 @ encoding: [0x00,0x10,0xb0,0xe4]
# CHECK: ldrbt r1, [r0], #0 @ encoding: [0x00,0x10,0xf0,0xe4]
# CHECK: strt r1, [r0], #0 @ encoding: [0x00,0x10,0xa0,0xe4]
# CHECK: strbt r1, [r0], #0 @ encoding: [0x00,0x10,0xe0,0xe4]

14
external/llvm/test/MC/Disassembler/ARM/arm-LDREXD-reencoding.txt vendored Normal file
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# RUN: llvm-mc -triple armv7 -show-encoding -disassemble < %s | FileCheck %s
0x9f 0x0f 0xb0 0xe1
0x9f 0xcf 0xb1 0xe1
0x9f 0xcf 0xb3 0xe1
0x9f 0x8f 0xbd 0xe1
0x9f 0xcf 0xbe 0xe1
# CHECK: ldrexd r0, r1, [r0] @ encoding: [0x9f,0x0f,0xb0,0xe1]
# CHECK: ldrexd r12, sp, [r1] @ encoding: [0x9f,0xcf,0xb1,0xe1]
# CHECK: ldrexd r12, sp, [r3] @ encoding: [0x9f,0xcf,0xb3,0xe1]
# CHECK: ldrexd r8, r9, [sp] @ encoding: [0x9f,0x8f,0xbd,0xe1]
# CHECK: ldrexd r12, sp, [lr] @ encoding: [0x9f,0xcf,0xbe,0xe1]

14
external/llvm/test/MC/Disassembler/ARM/arm-STREXD-reencoding.txt vendored Normal file
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@@ -0,0 +1,14 @@
# RUN: llvm-mc -triple armv7 -show-encoding -disassemble < %s | FileCheck %s
0x92 0x1f 0xa0 0xe1
0x90 0x4f 0xa3 0xe1
0x92 0xdf 0xa4 0xe1
0x90 0xaf 0xa6 0xe1
0x9c 0x5f 0xa8 0xe1
# CHECK: strexd r1, r2, r3, [r0] @ encoding: [0x92,0x1f,0xa0,0xe1]
# CHECK: strexd r4, r0, r1, [r3] @ encoding: [0x90,0x4f,0xa3,0xe1]
# CHECK: strexd sp, r2, r3, [r4] @ encoding: [0x92,0xdf,0xa4,0xe1]
# CHECK: strexd r10, r0, r1, [r6] @ encoding: [0x90,0xaf,0xa6,0xe1]
# CHECK: strexd r5, r12, sp, [r8] @ encoding: [0x9c,0x5f,0xa8,0xe1]

364
external/llvm/test/MC/Disassembler/ARM/arm-tests.txt vendored Normal file
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# RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 -mcpu=cortex-a9 | FileCheck %s
# CHECK: addpl r4, pc, #76, #10
0x4c 0x45 0x8f 0x52
# CHECK: b #0
0x00 0x00 0x00 0xea
# CHECK: bl #7732
0x8d 0x07 0x00 0xeb
# CHECK: bleq #-4
0xff 0xff 0xff 0x0b
# CHECK: bfc r8, #0, #16
0x1f 0x80 0xcf 0xe7
# CHECK: bfi r8, r0, #16, #1
0x10 0x88 0xd0 0xe7
# CHECK: mov pc, lr
0x0e 0xf0 0xa0 0xe1
# CHECK: mov pc, #3221225535
0xff 0xf1 0xa0 0xe3
# CHECK: movw r7, #4096
0x00 0x70 0x01 0xe3
# CHECK: cmn r0, #1
0x01 0x00 0x70 0xe3
# CHECK: dmb
0x5f 0xf0 0x7f 0xf5
# CHECK: dmb nshst
0x56 0xf0 0x7f 0xf5
# CHECK: dsb
0x4f 0xf0 0x7f 0xf5
# CHECK: dsb st
0x4e 0xf0 0x7f 0xf5
# CHECK: isb
0x6f 0xf0 0x7f 0xf5
# FIXME: LDC encoding information is incorrect. Re-enable this along with more
# robust testing for other values when we get it fleshed out and working
# properly.
# CHECKx: ldclvc p5, cr15, [r8], #-0
#0x00 0xf5 0x78 0x7c
# CHECK: ldc p13, c9, [r2, #0]!
0x00 0x9d 0xb2 0xed
# CHECK: ldcl p1, c9, [r3, #0]!
0x00 0x91 0xf3 0xed
# CHECK: ldr r0, [r2], #15
0x0f 0x00 0x92 0xe4
# CHECK: ldr r5, [r7, -r10, lsl #2]
0x0a 0x51 0x17 0xe7
# CHECK: ldr r4, [r5, #0]!
0x00 0x40 0xb5 0xe5
# CHECK: ldrb lr, [r10, #0]!
0x00 0xe0 0xfa 0xe5
# CHECK: ldrd r4, r5, [r0, #0]!
0xd0 0x40 0xe0 0xe1
# CHECK: ldrh r0, [r2], #0
0xb0 0x00 0xd2 0xe0
# CHECK: ldrh r0, [r2]
0xb0 0x00 0xd2 0xe1
# CHECK: ldrh lr, [sp, #0]!
0xb0 0xe0 0xfd 0xe1
# CHECK: ldrht r0, [r2], #15
0xbf 0x00 0xf2 0xe0
# CHECK: ldrsb r1, [lr, #0]!
0xd0 0x10 0xfe 0xe1
# CHECK: ldrsbtvs lr, [r2], -r9
0xd9 0xe0 0x32 0x60
# CHECK: ldrsh r9, [r1, #0]
0xf0 0x90 0xf1 0xe1
# CHECK: lsls r0, r2, #31
0x82 0x0f 0xb0 0xe1
# CHECK: mcr2 p0, #0, r2, c1, c0, #7
0xf0 0x20 0x01 0xfe
# CHECK: movt r8, #65535
0xff 0x8f 0x4f 0xe3
# CHECK: mvnspl r7, #1073741885
0xf5 0x71 0xf0 0x53
# CHECK-NOT: orr r7, r8, r7, rrx #0
# CHECK: orr r7, r8, r7, rrx
0x67 0x70 0x88 0xe1
# CHECK: pkhbt r8, r9, r10, lsl #4
0x1a 0x82 0x89 0xe6
# CHECK-NOT: pkhbtls r10, r11, r11, lsl #0
# CHECK: pkhbtls r10, r11, r11
0x1b 0xa0 0x8b 0x96
# CHECK: pkhtbmi lr, r1, r6, asr #21
0xd6 0xea 0x81 0x46
# CHECK: pop {r0, r2, r4, r6, r8, r10}
0x55 0x05 0xbd 0xe8
# CHECK: push {r0, r2, r4, r6, r8, r10}
0x55 0x05 0x2d 0xe9
# CHECK: qsax r8, r9, r10
0x5a 0x8f 0x29 0xe6
# CHECK: rfedb r0!
0x00 0x0a 0x30 0xf9
# CHECK: srsdb sp!, #19
0x13 0x05 0x6d 0xf9
# CHECK: srsia sp, #9
0x09 0x05 0xcd 0xf8
# CHECK-NOT: rsbeq r0, r2, r0, lsl #0
# CHECK: rsbeq r0, r2, r0
0x00 0x00 0x62 0x00
# CHECK-NOT: rscseq r0, r0, r1, lsl #0
# CHECK: rscseq r0, r0, r1
0x01 0x00 0xf0 0x00
# CHECK: sbcs r0, pc, #1
0x01 0x00 0xdf 0xe2
# CHECK: sbfx r0, r1, #0, #8
0x51 0x00 0xa7 0xe7
# CHECK: ssat r8, #1, r10, lsl #8
0x1a 0x84 0xa0 0xe6
# CHECK-NOT: ssatmi r0, #17, r12, lsl #0
# CHECK: ssatmi r0, #17, r12
0x1c 0x00 0xb0 0x46
# CHECK: stmdb r10!, {r4, r5, r6, r7, lr}
0xf0 0x40 0x2a 0xe9
# CHECK: teq r0, #31
0x1f 0x00 0x30 0xe3
# CHECK: ubfx r0, r0, #16, #1
0x50 0x08 0xe0 0xe7
# CHECK: usat r8, #0, r10, asr #32
0x5a 0x80 0xe0 0xe6
# CHECK: setend be
0x00 0x02 0x01 0xf1
# CHECK: setend le
0x00 0x00 0x01 0xf1
# CHECK: cpsie aif
0xc0 0x01 0x08 0xf1
# CHECK: cps #15
0x0f 0x00 0x02 0xf1
# CHECK: cpsie if, #10
0xca 0x00 0x0a 0xf1
# CHECK: msr CPSR_fc, r0
0x00 0xf0 0x29 0xe1
# CHECK: msrmi CPSR_c, #4043309056
0xf1 0xf4 0x21 0x43
# CHECK: rsbs r6, r7, r8
0x08 0x60 0x77 0xe0
# CHECK: blxeq r5
0x35 0xff 0x2f 0x01
# CHECK: bx r12
0x1c 0xff 0x2f 0xe1
# CHECK: bxeq r5
0x15 0xff 0x2f 0x01
# CHECK: uqadd16mi r6, r11, r8
0x18 0x6F 0x6b 0x46
# CHECK: str r0, [sp, #4]
0x04 0x00 0x8d 0xe5
# CHECK: str r1, [sp]
0x00 0x10 0x8d 0xe5
# CHECK: ldr r3, [pc, #144]
0x90 0x30 0x9f 0xe5
# CHECK: ldr r3, [r0, #-4]
0x4 0x30 0x10 0xe5
# CHECK: ldr r5, [sp, r0, lsl #1]!
0x80 0x50 0xbd 0xe7
# CHECK: ldr r5, [r7], -r0, lsr #2
0x20 0x51 0x17 0xe6
# CHECK: strdeq r2, r3, [r0], -r8
0xf8 0x20 0x00 0x00
# CHECK: ldrdeq r2, r3, [r0], -r12
0xdc 0x24 0x00 0x00
# CHECK: ldrbt r3, [r4], -r5, lsl #12
0x05 0x36 0x74 0xe6
# CHECK: vcmpe.f64 d8, #0
0xc0 0x8b 0xb5 0xee
# CHECK: vldmdb r2!, {s7, s8, s9, s10, s11}
0x05 0x3a 0x72 0xed
# CHECK: vldr s23, [r2, #660]
0xa5 0xba 0xd2 0xed
# CHECK: strtvc r5, [r3], r0, lsr #20
0x20 0x5a 0xa3 0x76
# CHECK: stmiblo sp, {r0, r4, r8, r11, r12, pc}
0x11 0x99 0x8d 0x39
# CHECK: ldmdb sp, {r0, r4, r8, r11, r12, pc}
0x11 0x99 0x1d 0xe9
# CHECK: swpge r3, r2, [r6]
0x92 0x30 0x06 0xa1
# CHECK: umull r1, r2, r3, r4
0x93 0x14 0x82 0xe0
# CHECK: pldw [pc, #-0]
0x00 0xf0 0x1f 0xf5
# CHECK: pli [pc, #-0]
0x00 0xf0 0x5f 0xf4
# CHECK: pli [r3, r1, lsl #2]
0x01 0xf1 0xd3 0xf6
# CHECK: stc p2, c4, [r9], {157}
0x9d 0x42 0x89 0xec
# CHECK: stc p15, c0, [r3, #0]!
0x00 0x0f 0xa3 0xed
# CHECK: stc2 p2, c4, [r9], {157}
0x9d 0x42 0x89 0xfc
# CHECK: stcl p13, c12, [r9, #0]!
0x00 0xcd 0xe9 0xed
# CHECK: str pc, [r11, #0]!
0x00 0xf0 0xab 0xe5
# CHECK: strb r9, [r10, #0]!
0x00 0x90 0xea 0xe5
# CHECK: strd r12, sp, [r6, #0]!
0xf0 0xc0 0xe6 0xe1
# CHECK: strh r7, [r9, #0]!
0xb0 0x70 0xe9 0xe1
# CHECK: bne #-24
0xfa 0xff 0xff 0x1a
# CHECK: blx #60
0x0f 0x00 0x00 0xfa
# CHECK-NOT: adcs r10, r8, r0, asr #6
# CHECK: adcshi r10, r8, r0, asr #6
0x40 0xa3 0xb8 0x80
# CHECK: adcshi r10, r8, r0, asr r3
0x50 0xa3 0xb8 0x80
# CHECK: streq r1, [sp], #-1567
0x1f 0x16 0xd 0x4
# CHECK: mrchs p2, #3, r11, c13, c6, #6
0xd6 0xb2 0x7d 0x2e
# CHECK: smlsldx r4, r12, r11, r4
0x7b 0x44 0x4c 0xe7
# CHECK: lsl r3, r2, r1
0x12 0x31 0xa0 0xe1
# CHECK: sxtab r9, r8, r5
0x75 0x90 0xa8 0xe6
# CHECK: sxtb r9, r5, ror #8
0x75 0x94 0xaf 0xe6
# CHECK: bfc r5, #0, #16
0x1f 0x50 0xcf 0xe7
# CHECK: bfi r5, r6, #0, #16
0x16 0x50 0xcf 0xe7
# CHECK: sbfx r5, r6, #8, #8
0x56 0x54 0xa7 0xe7
# CHECK: rsb pc, r5, r0
0x00 0xf0 0x65 0xe0
# CHECK: uqadd8 r5, r6, r7
0x97 0x5f 0x66 0xe6
# CHECK: uqsax r5, r6, r7
0x57 0x5f 0x66 0xe6
# CHECK: smmlareq r0, r0, r0, r0
0x30 0x00 0x50 0x07
# CHECK: nop
0x00 0xf0 0x20 0xe3
# CHECK: andeq r0, r0, r0, lsr #32
0x20 0x00 0x00 0x00
# CHECK: strb r3, [r2], #1
0x01 0x30 0xc2 0xe4
# CHECK: strheq r0, [r0, -r0]
0xb0 0x00 0x00 0x01
# CHECK: rfedb #4!
0x14 0x0 0x32 0xf9
# CHECK: stc2l p0, c0, [r2], #-96
0x18 0x0 0x62 0xfc
# CHECK: ldmgt sp!, {r9}
0x00 0x02 0xbd 0xc8

17
external/llvm/test/MC/Disassembler/ARM/arm-thumb-trustzone.txt vendored Normal file
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@@ -0,0 +1,17 @@
# RUN: llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 -disassemble -mattr=-trustzone < %s | FileCheck %s -check-prefix=NOTZ
# RUN: llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 -disassemble -mattr=trustzone < %s | FileCheck %s -check-prefix=TZ
#------------------------------------------------------------------------------
# SMC
#------------------------------------------------------------------------------
0xff 0xf7 0x00 0x80
0x0c 0xbf
0xf0 0xf7 0x00 0x80
# NOTZ-NOT: smc #15
# NOTZ-NOT: smceq #0
# TZ: smc #15
# TZ: ite eq
# TZ: smceq #0

16
external/llvm/test/MC/Disassembler/ARM/arm-trustzone.txt vendored Normal file
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@@ -0,0 +1,16 @@
# RUN: llvm-mc -triple=armv7-apple-darwin -mcpu=cortex-a8 -disassemble -mattr=-trustzone < %s | FileCheck %s -check-prefix=NOTZ
# RUN: llvm-mc -triple=armv7-apple-darwin -mcpu=cortex-a8 -disassemble -mattr=trustzone < %s | FileCheck %s -check-prefix=TZ
#------------------------------------------------------------------------------
# SMC
#------------------------------------------------------------------------------
0x7f 0x00 0x60 0xe1
0x70 0x00 0x60 0x01
# NOTZ-NOT: smc #15
# NOTZ-NOT: smceq #0
# TZ: smc #15
# TZ: smceq #0

111
external/llvm/test/MC/Disassembler/ARM/arm-vmrs_vmsr.txt vendored Normal file
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@@ -0,0 +1,111 @@
# RUN: not llvm-mc -disassemble -triple=armv7a-arm-none-eabi -mattr=+vfp2 -show-encoding < %s 2>%t \
# RUN: | FileCheck --check-prefix=CHECK-V7A %s
# RUN: FileCheck --check-prefix=ERROR-V7A < %t %s
# RUN: llvm-mc -disassemble -triple=armv8a-arm-none-eabi -mattr=+fp-armv8 -show-encoding < %s 2>%t \
# RUN: | FileCheck --check-prefix=CHECK-V8A %s
# RUN: FileCheck --check-prefix=ERROR-V8A < %t %s
[0x10,0xfa,0xf1,0xee]
[0x10,0xfa,0xf1,0xee]
[0x10,0xfa,0xf1,0xee]
[0x10,0xaa,0xf1,0xee]
[0x10,0x2a,0xf0,0xee]
[0x10,0x3a,0xf0,0xee]
[0x10,0x4a,0xf7,0xee]
[0x10,0x5a,0xf6,0xee]
[0x10,0x6a,0xf5,0xee]
[0x10,0xda,0xf1,0xee]
# CHECK-V7A: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
# CHECK-V7A: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
# CHECK-V7A: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
# CHECK-V7A: vmrs r10, fpscr @ encoding: [0x10,0xaa,0xf1,0xee]
# CHECK-V7A: vmrs r2, fpsid @ encoding: [0x10,0x2a,0xf0,0xee]
# CHECK-V7A: vmrs r3, fpsid @ encoding: [0x10,0x3a,0xf0,0xee]
# CHECK-V7A: vmrs r4, mvfr0 @ encoding: [0x10,0x4a,0xf7,0xee]
# CHECK-V7A: vmrs r5, mvfr1 @ encoding: [0x10,0x5a,0xf6,0xee]
# ERROR-V7A: invalid instruction encoding
# CHECK-V7A: vmrs sp, fpscr @ encoding: [0x10,0xda,0xf1,0xee]
# CHECK-V8A: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
# CHECK-V8A: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
# CHECK-V8A: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
# CHECK-V8A: vmrs r10, fpscr @ encoding: [0x10,0xaa,0xf1,0xee]
# CHECK-V8A: vmrs r2, fpsid @ encoding: [0x10,0x2a,0xf0,0xee]
# CHECK-V8A: vmrs r3, fpsid @ encoding: [0x10,0x3a,0xf0,0xee]
# CHECK-V8A: vmrs r4, mvfr0 @ encoding: [0x10,0x4a,0xf7,0xee]
# CHECK-V8A: vmrs r5, mvfr1 @ encoding: [0x10,0x5a,0xf6,0xee]
# CHECK-V8A: vmrs r6, mvfr2 @ encoding: [0x10,0x6a,0xf5,0xee]
# CHECK-V8A: vmrs sp, fpscr @ encoding: [0x10,0xda,0xf1,0xee]
[0x10,0xfa,0xe1,0xee]
[0x10,0x0a,0xe1,0xee]
[0x10,0x1a,0xe8,0xee]
[0x10,0x2a,0xe0,0xee]
[0x10,0xaa,0xe1,0xee]
[0x10,0xda,0xe1,0xee]
# ERROR-V7A: potentially undefined instruction encoding
# CHECK-V7A: vmsr fpscr, r0 @ encoding: [0x10,0x0a,0xe1,0xee]
# CHECK-V7A: vmsr fpexc, r1 @ encoding: [0x10,0x1a,0xe8,0xee]
# CHECK-V7A: vmsr fpsid, r2 @ encoding: [0x10,0x2a,0xe0,0xee]
# CHECK-V7A: vmsr fpscr, r10 @ encoding: [0x10,0xaa,0xe1,0xee]
# CHECK-V7A: vmsr fpscr, sp @ encoding: [0x10,0xda,0xe1,0xee]
# ERROR-V8A: potentially undefined instruction encoding
# CHECK-V8A: vmsr fpscr, r0 @ encoding: [0x10,0x0a,0xe1,0xee]
# CHECK-V8A: vmsr fpexc, r1 @ encoding: [0x10,0x1a,0xe8,0xee]
# CHECK-V8A: vmsr fpsid, r2 @ encoding: [0x10,0x2a,0xe0,0xee]
# CHECK-V8A: vmsr fpscr, r10 @ encoding: [0x10,0xaa,0xe1,0xee]
# CHECK-V8A: vmsr fpscr, sp @ encoding: [0x10,0xda,0xe1,0xee]
[0x10,0xfa,0xf1,0x0e]
[0x10,0xfa,0xf1,0x1e]
[0x10,0xfa,0xf1,0x2e]
[0x10,0xaa,0xf1,0x3e]
[0x10,0x2a,0xf0,0x4e]
[0x10,0x3a,0xf0,0x5e]
[0x10,0x4a,0xf7,0x6e]
[0x10,0x5a,0xf6,0x7e]
[0x10,0x6a,0xf5,0x8e]
[0x10,0xda,0xf1,0x9e]
# CHECK-V7A: vmrseq APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0x0e]
# CHECK-V7A: vmrsne APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0x1e]
# CHECK-V7A: vmrshs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0x2e]
# CHECK-V7A: vmrslo r10, fpscr @ encoding: [0x10,0xaa,0xf1,0x3e]
# CHECK-V7A: vmrsmi r2, fpsid @ encoding: [0x10,0x2a,0xf0,0x4e]
# CHECK-V7A: vmrspl r3, fpsid @ encoding: [0x10,0x3a,0xf0,0x5e]
# CHECK-V7A: vmrsvs r4, mvfr0 @ encoding: [0x10,0x4a,0xf7,0x6e]
# CHECK-V7A: vmrsvc r5, mvfr1 @ encoding: [0x10,0x5a,0xf6,0x7e]
# ERROR-V7A: invalid instruction encoding
# CHECK-V7A: vmrsls sp, fpscr @ encoding: [0x10,0xda,0xf1,0x9e]
# CHECK-V8A: vmrseq APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0x0e]
# CHECK-V8A: vmrsne APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0x1e]
# CHECK-V8A: vmrshs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0x2e]
# CHECK-V8A: vmrslo r10, fpscr @ encoding: [0x10,0xaa,0xf1,0x3e]
# CHECK-V8A: vmrsmi r2, fpsid @ encoding: [0x10,0x2a,0xf0,0x4e]
# CHECK-V8A: vmrspl r3, fpsid @ encoding: [0x10,0x3a,0xf0,0x5e]
# CHECK-V8A: vmrsvs r4, mvfr0 @ encoding: [0x10,0x4a,0xf7,0x6e]
# CHECK-V8A: vmrsvc r5, mvfr1 @ encoding: [0x10,0x5a,0xf6,0x7e]
# CHECK-V8A: vmrshi r6, mvfr2 @ encoding: [0x10,0x6a,0xf5,0x8e]
# CHECK-V8A: vmrsls sp, fpscr @ encoding: [0x10,0xda,0xf1,0x9e]
[0x10,0x0a,0xe1,0xae]
[0x10,0x1a,0xe8,0xbe]
[0x10,0x2a,0xe0,0xce]
[0x10,0xaa,0xe1,0xde]
[0x10,0xda,0xe1,0x0e]
# CHECK-V7A: vmsrge fpscr, r0 @ encoding: [0x10,0x0a,0xe1,0xae]
# CHECK-V7A: vmsrlt fpexc, r1 @ encoding: [0x10,0x1a,0xe8,0xbe]
# CHECK-V7A: vmsrgt fpsid, r2 @ encoding: [0x10,0x2a,0xe0,0xce]
# CHECK-V7A: vmsrle fpscr, r10 @ encoding: [0x10,0xaa,0xe1,0xde]
# CHECK-V7A: vmsreq fpscr, sp @ encoding: [0x10,0xda,0xe1,0x0e]
# CHECK-V8A: vmsrge fpscr, r0 @ encoding: [0x10,0x0a,0xe1,0xae]
# CHECK-V8A: vmsrlt fpexc, r1 @ encoding: [0x10,0x1a,0xe8,0xbe]
# CHECK-V8A: vmsrgt fpsid, r2 @ encoding: [0x10,0x2a,0xe0,0xce]
# CHECK-V8A: vmsrle fpscr, r10 @ encoding: [0x10,0xaa,0xe1,0xde]
# CHECK-V8A: vmsreq fpscr, sp @ encoding: [0x10,0xda,0xe1,0x0e]

52
external/llvm/test/MC/Disassembler/ARM/armv8.1a.txt vendored Normal file
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@@ -0,0 +1,52 @@
# RUN: llvm-mc -triple armv8 -mattr=+v8.1a --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V81a
# RUN: not llvm-mc -triple armv8 -mattr=+v8 --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V8
[0x54,0x0b,0x12,0xf3]
[0x12,0x0b,0x21,0xf3]
[0x54,0x0c,0x12,0xf3]
[0x12,0x0c,0x21,0xf3]
# CHECK-V81a: vqrdmlah.s16 q0, q1, q2
# CHECK-V81a: vqrdmlah.s32 d0, d1, d2
# CHECK-V81a: vqrdmlsh.s16 q0, q1, q2
# CHECK-V81a: vqrdmlsh.s32 d0, d1, d2
# CHECK-V8: warning: invalid instruction encoding
# CHECK-V8: [0x54,0x0b,0x12,0xf3]
# CHECK-V8: warning: invalid instruction encoding
# CHECK-V8: [0x12,0x0b,0x21,0xf3]
# CHECK-V8: warning: invalid instruction encoding
# CHECK-V8: [0x54,0x0c,0x12,0xf3]
# CHECK-V8: warning: invalid instruction encoding
# CHECK-V8: [0x12,0x0c,0x21,0xf3]
[0x42,0x0e,0x92,0xf3]
[0x42,0x0e,0xa1,0xf2]
[0x42,0x0f,0x92,0xf3]
[0x42,0x0f,0xa1,0xf2]
# CHECK-V81a: vqrdmlah.s16 q0, q1, d2[0]
# CHECK-V81a: vqrdmlah.s32 d0, d1, d2[0]
# CHECK-V81a: vqrdmlsh.s16 q0, q1, d2[0]
# CHECK-V81a: vqrdmlsh.s32 d0, d1, d2[0]
# CHECK-V8: warning: invalid instruction encoding
# CHECK-V8: [0x42,0x0e,0x92,0xf3]
# CHECK-V8: warning: invalid instruction encoding
# CHECK-V8: [0x42,0x0e,0xa1,0xf2]
# CHECK-V8: warning: invalid instruction encoding
# CHECK-V8: [0x42,0x0f,0x92,0xf3]
# CHECK-V8: warning: invalid instruction encoding
# CHECK-V8: [0x42,0x0f,0xa1,0xf2]
# The SETPAN(v8.1a) and TST(v8) instructions occupy the same space, but SETPAN
# uses the encoding for the invalid NV predicate operand. This test checks that
# the disassembler is correctly disambiguating and decoding these instructions.
[0x00 0x00 0x10 0xf1]
# CHECK: setpan #0
[0x00 0x02 0x10 0xf1]
# CHECK: setpan #1
[0x00 0x00 0x10 0xe1]
# CHECK: tst r0, r0
[0x00 0x02 0x10 0xe1]
# CHECK: tst r0, r0, lsl #4

33
external/llvm/test/MC/Disassembler/ARM/armv8.2a-dotprod-a32.s vendored Normal file
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@@ -0,0 +1,33 @@
# RUN: llvm-mc -triple arm-none-linux-gnu -mattr=+dotprod --disassemble < %s | FileCheck %s
# RUN: llvm-mc -triple arm-none-linux-gnu -mattr=-dotprod --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
0x12,0x0d,0x21,0xfc
0x02,0x0d,0x21,0xfc
0x58,0x0d,0x22,0xfc
0x48,0x0d,0x22,0xfc
0x12,0x0d,0x21,0xfe
0x22,0x0d,0x21,0xfe
0x54,0x0d,0x22,0xfe
0x64,0x0d,0x22,0xfe
#CHECK: vudot.u8 d0, d1, d2
#CHECK: vsdot.s8 d0, d1, d2
#CHECK: vudot.u8 q0, q1, q4
#CHECK: vsdot.s8 q0, q1, q4
#CHECK: vudot.u8 d0, d1, d2[0]
#CHECK: vsdot.s8 d0, d1, d2[1]
#CHECK: vudot.u8 q0, q1, d4[0]
#CHECK: vsdot.s8 q0, q1, d4[1]
# without dot product enabled, the instructions get disassembled to these
# coprocessor instructions:
#CHECK-ERROR: stc2 p13, c0, [r1], #-72
#CHECK-ERROR: stc2 p13, c0, [r1], #-8
#CHECK-ERROR: stc2 p13, c0, [r2], #-352
#CHECK-ERROR: stc2 p13, c0, [r2], #-288
#CHECK-ERROR: mcr2 p13, #1, r0, c1, c2, #0
#CHECK-ERROR: cdp2 p13, #2, c0, c1, c2, #1
#CHECK-ERROR: mcr2 p13, #1, r0, c2, c4, #2
#CHECK-ERROR: cdp2 p13, #2, c0, c2, c4, #3

29
external/llvm/test/MC/Disassembler/ARM/armv8.2a-dotprod-t32.s vendored Normal file
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@@ -0,0 +1,29 @@
# RUN: llvm-mc -triple thumbv7a -mattr=+dotprod --disassemble < %s | FileCheck %s
# RUN: llvm-mc -triple thumbv7a -mattr=-dotprod --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
[0x21,0xfc,0x12,0x0d]
[0x21,0xfc,0x02,0x0d]
[0x22,0xfc,0x58,0x0d]
[0x22,0xfc,0x48,0x0d]
[0x21,0xfe,0x12,0x0d]
[0x21,0xfe,0x22,0x0d]
[0x22,0xfe,0x54,0x0d]
[0x22,0xfe,0x64,0x0d]
#CHECK: vudot.u8 d0, d1, d2
#CHECK: vsdot.s8 d0, d1, d2
#CHECK: vudot.u8 q0, q1, q4
#CHECK: vsdot.s8 q0, q1, q4
#CHECK: vudot.u8 d0, d1, d2[0]
#CHECK: vsdot.s8 d0, d1, d2[1]
#CHECK: vudot.u8 q0, q1, d4[0]
#CHECK: vsdot.s8 q0, q1, d4[1]
#CHECK-ERROR: stc2 p13, c0, [r1], #-72
#CHECK-ERROR: stc2 p13, c0, [r1], #-8
#CHECK-ERROR: stc2 p13, c0, [r2], #-352
#CHECK-ERROR: stc2 p13, c0, [r2], #-288
#CHECK-ERROR: mcr2 p13, #1, r0, c1, c2, #0
#CHECK-ERROR: cdp2 p13, #2, c0, c1, c2, #1
#CHECK-ERROR: mcr2 p13, #1, r0, c2, c4, #2
#CHECK-ERROR: cdp2 p13, #2, c0, c2, c4, #3

10
external/llvm/test/MC/Disassembler/ARM/armv8.3a-js-arm.txt vendored Normal file
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@@ -0,0 +1,10 @@
# RUN: llvm-mc -triple arm-none-eabi -mattr=+v8.3a,+fp-armv8 --disassemble < %s 2>&1 | FileCheck %s
# RUN: not llvm-mc -triple arm-none-eabi -mattr=+v8.2a,+fp-armv8 --disassemble < %s 2>&1 | FileCheck %s --check-prefix=UNDEF
# RUN: not llvm-mc -triple arm-none-eabi -mattr=+v8.3a,-fp-armv8 --disassemble < %s 2>&1 | FileCheck %s --check-prefix=UNDEF
[0xc2,0x0b,0xf9,0xee]
# CHECK: vjcvt.s32.f64 s1, d2
# UNDEF: :[[@LINE-2]]:{{[0-9]+}}: warning: invalid instruction encoding
[0xe2,0x8b,0xf9,0xee]
# CHECK: vjcvt.s32.f64 s17, d18
# UNDEF: :[[@LINE-2]]:{{[0-9]+}}: warning: invalid instruction encoding

10
external/llvm/test/MC/Disassembler/ARM/armv8.3a-js-thumb.txt vendored Normal file
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@@ -0,0 +1,10 @@
# RUN: llvm-mc -triple thumb-none-eabi -mattr=+v8.3a,+fp-armv8 --disassemble < %s 2>&1 | FileCheck %s
# RUN: not llvm-mc -triple thumb-none-eabi -mattr=+v8.2a,+fp-armv8 --disassemble < %s 2>&1 | FileCheck %s --check-prefix=UNDEF
# RUN: not llvm-mc -triple thumb-none-eabi -mattr=+v8.3a,-fp-armv8 --disassemble < %s 2>&1 | FileCheck %s --check-prefix=UNDEF
[0xf9,0xee,0xc2,0x0b]
# CHECK: vjcvt.s32.f64 s1, d2
# UNDEF: :[[@LINE-2]]:{{[0-9]+}}: warning: invalid instruction encoding
[0xf9,0xee,0xe2,0x8b]
# CHECK: vjcvt.s32.f64 s17, d18
# UNDEF: :[[@LINE-2]]:{{[0-9]+}}: warning: invalid instruction encoding

58
external/llvm/test/MC/Disassembler/ARM/basic-arm-instructions-v8.txt vendored Normal file
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@@ -0,0 +1,58 @@
# RUN: llvm-mc -disassemble -triple armv8 -mattr=+db -show-encoding < %s | FileCheck %s
# New v8 ARM instructions
# HLT
0x70 0x00 0x00 0xe1
# CHECK: hlt #0
0x7f 0xff 0x0f 0xe1
# CHECK: hlt #65535
0x59 0xf0 0x7f 0xf5
0x51 0xf0 0x7f 0xf5
0x55 0xf0 0x7f 0xf5
0x5d 0xf0 0x7f 0xf5
# CHECK: dmb ishld
# CHECK: dmb oshld
# CHECK: dmb nshld
# CHECK: dmb ld
0x05 0xf0 0x20 0xe3
# CHECK: sevl
# These are the only coprocessor instructions that remain defined in ARMv8
# (The operations on p10/p11 disassemble into FP/NEON instructions)
0x10 0x0e 0x00 0xee
# CHECK: mcr p14
0x10 0x0f 0x00 0xee
# CHECK: mcr p15
0x10 0x0e 0x10 0xee
# CHECK: mrc p14
0x10 0x0f 0x10 0xee
# CHECK: mrc p15
0x00 0x0e 0x40 0xec
# CHECK: mcrr p14
0x00 0x0f 0x40 0xec
# CHECK: mcrr p15
0x00 0x0e 0x50 0xec
# CHECK: mrrc p14
0x00 0x0f 0x50 0xec
# CHECK: mrrc p15
0x00 0x0e 0x80 0xec
# CHECK: stc p14
0x00 0x0e 0x90 0xec
# CHECK: ldc p14

2537
external/llvm/test/MC/Disassembler/ARM/basic-arm-instructions.txt vendored Normal file
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15
external/llvm/test/MC/Disassembler/ARM/crc32-thumb.txt vendored Normal file
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@@ -0,0 +1,15 @@
# RUN: llvm-mc --disassemble %s -triple=thumbv8 2>&1 | FileCheck %s
# CHECK: crc32b r0, r1, r2
# CHECK: crc32h r0, r1, r2
# CHECK: crc32w r0, r1, r2
# CHECK: crc32cb r0, r1, r2
# CHECK: crc32ch r0, r1, r2
# CHECK: crc32cw r0, r1, r2
0xc1 0xfa 0x82 0xf0
0xc1 0xfa 0x92 0xf0
0xc1 0xfa 0xa2 0xf0
0xd1 0xfa 0x82 0xf0
0xd1 0xfa 0x92 0xf0
0xd1 0xfa 0xa2 0xf0

15
external/llvm/test/MC/Disassembler/ARM/crc32.txt vendored Normal file
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@@ -0,0 +1,15 @@
# RUN: llvm-mc --disassemble %s -triple=armv8 2>&1 | FileCheck %s
# CHECK: crc32b r0, r1, r2
# CHECK: crc32h r0, r1, r2
# CHECK: crc32w r0, r1, r2
# CHECK: crc32cb r0, r1, r2
# CHECK: crc32ch r0, r1, r2
# CHECK: crc32cw r0, r1, r2
0x42 0x00 0x01 0xe1
0x42 0x00 0x21 0xe1
0x42 0x00 0x41 0xe1
0x42 0x02 0x01 0xe1
0x42 0x02 0x21 0xe1
0x42 0x02 0x41 0xe1

23
external/llvm/test/MC/Disassembler/ARM/d16.txt vendored Normal file
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@@ -0,0 +1,23 @@
# RUN: llvm-mc < %s -triple thumbv7-unknown-unknown -disassemble -mattr=+vfp4,-d16 2>&1 | FileCheck %s --check-prefix=D32
# RUN: llvm-mc < %s -triple thumbv7-unknown-unknown -disassemble -mattr=+vfp4,-d16 2>&1 | FileCheck %s --check-prefix=D32
# D32: vadd.f64 d1, d2, d16
# D16: warning: invalid instruction encoding
[0x32,0xee,0x20,0x1b]
# D32: vadd.f64 d1, d17, d6
# D16: warning: invalid instruction encoding
[0x31,0xee,0x86,0x1b]
# D32: vadd.f64 d19, d7, d6
# D16: warning: invalid instruction encoding
[0x77,0xee,0x06,0x3b]
# D32: vcvt.f64.f32 d22, s4
# D16: warning: invalid instruction encoding
[0xf7,0xee,0xc2,0x6a]
# D32: vcvt.f32.f64 s26, d30
# D16: warning: invalid instruction encoding
[0xb7,0xee,0xee,0xdb]

6
external/llvm/test/MC/Disassembler/ARM/dfb-arm.txt vendored Normal file
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@@ -0,0 +1,6 @@
# RUN: llvm-mc -disassemble -triple armv8-none-eabi -mcpu=cortex-r52 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DFB
# RUN: llvm-mc -disassemble -triple armv8-none-eabi -mcpu=cortex-r52 -mattr=-dfb -show-encoding < %s | FileCheck %s --check-prefix=CHECK-NODFB
# CHECK-DFB: dfb @ encoding: [0x4c,0xf0,0x7f,0xf5]
# CHECK-NODFB: dsb #0xc @ encoding: [0x4c,0xf0,0x7f,0xf5]
[0x4c,0xf0,0x7f,0xf5]

6
external/llvm/test/MC/Disassembler/ARM/dfb-thumb.txt vendored Normal file
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@@ -0,0 +1,6 @@
# RUN: llvm-mc -disassemble -triple thumbv8-none-eabi -mcpu=cortex-r52 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DFB
# RUN: llvm-mc -disassemble -triple thumbv8-none-eabi -mcpu=cortex-r52 -mattr=-dfb -show-encoding < %s | FileCheck %s --check-prefix=CHECK-NODFB
# CHECK-DFB: dfb @ encoding: [0xbf,0xf3,0x4c,0x8f]
# CHECK-NODFB: dsb #0xc @ encoding: [0xbf,0xf3,0x4c,0x8f]
[0xbf,0xf3,0x4c,0x8f]

160
external/llvm/test/MC/Disassembler/ARM/fp-armv8.txt vendored Normal file
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@@ -0,0 +1,160 @@
# RUN: llvm-mc -disassemble -triple armv8 -mattr=+fp-armv8 -show-encoding < %s | FileCheck %s
0xe0 0x3b 0xb2 0xee
# CHECK: vcvtt.f64.f16 d3, s1
0xcc 0x2b 0xf3 0xee
# CHECK: vcvtt.f16.f64 s5, d12
0x60 0x3b 0xb2 0xee
# CHECK: vcvtb.f64.f16 d3, s1
0x41 0x2b 0xb3 0xee
# CHECK: vcvtb.f16.f64 s4, d1
0xe0 0x3b 0xb2 0xae
# CHECK: vcvttge.f64.f16 d3, s1
0xcc 0x2b 0xf3 0xce
# CHECK: vcvttgt.f16.f64 s5, d12
0x60 0x3b 0xb2 0x0e
# CHECK: vcvtbeq.f64.f16 d3, s1
0x41 0x2b 0xb3 0xbe
# CHECK: vcvtblt.f16.f64 s4, d1
0xe1 0x1a 0xbc 0xfe
# CHECK: vcvta.s32.f32 s2, s3
0xc3 0x1b 0xbc 0xfe
# CHECK: vcvta.s32.f64 s2, d3
0xeb 0x3a 0xbd 0xfe
# CHECK: vcvtn.s32.f32 s6, s23
0xe7 0x3b 0xbd 0xfe
# CHECK: vcvtn.s32.f64 s6, d23
0xc2 0x0a 0xbe 0xfe
# CHECK: vcvtp.s32.f32 s0, s4
0xc4 0x0b 0xbe 0xfe
# CHECK: vcvtp.s32.f64 s0, d4
0xc4 0x8a 0xff 0xfe
# CHECK: vcvtm.s32.f32 s17, s8
0xc8 0x8b 0xff 0xfe
# CHECK: vcvtm.s32.f64 s17, d8
0x61 0x1a 0xbc 0xfe
# CHECK: vcvta.u32.f32 s2, s3
0x43 0x1b 0xbc 0xfe
# CHECK: vcvta.u32.f64 s2, d3
0x6b 0x3a 0xbd 0xfe
# CHECK: vcvtn.u32.f32 s6, s23
0x67 0x3b 0xbd 0xfe
# CHECK: vcvtn.u32.f64 s6, d23
0x42 0x0a 0xbe 0xfe
# CHECK: vcvtp.u32.f32 s0, s4
0x44 0x0b 0xbe 0xfe
# CHECK: vcvtp.u32.f64 s0, d4
0x44 0x8a 0xff 0xfe
# CHECK: vcvtm.u32.f32 s17, s8
0x48 0x8b 0xff 0xfe
# CHECK: vcvtm.u32.f64 s17, d8
0xab 0x2a 0x20 0xfe
# CHECK: vselge.f32 s4, s1, s23
0xa7 0xeb 0x6f 0xfe
# CHECK: vselge.f64 d30, d31, d23
0x80 0x0a 0x30 0xfe
# CHECK: vselgt.f32 s0, s1, s0
0x24 0x5b 0x3a 0xfe
# CHECK: vselgt.f64 d5, d10, d20
0x2b 0xfa 0x0e 0xfe
# CHECK: vseleq.f32 s30, s28, s23
0x08 0x2b 0x04 0xfe
# CHECK: vseleq.f64 d2, d4, d8
0x07 0xaa 0x58 0xfe
# CHECK: vselvs.f32 s21, s16, s14
0x2f 0x0b 0x11 0xfe
# CHECK: vselvs.f64 d0, d1, d31
0x00 0x2a 0xc6 0xfe
# CHECK: vmaxnm.f32 s5, s12, s0
0xae 0x5b 0x86 0xfe
# CHECK: vmaxnm.f64 d5, d22, d30
0x46 0x0a 0x80 0xfe
# CHECK: vminnm.f32 s0, s0, s12
0x49 0x4b 0x86 0xfe
# CHECK: vminnm.f64 d4, d6, d9
0xcc 0x3b 0xb6 0xae
# CHECK: vrintzge.f64 d3, d12
0xcc 0x1a 0xf6 0xee
# CHECK: vrintz.f32 s3, s24
0x40 0x5b 0xb6 0xbe
# CHECK: vrintrlt.f64 d5, d0
0x64 0x0a 0xb6 0xee
# CHECK: vrintr.f32 s0, s9
0x6e 0xcb 0xf7 0x0e
# CHECK: vrintxeq.f64 d28, d30
0x47 0x5a 0xb7 0x6e
# CHECK: vrintxvs.f32 s10, s14
0x44 0x3b 0xb8 0xfe
# CHECK: vrinta.f64 d3, d4
0x60 0x6a 0xb8 0xfe
# CHECK: vrinta.f32 s12, s1
0x44 0x3b 0xb9 0xfe
# CHECK: vrintn.f64 d3, d4
0x60 0x6a 0xb9 0xfe
# CHECK: vrintn.f32 s12, s1
0x44 0x3b 0xba 0xfe
# CHECK: vrintp.f64 d3, d4
0x60 0x6a 0xba 0xfe
# CHECK: vrintp.f32 s12, s1
0x44 0x3b 0xbb 0xfe
# CHECK: vrintm.f64 d3, d4
0x60 0x6a 0xbb 0xfe
# CHECK: vrintm.f32 s12, s1
0x10 0xa 0xf5 0xee
# CHECK: vmrs r0, mvfr2

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