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Imported Upstream version 5.18.0.246
Former-commit-id: 0c7ce5b1a7851e13f22acfd379b7f9fb304e4833
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209
external/llvm/test/CodeGen/PowerPC/vec_shuffle_le.ll
vendored
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209
external/llvm/test/CodeGen/PowerPC/vec_shuffle_le.ll
vendored
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@ -0,0 +1,209 @@
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; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec -mattr=-vsx -mcpu=pwr7 | FileCheck %s
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define void @VPKUHUM_xy(<16 x i8>* %A, <16 x i8>* %B) {
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entry:
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; CHECK: VPKUHUM_xy:
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%tmp = load <16 x i8>, <16 x i8>* %A
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%tmp2 = load <16 x i8>, <16 x i8>* %B
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%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
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; CHECK: lvx [[REG1:[0-9]+]]
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; CHECK: lvx [[REG2:[0-9]+]]
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; CHECK: vpkuhum [[REG3:[0-9]+]], [[REG2]], [[REG1]]
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store <16 x i8> %tmp3, <16 x i8>* %A
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ret void
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}
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define void @VPKUHUM_xx(<16 x i8>* %A) {
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entry:
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; CHECK: VPKUHUM_xx:
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%tmp = load <16 x i8>, <16 x i8>* %A
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%tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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; CHECK: vpkuhum
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store <16 x i8> %tmp2, <16 x i8>* %A
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ret void
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}
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define void @VPKUWUM_xy(<16 x i8>* %A, <16 x i8>* %B) {
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entry:
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; CHECK: VPKUWUM_xy:
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%tmp = load <16 x i8>, <16 x i8>* %A
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%tmp2 = load <16 x i8>, <16 x i8>* %B
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%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 1, i32 4, i32 5, i32 8, i32 9, i32 12, i32 13, i32 16, i32 17, i32 20, i32 21, i32 24, i32 25, i32 28, i32 29>
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; CHECK: lvx [[REG1:[0-9]+]]
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; CHECK: lvx [[REG2:[0-9]+]]
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; CHECK: vpkuwum [[REG3:[0-9]+]], [[REG2]], [[REG1]]
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store <16 x i8> %tmp3, <16 x i8>* %A
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ret void
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}
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define void @VPKUWUM_xx(<16 x i8>* %A) {
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entry:
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; CHECK: VPKUWUM_xx:
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%tmp = load <16 x i8>, <16 x i8>* %A
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%tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 1, i32 4, i32 5, i32 8, i32 9, i32 12, i32 13, i32 0, i32 1, i32 4, i32 5, i32 8, i32 9, i32 12, i32 13>
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; CHECK: vpkuwum
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store <16 x i8> %tmp2, <16 x i8>* %A
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ret void
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}
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define void @VMRGLB_xy(<16 x i8>* %A, <16 x i8>* %B) {
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entry:
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; CHECK: VMRGLB_xy:
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%tmp = load <16 x i8>, <16 x i8>* %A
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%tmp2 = load <16 x i8>, <16 x i8>* %B
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%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
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; CHECK: lvx [[REG1:[0-9]+]]
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; CHECK: lvx [[REG2:[0-9]+]]
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; CHECK: vmrglb [[REG3:[0-9]+]], [[REG2]], [[REG1]]
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store <16 x i8> %tmp3, <16 x i8>* %A
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ret void
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}
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define void @VMRGLB_xx(<16 x i8>* %A) {
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entry:
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; CHECK: VMRGLB_xx:
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%tmp = load <16 x i8>, <16 x i8>* %A
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%tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 0, i32 1, i32 1, i32 2, i32 2, i32 3, i32 3, i32 4, i32 4, i32 5, i32 5, i32 6, i32 6, i32 7, i32 7>
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; CHECK: vmrglb
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store <16 x i8> %tmp2, <16 x i8>* %A
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ret void
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}
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define void @VMRGHB_xy(<16 x i8>* %A, <16 x i8>* %B) {
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entry:
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; CHECK: VMRGHB_xy:
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%tmp = load <16 x i8>, <16 x i8>* %A
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%tmp2 = load <16 x i8>, <16 x i8>* %B
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%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
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; CHECK: lvx [[REG1:[0-9]+]]
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; CHECK: lvx [[REG2:[0-9]+]]
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; CHECK: vmrghb [[REG3:[0-9]+]], [[REG2]], [[REG1]]
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store <16 x i8> %tmp3, <16 x i8>* %A
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ret void
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}
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define void @VMRGHB_xx(<16 x i8>* %A) {
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entry:
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; CHECK: VMRGHB_xx:
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%tmp = load <16 x i8>, <16 x i8>* %A
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%tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 8, i32 8, i32 9, i32 9, i32 10, i32 10, i32 11, i32 11, i32 12, i32 12, i32 13, i32 13, i32 14, i32 14, i32 15, i32 15>
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; CHECK: vmrghb
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store <16 x i8> %tmp2, <16 x i8>* %A
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ret void
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}
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define void @VMRGLH_xy(<16 x i8>* %A, <16 x i8>* %B) {
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entry:
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; CHECK: VMRGLH_xy:
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%tmp = load <16 x i8>, <16 x i8>* %A
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%tmp2 = load <16 x i8>, <16 x i8>* %B
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%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 1, i32 16, i32 17, i32 2, i32 3, i32 18, i32 19, i32 4, i32 5, i32 20, i32 21, i32 6, i32 7, i32 22, i32 23>
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; CHECK: lvx [[REG1:[0-9]+]]
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; CHECK: lvx [[REG2:[0-9]+]]
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; CHECK: vmrglh [[REG3:[0-9]+]], [[REG2]], [[REG1]]
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store <16 x i8> %tmp3, <16 x i8>* %A
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ret void
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}
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define void @VMRGLH_xx(<16 x i8>* %A) {
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entry:
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; CHECK: VMRGLH_xx:
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%tmp = load <16 x i8>, <16 x i8>* %A
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%tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 1, i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 4, i32 5, i32 4, i32 5, i32 6, i32 7, i32 6, i32 7>
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; CHECK: vmrglh
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store <16 x i8> %tmp2, <16 x i8>* %A
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ret void
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}
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define void @VMRGHH_xy(<16 x i8>* %A, <16 x i8>* %B) {
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entry:
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; CHECK: VMRGHH_xy:
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%tmp = load <16 x i8>, <16 x i8>* %A
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%tmp2 = load <16 x i8>, <16 x i8>* %B
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%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 9, i32 24, i32 25, i32 10, i32 11, i32 26, i32 27, i32 12, i32 13, i32 28, i32 29, i32 14, i32 15, i32 30, i32 31>
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; CHECK: lvx [[REG1:[0-9]+]]
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; CHECK: lvx [[REG2:[0-9]+]]
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; CHECK: vmrghh [[REG3:[0-9]+]], [[REG2]], [[REG1]]
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store <16 x i8> %tmp3, <16 x i8>* %A
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ret void
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}
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define void @VMRGHH_xx(<16 x i8>* %A) {
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entry:
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; CHECK: VMRGHH_xx:
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%tmp = load <16 x i8>, <16 x i8>* %A
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%tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 8, i32 9, i32 8, i32 9, i32 10, i32 11, i32 10, i32 11, i32 12, i32 13, i32 12, i32 13, i32 14, i32 15, i32 14, i32 15>
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; CHECK: vmrghh
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store <16 x i8> %tmp2, <16 x i8>* %A
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ret void
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}
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define void @VMRGLW_xy(<16 x i8>* %A, <16 x i8>* %B) {
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entry:
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; CHECK: VMRGLW_xy:
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%tmp = load <16 x i8>, <16 x i8>* %A
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%tmp2 = load <16 x i8>, <16 x i8>* %B
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%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 16, i32 17, i32 18, i32 19, i32 4, i32 5, i32 6, i32 7, i32 20, i32 21, i32 22, i32 23>
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; CHECK: lvx [[REG1:[0-9]+]]
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; CHECK: lvx [[REG2:[0-9]+]]
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; CHECK: vmrglw [[REG3:[0-9]+]], [[REG2]], [[REG1]]
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store <16 x i8> %tmp3, <16 x i8>* %A
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ret void
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}
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define void @VMRGLW_xx(<16 x i8>* %A) {
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entry:
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; CHECK: VMRGLW_xx:
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%tmp = load <16 x i8>, <16 x i8>* %A
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%tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7>
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; CHECK: vmrglw
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store <16 x i8> %tmp2, <16 x i8>* %A
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ret void
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}
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define void @VMRGHW_xy(<16 x i8>* %A, <16 x i8>* %B) {
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entry:
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; CHECK: VMRGHW_xy:
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%tmp = load <16 x i8>, <16 x i8>* %A
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%tmp2 = load <16 x i8>, <16 x i8>* %B
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%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 24, i32 25, i32 26, i32 27, i32 12, i32 13, i32 14, i32 15, i32 28, i32 29, i32 30, i32 31>
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; CHECK: lvx [[REG1:[0-9]+]]
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; CHECK: lvx [[REG2:[0-9]+]]
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; CHECK: vmrghw [[REG3:[0-9]+]], [[REG2]], [[REG1]]
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store <16 x i8> %tmp3, <16 x i8>* %A
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ret void
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}
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define void @VMRGHW_xx(<16 x i8>* %A) {
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entry:
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; CHECK: VMRGHW_xx:
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%tmp = load <16 x i8>, <16 x i8>* %A
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%tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15>
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; CHECK: vmrghw
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store <16 x i8> %tmp2, <16 x i8>* %A
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ret void
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}
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define void @VSLDOI_xy(<16 x i8>* %A, <16 x i8>* %B) {
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entry:
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; CHECK: VSLDOI_xy:
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%tmp = load <16 x i8>, <16 x i8>* %A
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%tmp2 = load <16 x i8>, <16 x i8>* %B
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%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27>
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; CHECK: lvx [[REG1:[0-9]+]]
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; CHECK: lvx [[REG2:[0-9]+]]
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; CHECK: vsldoi [[REG3:[0-9]+]], [[REG2]], [[REG1]], 4
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store <16 x i8> %tmp3, <16 x i8>* %A
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ret void
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}
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define void @VSLDOI_xx(<16 x i8>* %A) {
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entry:
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; CHECK: VSLDOI_xx:
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%tmp = load <16 x i8>, <16 x i8>* %A
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%tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>
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; CHECK: vsldoi {{[0-9]+}}, [[REG1:[0-9]+]], [[REG1]], 4
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store <16 x i8> %tmp2, <16 x i8>* %A
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ret void
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}
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