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Imported Upstream version 5.18.0.246

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Former-commit-id: 0c7ce5b1a7851e13f22acfd379b7f9fb304e4833
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Xamarin Public Jenkins (auto-signing)
2019-01-23 08:21:40 +00:00
parent a7724cd563
commit 279aa8f685
28482 changed files with 3866972 additions and 44 deletions
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33
external/llvm/test/CodeGen/PowerPC/fast-isel-fpconv.ll vendored Normal file
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; RUN: llc -verify-machineinstrs -mtriple powerpc64-unknown-linux-gnu -fast-isel -O0 < %s | FileCheck %s
; The second fctiwz would use an incorrect input register due to wrong handling
; of COPY_TO_REGCLASS in the FastISel pass. Verify that this is fixed.
declare void @func(i32, i32)
define void @test() {
; CHECK-LABEL: test:
; CHECK: bl func
; CHECK-NEXT: nop
; CHECK: lfs [[REG:[0-9]+]],
; CHECK: fctiwz {{[0-9]+}}, [[REG]]
; CHECK: bl func
; CHECK-NEXT: nop
%memPos = alloca float, align 4
store float 1.500000e+01, float* %memPos
%valPos = load float, float* %memPos
%memNeg = alloca float, align 4
store float -1.500000e+01, float* %memNeg
%valNeg = load float, float* %memNeg
%FloatToIntPos = fptosi float %valPos to i32
call void @func(i32 15, i32 %FloatToIntPos)
%FloatToIntNeg = fptosi float %valNeg to i32
call void @func(i32 -15, i32 %FloatToIntNeg)
ret void
}