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Imported Upstream version 5.18.0.246

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Former-commit-id: 0c7ce5b1a7851e13f22acfd379b7f9fb304e4833
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Xamarin Public Jenkins (auto-signing)
2019-01-23 08:21:40 +00:00
parent a7724cd563
commit 279aa8f685
28482 changed files with 3866972 additions and 44 deletions
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22
external/llvm/test/CodeGen/PowerPC/dcbt-sched.ll vendored Normal file
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
; RUN: llc -verify-machineinstrs -mcpu=a2 -enable-misched -enable-aa-sched-mi < %s | FileCheck %s
define i8 @test1(i8* noalias %a, i8* noalias %b, i8* noalias %c) nounwind {
entry:
%q = load i8, i8* %b
call void @llvm.prefetch(i8* %a, i32 0, i32 3, i32 1)
%r = load i8, i8* %c
%s = add i8 %q, %r
ret i8 %s
}
declare void @llvm.prefetch(i8*, i32, i32, i32)
; Test that we've moved the second load to before the dcbt to better
; hide its latency.
; CHECK: @test1
; CHECK: lbz
; CHECK: lbz
; CHECK: dcbt