Imported Upstream version 5.18.0.246

Former-commit-id: 0c7ce5b1a7851e13f22acfd379b7f9fb304e4833

external/llvm/test/CodeGen/Mips/compactbranches/beqc-bnec-register-constraint.ll

@@ -0,0 +1,95 @@
+; RUN: llc -march=mips -mcpu=mips32r6 -O1 -start-after=dwarfehprepare < %s | FileCheck %s
+; RUN: llc -march=mips64 -mcpu=mips64r6 -O1 -start-after=dwarfehprepare < %s | FileCheck %s
+
+
+; beqc/bnec have the constraint that $rs < $rt && $rs != 0 && $rt != 0
+; Cases where $rs == 0 and $rt != 0 should be transformed into beqzc/bnezc.
+; Cases where $rs > $rt can have the operands swapped as ==,!= are commutative.
+
+; Cases where beq & bne where $rs == $rt have to inhibited from being turned
+; into compact branches but arguably should not occur. This test covers the
+; $rs == $rt case.
+
+; Starting from dwarf exception handling preparation skips optimizations that
+; may simplify out the crucical bnec $4, $4 instruction.
+
+define internal void @_ZL14TestRemoveLastv(i32* %alist.sroa.0.4) {
+; CHECK-LABEL: _ZL14TestRemoveLastv:
+entry:
+  %ascevgep = getelementptr i32, i32* %alist.sroa.0.4, i64 99
+  br label %do.body121
+
+for.cond117:
+  %alsr.iv.next = add nsw i32 %alsr.iv, -1
+  %ascevgep340 = getelementptr i32, i32* %alsr.iv339, i64 -1
+  %acmp118 = icmp sgt i32 %alsr.iv.next, 0
+  br i1 %acmp118, label %do.body121, label %if.then143
+
+do.body121:
+  %alsr.iv339 = phi i32* [ %ascevgep, %entry ], [ %ascevgep340, %for.cond117 ]
+  %alsr.iv = phi i32 [ 100, %entry ], [ %alsr.iv.next, %for.cond117 ]
+  %a9 = add i32 %alsr.iv, -1
+  %alnot124 = icmp eq i32 %alsr.iv, %alsr.iv
+  br i1 %alnot124, label %do.body134, label %if.then143, !prof !11
+
+do.body134:
+  %a10 = add i32 %alsr.iv, -1
+  %a11 = load i32, i32* %alsr.iv339, align 4, !tbaa !5
+; CHECK-NOT: bnec $[[R0:[0-9]+]], $[[R0]]
+; CHECK-NOT: beqc $[[R1:[0-9]+]], $[[R1]]
+  %alnot137 = icmp eq i32 %a9, %a11
+  br i1 %alnot137, label %do.end146, label %if.then143, !prof !11
+
+if.then143:
+ ret void
+ unreachable
+
+do.end146:
+  %alnot151 = icmp eq i32 %a9, %a10
+  br i1 %alnot151, label %for.cond117, label %if.then143, !prof !11
+
+}
+
+define internal void @_ZL14TestRemoveLastv64(i64* %alist.sroa.0.4) {
+; CHECK-LABEL: _ZL14TestRemoveLastv64:
+entry:
+  %ascevgep = getelementptr i64, i64* %alist.sroa.0.4, i64 99
+  br label %do.body121
+
+for.cond117:
+  %alsr.iv.next = add nsw i64 %alsr.iv, -1
+  %ascevgep340 = getelementptr i64, i64* %alsr.iv339, i64 -1
+  %acmp118 = icmp sgt i64 %alsr.iv.next, 0
+  br i1 %acmp118, label %do.body121, label %if.then143
+
+do.body121:
+  %alsr.iv339 = phi i64* [ %ascevgep, %entry ], [ %ascevgep340, %for.cond117 ]
+  %alsr.iv = phi i64 [ 100, %entry ], [ %alsr.iv.next, %for.cond117 ]
+  %a9 = add i64 %alsr.iv, -1
+  %alnot124 = icmp eq i64 %alsr.iv, %alsr.iv
+  br i1 %alnot124, label %do.body134, label %if.then143, !prof !11
+
+do.body134:
+  %a10 = add i64 %alsr.iv, -1
+  %a11 = load i64, i64* %alsr.iv339, align 4, !tbaa !5
+; CHECK-NOT: bnec $[[R0:[0-9]+]], $[[R0]]
+; CHECK-NOT: beqc $[[R1:[0-9]+]], $[[R1]]
+  %alnot137 = icmp eq i64 %a9, %a11
+  br i1 %alnot137, label %do.end146, label %if.then143, !prof !11
+
+if.then143:
+ ret void
+ unreachable
+
+do.end146:
+  %alnot151 = icmp eq i64 %a9, %a10
+  br i1 %alnot151, label %for.cond117, label %if.then143, !prof !11
+
+}
+!3 = !{!"omnipotent char", !4, i64 0}
+!4 = !{!"Simple C++ TBAA"}
+!5 = !{!6, !6, i64 0}
+!6 = !{!"int", !3, i64 0}
+!11 = !{!"branch_weights", i32 2000, i32 1}
+!12 = !{!"branch_weights", i32 -388717296, i32 7818360}
+

external/llvm/test/CodeGen/Mips/compactbranches/compact-branch-implicit-def.mir

@@ -0,0 +1,158 @@
+# RUN: llc -march=mips64 -mcpu=mips64r6 -start-after=block-placement -o - %s | FileCheck %s
+
+# Check that MipsHazardSchedule sees through basic blocks with transient instructions.
+# The mir code in this file isn't representative of the llvm-ir.
+
+--- |
+  ; ModuleID = 'test.ll'
+  source_filename = "test.c"
+  target datalayout = "E-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"
+  target triple = "mips64-img-linux-gnu"
+
+  ; Function Attrs: nounwind
+  define i32 @f(i32 signext %a) {
+  entry:
+    %retval = alloca i32, align 4
+    %a.addr = alloca i32, align 4
+    store i32 %a, i32* %a.addr, align 4
+    %0 = load i32, i32* %a.addr, align 4
+    %cmp = icmp sgt i32 %0, 5
+    br i1 %cmp, label %if.then, label %if.else
+
+  if.then:                                          ; preds = %entry
+    %1 = load i32, i32* %a.addr, align 4
+    %2 = load i32, i32* %a.addr, align 4
+    %add = add nsw i32 %1, %2
+    store i32 %add, i32* %retval, align 4
+    br label %return
+
+  if.else:                                          ; preds = %entry
+    %3 = load i32, i32* %a.addr, align 4
+    %call = call i32 @g(i32 signext %3)
+    store i32 %call, i32* %retval, align 4
+    br label %return
+
+  return:                                           ; preds = %if.else, %if.then
+    %4 = load i32, i32* %retval, align 4
+    ret i32 %4
+  }
+
+  declare i32 @g(i32 signext)
+
+  ; Function Attrs: nounwind
+  declare void @llvm.stackprotector(i8*, i8**)
+
+  !llvm.ident = !{!0}
+
+  !0 = !{!"clang version 4.0.0 "}
+
+...
+---
+# CHECK-LABEL: f:
+# CHECK: bgtzc
+# CHECK-NEXT: nop
+# CHECK: bltzc
+# CHECK-NEXT: nop
+# CHECK: blezc
+name:            f
+alignment:       3
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+liveins:
+  - { reg: '%a0_64' }
+  - { reg: '%t9_64' }
+calleeSavedRegisters: [ '%fp', '%gp', '%ra', '%d12', '%d13', '%d14', '%d15',
+                        '%f24', '%f25', '%f26', '%f27', '%f28', '%f29',
+                        '%f30', '%f31', '%fp_64', '%f_hi24', '%f_hi25',
+                        '%f_hi26', '%f_hi27', '%f_hi28', '%f_hi29', '%f_hi30',
+                        '%f_hi31', '%gp_64', '%ra_64', '%s0', '%s1', '%s2',
+                        '%s3', '%s4', '%s5', '%s6', '%s7', '%d24_64', '%d25_64',
+                        '%d26_64', '%d27_64', '%d28_64', '%d29_64', '%d30_64',
+                        '%d31_64', '%s0_64', '%s1_64', '%s2_64', '%s3_64',
+                        '%s4_64', '%s5_64', '%s6_64', '%s7_64' ]
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       32
+  offsetAdjustment: 0
+  maxAlignment:    8
+  adjustsStack:    true
+  hasCalls:        true
+  maxCallFrameSize: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+stack:
+  - { id: 0, name: retval, offset: -28, size: 4, alignment: 4 }
+  - { id: 1, name: a.addr, offset: -32, size: 4, alignment: 4 }
+  - { id: 2, type: spill-slot, offset: -8, size: 8, alignment: 8, callee-saved-register: '%ra_64' }
+  - { id: 3, type: spill-slot, offset: -16, size: 8, alignment: 8, callee-saved-register: '%fp_64' }
+  - { id: 4, type: spill-slot, offset: -24, size: 8, alignment: 8, callee-saved-register: '%gp_64' }
+body:             |
+  bb.0.entry:
+    successors: %bb.1.if.then(0x40000000), %bb.5.if.else(0x40000000)
+    liveins: %a0_64, %t9_64, %ra_64, %fp_64, %gp_64
+
+    %sp_64 = DADDiu %sp_64, -32
+    CFI_INSTRUCTION def_cfa_offset 32
+    SD killed %ra_64, %sp_64, 24 :: (store 8 into %stack.2)
+    SD killed %fp_64, %sp_64, 16 :: (store 8 into %stack.3)
+    SD killed %gp_64, %sp_64, 8 :: (store 8 into %stack.4)
+    CFI_INSTRUCTION offset %ra_64, -8
+    CFI_INSTRUCTION offset %fp_64, -16
+    CFI_INSTRUCTION offset %gp_64, -24
+    CFI_INSTRUCTION def_cfa_register %fp_64
+    %at_64 = LUi64 @f
+    %v0_64 = DADDu killed %at_64, %t9_64
+    SW %a0, %sp_64, 0 :: (store 4 into %ir.a.addr)
+    BGTZC %a0, %bb.5.if.else, implicit-def %at
+
+  bb.1.if.then:
+    successors: %bb.6.return(0x40000000), %bb.2.if.then(0x40000000)
+    liveins: %a0
+
+    BLTZC %a0, %bb.6.return, implicit-def %at
+
+  bb.2.if.then:
+    successors: %bb.3.if.else(0x80000000)
+    %t8 = IMPLICIT_DEF
+
+  bb.3.if.else:
+    successors: %bb.6.return(0x40000000), %bb.4.if.else(0x40000000)
+    liveins: %t8
+
+    BLEZC %t8, %bb.6.return, implicit-def %at
+
+  bb.4.if.else:
+    successors: %bb.6.return(0x80000000)
+    liveins: %t8
+
+    %at = LW %sp_64, 0 :: (dereferenceable load 4 from %ir.a.addr)
+    %at = ADDu killed %at, %t8
+    SW killed %at, %sp_64, 4 :: (store 4 into %ir.retval)
+    J %bb.6.return, implicit-def dead %at
+
+  bb.5.if.else:
+    successors: %bb.6.return(0x80000000)
+    liveins: %v0_64
+
+    %gp_64 = DADDiu killed %v0_64, @f
+    %a0_64 = LW64 %sp_64, 0 :: (dereferenceable load 4 from %ir.a.addr)
+    %t9_64 = LD %gp_64, @g :: (load 8 from call-entry @g)
+    JALR64Pseudo %t9_64, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit %gp_64, implicit-def %sp, implicit-def %v0
+    SW killed %v0, %sp_64, 4 :: (store 4 into %ir.retval)
+
+  bb.6.return:
+    %v0 = LW %sp_64, 4 :: (dereferenceable load 4 from %ir.retval)
+    %gp_64 = LD %sp_64, 8 :: (load 8 from %stack.4)
+    %fp_64 = LD %sp_64, 16 :: (load 8 from %stack.3)
+    %ra_64 = LD %sp_64, 24 :: (load 8 from %stack.2)
+    %sp_64 = DADDiu %sp_64, 32
+    PseudoReturn64 %ra_64
+
+...

external/llvm/test/CodeGen/Mips/compactbranches/compact-branch-policy.ll

@@ -0,0 +1,28 @@
+; Check that -mips-compact-branches={never,optimal,always} is accepted and honoured.
+; RUN: llc -march=mips -mcpu=mips32r6 -mips-compact-branches=never < %s | FileCheck %s -check-prefix=NEVER
+; RUN: llc -march=mips -mcpu=mips32r6 -mips-compact-branches=optimal < %s | FileCheck %s -check-prefix=OPTIMAL
+; RUN: llc -march=mips -mcpu=mips32r6 -mips-compact-branches=always < %s | FileCheck %s -check-prefix=ALWAYS
+
+define i32 @l(i32 signext %a, i32 signext %b) {
+entry:
+  %add = add nsw i32 %b, %a
+  %cmp = icmp slt i32 %add, 100
+; NEVER: beq
+; OPTIMAL: beq
+; ALWAYS: beqzc
+; This nop is required for correct as having (j|b)al as the instruction
+; immediately following beqzc would cause a forbidden slot hazard.
+; ALWAYS: nop
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  %call = tail call i32 @k()
+  br label %if.end
+
+if.end:                                           ; preds = %entry, %if.then
+  %call.pn = phi i32 [ %call, %if.then ], [ -1, %entry ]
+  %c.0 = add nsw i32 %call.pn, %add
+  ret i32 %c.0
+}
+
+declare i32 @k() #1

external/llvm/test/CodeGen/Mips/compactbranches/compact-branches-64.ll

@@ -0,0 +1,195 @@
+; RUN: llc -relocation-model=pic -march=mipsel -mcpu=mips64r6 \
+; RUN:     -disable-mips-delay-filler -target-abi=n64 < %s | FileCheck %s
+
+; Function Attrs: nounwind
+define void @l() {
+entry:
+; CHECK-LABEL:  l:
+; CHECK: jalrc $25
+  %call = tail call i64 @k()
+; CHECK: jalrc $25
+  %call1 = tail call i64 @j()
+  %cmp = icmp eq i64 %call, %call1
+; CHECK: bnec
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry:
+; CHECK: jalrc $25
+  tail call void @f(i64 signext -2)
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+; CHECK: jrc  $ra
+  ret void
+}
+
+declare i64 @k()
+
+declare i64 @j()
+
+declare void @f(i64 signext)
+
+; Function Attrs: define void @l2() {
+define void @l2() {
+entry:
+; CHECK-LABEL: l2:
+; CHECK: jalrc $25
+  %call = tail call i64 @k()
+; CHECK: jalrc $25
+  %call1 = tail call i64 @i()
+  %cmp = icmp eq i64 %call, %call1
+; CHECK: beqc
+  br i1 %cmp, label %if.end, label %if.then
+
+if.then:                                          ; preds = %entry:
+; CHECK: jalrc $25
+  tail call void @f(i64 signext -1)
+  br label %if.end
+
+if.end:                                           ; preds = %entry, %if.then
+; CHECK: jrc  $ra
+  ret void
+}
+
+declare i64 @i()
+
+; Function Attrs: nounwind
+define void @l3() {
+entry:
+; CHECK-LABEL: l3:
+; CHECK: jalrc $25
+  %call = tail call i64 @k()
+  %cmp = icmp slt i64 %call, 0
+; CHECK: bgez
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry:
+; CHECK: jalrc $25
+  tail call void @f(i64 signext 0)
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+; CHECK: jrc $ra
+  ret void
+}
+
+; Function Attrs: nounwind
+define void @l4() {
+entry:
+; CHECK-LABEL: l4:
+; CHECK: jalrc $25
+  %call = tail call i64 @k()
+  %cmp = icmp slt i64 %call, 1
+; CHECK: bgtzc
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry:
+  tail call void @f(i64 signext 1)
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+; CHECK: jrc $ra
+  ret void
+}
+
+; Function Attrs: nounwind
+define void @l5() {
+entry:
+; CHECK-LABEL: l5:
+; CHECK: jalrc $25
+  %call = tail call i64 @k()
+  %cmp = icmp sgt i64 %call, 0
+; CHECK: blezc
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry:
+; CHECK: jalrc $25
+  tail call void @f(i64 signext 2)
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+; CHECK: jrc  $ra
+  ret void
+}
+
+; Function Attrs: nounwind
+define void @l6() {
+entry:
+; CHECK-LABEL: l6:
+; CHECK: jalrc $25
+  %call = tail call i64 @k()
+  %cmp = icmp sgt i64 %call, -1
+; CHECK: bltzc
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry:
+; CHECK: jalrc $25
+  tail call void @f(i64 signext 3)
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+; CHECK: jrc $ra
+  ret void
+}
+
+; Function Attrs: nounwind
+define void @l7() {
+entry:
+; CHECK-LABEL: l7:
+; CHECK: jalrc $25
+  %call = tail call i64 @k()
+  %cmp = icmp eq i64 %call, 0
+; CHECK: bnezc
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry:
+; CHECK: jalrc $25
+  tail call void @f(i64 signext 4)
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+; CHECK: jrc  $ra
+  ret void
+}
+
+; Function Attrs: nounwind
+define void @l8() {
+entry:
+; CHECK-LABEL: l8:
+; CHECK: jalrc $25
+  %call = tail call i64 @k()
+  %cmp = icmp eq i64 %call, 0
+; CHECK: beqzc
+  br i1 %cmp, label %if.end, label %if.then
+
+if.then:                                          ; preds = %entry:
+; CHECK: jalrc $25
+  tail call void @f(i64 signext 5)
+  br label %if.end
+
+if.end:                                           ; preds = %entry, %if.then
+; CHECK: jrc  $ra
+  ret void
+}
+
+define i64 @l9(i8* ()* %i) {
+entry:
+; CHECK-LABEL: l9:
+  %i.addr = alloca i8* ()*, align 4
+  store i8* ()* %i, i8* ()** %i.addr, align 4
+; CHECK: jalrc $25
+  %call = call i64 @k()
+  %cmp = icmp ne i64 %call, 0
+; CHECK: beqzc
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  %0 = load i8* ()*, i8* ()** %i.addr, align 4
+; CHECK: jalrc $25
+  %call1 = call i8* %0()
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+; CHECK: jrc $ra
+  ret i64 -1
+}

external/llvm/test/CodeGen/Mips/compactbranches/compact-branches.ll

@@ -0,0 +1,208 @@
+; RUN: llc -march=mipsel -mcpu=mips32r6 -relocation-model=static \
+; RUN:     -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=STATIC32
+; RUN: llc -march=mipsel -mcpu=mips64r6 -relocation-model=pic -target-abi n64 \
+; RUN:     -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=PIC
+
+; Function Attrs: nounwind
+define void @l()  {
+entry:
+; PIC: jalrc $25
+  %call = tail call i32 @k()
+; PIC: jalrc $25
+  %call1 = tail call i32 @j()
+  %cmp = icmp eq i32 %call, %call1
+; CHECK: bnec
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry:
+; STATIC: nop
+; STATIC: jal
+; PIC: jalrc $25
+  tail call void @f(i32 signext -2)
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+; CHECK: jrc  $ra
+  ret void
+}
+
+declare i32 @k()
+
+declare i32 @j()
+
+declare void @f(i32 signext) 
+
+; Function Attrs: define void @l2()  {
+define void @l2()  {
+entry:
+; PIC: jalrc $25
+  %call = tail call i32 @k()
+; PIC: jalrc $25
+  %call1 = tail call i32 @i()
+  %cmp = icmp eq i32 %call, %call1
+; CHECK: beqc
+  br i1 %cmp, label %if.end, label %if.then
+
+if.then:                                          ; preds = %entry:
+; STATIC: nop
+; STATIC: jal
+; PIC: jalrc $25
+  tail call void @f(i32 signext -1)
+  br label %if.end
+
+if.end:                                           ; preds = %entry, %if.then
+; CHECK: jrc  $ra
+  ret void
+}
+
+declare i32 @i()
+
+; Function Attrs: nounwind
+define void @l3()  {
+entry:
+; PIC: jalrc $25
+  %call = tail call i32 @k()
+  %cmp = icmp slt i32 %call, 0
+; CHECK: bgez
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry:
+; STATIC: nop
+; STATIC: jal
+; PIC: jalrc $25
+  tail call void @f(i32 signext 0)
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+; CHECK: jrc $ra
+  ret void
+}
+
+; Function Attrs: nounwind
+define void @l4()  {
+entry:
+  %call = tail call i32 @k()
+  %cmp = icmp slt i32 %call, 1
+; CHECK: bgtzc
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry:
+; STATIC: nop
+; STATIC: jal
+  tail call void @f(i32 signext 1)
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+; CHECK: jrc $ra
+  ret void
+}
+
+; Function Attrs: nounwind
+define void @l5()  {
+entry:
+; PIC: jalrc $25
+  %call = tail call i32 @k()
+; PIC: jalrc $25
+  %cmp = icmp sgt i32 %call, 0
+; CHECK: blezc
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry:
+; STATIC: nop
+; STATIC: jal
+; PIC: jalrc $25
+  tail call void @f(i32 signext 2) 
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+; CHECK: jrc  $ra
+  ret void
+}
+
+; Function Attrs: nounwind
+define void @l6()  {
+entry:
+; PIC: jalrc $25
+  %call = tail call i32 @k()
+; PIC: jalrc $25
+  %cmp = icmp sgt i32 %call, -1
+; CHECK: bltzc
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry:
+; STATIC: nop
+; STATIC: jal
+; PIC: jalrc $25
+  tail call void @f(i32 signext 3)
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+; CHECK: jrc $ra
+  ret void
+}
+
+; Function Attrs: nounwind
+define void @l7()  {
+entry:
+; PIC: jalrc $25
+  %call = tail call i32 @k()
+  %cmp = icmp eq i32 %call, 0
+; CHECK: bnezc
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry:
+; STATIC: nop
+; STATIC: jal
+; PIC: jalrc $25
+  tail call void @f(i32 signext 4)
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+; CHECK: jrc  $ra
+  ret void
+}
+
+; Function Attrs: nounwind
+define void @l8()  {
+entry:
+; PIC: jalrc $25
+  %call = tail call i32 @k()
+  %cmp = icmp eq i32 %call, 0
+; CHECK: beqzc
+  br i1 %cmp, label %if.end, label %if.then
+
+if.then:                                          ; preds = %entry:
+; STATIC: nop
+; STATIC: jal
+; PIC: jalrc $25
+  tail call void @f(i32 signext 5)
+  br label %if.end
+
+if.end:                                           ; preds = %entry, %if.then
+; CHECK: jrc  $ra
+  ret void
+}
+
+define i32 @l9(i8* ()* %i) #0 {
+entry:
+  %i.addr = alloca i8* ()*, align 4
+  store i8* ()* %i, i8* ()** %i.addr, align 4
+; STATIC32: jal
+; STATIC32: nop
+; PIC: jalrc $25
+  %call = call i32 @k()
+; PIC: jalrc $25
+  %cmp = icmp ne i32 %call, 0
+; CHECK: beqzc
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  %0 = load i8* ()*, i8* ()** %i.addr, align 4
+; CHECK: jalrc $25
+  %call1 = call i8* %0()
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+; CHECK: jrc $ra
+  ret i32 -1
+}

external/llvm/test/CodeGen/Mips/compactbranches/empty-block.mir

@@ -0,0 +1,91 @@
+# RUN: llc -march=mipsel -mcpu=mips32r6 -start-after=block-placement %s -o - | FileCheck %s
+
+# Check that empty blocks in the cfg don't cause the mips hazard scheduler to
+# crash and that the nop is inserted correctly.
+
+# CHECK:  blezc
+# CHECK:  nop
+# CHECK: # %bb.1:
+# CHECK:  .insn
+# CHECK: # %bb.2:
+# CHECK:  .insn
+# CHECK: # %bb.3:
+# CHECK:  jal
+
+--- |
+  ; ModuleID = '<stdin>'
+  source_filename = "<stdin>"
+  target datalayout = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"
+
+  declare i32 @k()
+
+  declare void @f(i32)
+
+  define void @l5() {
+  entry:
+    %call = tail call i32 @k()
+    %cmp = icmp sgt i32 %call, 0
+    br i1 %cmp, label %if.then, label %if.end
+
+  if.then:                                          ; preds = %entry
+    tail call void @f(i32 signext 2)
+    br label %if.end
+
+  if.end:                                           ; preds = %if.then, %entry
+    ret void
+  }
+
+---
+name:            l5
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       24
+  offsetAdjustment: 0
+  maxAlignment:    4
+  adjustsStack:    true
+  hasCalls:        true
+  maxCallFrameSize: 16
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+stack:
+  - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '%ra' }
+body:             |
+  bb.0.entry:
+    successors: %bb.1.if.then(0x50000000), %bb.4.if.end(0x30000000)
+    liveins: %ra
+
+    %sp = ADDiu %sp, -24
+    CFI_INSTRUCTION def_cfa_offset 24
+    SW killed %ra, %sp, 20 :: (store 4 into %stack.0)
+    CFI_INSTRUCTION offset %ra_64, -4
+    JAL @k, csr_o32_fp64, implicit-def dead %ra, implicit-def %sp, implicit-def %v0
+    BLEZ %v0, %bb.4.if.end, implicit-def %at
+
+  bb.1.if.then:
+    successors: %bb.2.if.then(0x80000000)
+
+  bb.2.if.then:
+    successors: %bb.3.if.then(0x80000000)
+
+  bb.3.if.then:
+    successors: %bb.4.if.end(0x80000000)
+
+    %a0 = ADDiu %zero, 2
+    JAL @f, csr_o32_fp64, implicit-def dead %ra, implicit killed %a0, implicit-def %sp
+
+  bb.4.if.end:
+    %ra = LW %sp, 20 :: (load 4 from %stack.0)
+    %sp = ADDiu %sp, 24
+    PseudoReturn undef %ra
+
+...

external/llvm/test/CodeGen/Mips/compactbranches/no-beqzc-bnezc.ll

@@ -0,0 +1,130 @@
+; RUN: llc -march=mipsel -mcpu=mips32r6 -disable-mips-delay-filler < %s | FileCheck %s
+; RUN: llc -march=mips -mcpu=mips32r6 -disable-mips-delay-filler < %s -filetype=obj \
+; RUN:     -o - | llvm-objdump -d - | FileCheck %s -check-prefix=ENCODING
+; RUN: llc -march=mipsel -mcpu=mips64r6 -disable-mips-delay-filler -target-abi=n64 < %s | FileCheck %s
+; RUN: llc -march=mips -mcpu=mips64r6 -disable-mips-delay-filler -target-abi=n64 < %s -filetype=obj \
+; RUN:     -o - | llvm-objdump -d - | FileCheck %s -check-prefix=ENCODING
+
+; bnezc and beqzc have restriction that $rt != 0
+
+define i32 @f() {
+; CHECK-LABEL: f:
+; CHECK-NOT:   bnezc $0
+
+  %cmp = icmp eq i32 1, 1
+  br i1 %cmp, label %if.then, label %if.end
+
+  if.then:
+    ret i32 1
+
+  if.end:
+    ret i32 0
+}
+
+define i32 @f1() {
+; CHECK-LABEL: f1:
+; CHECK-NOT:   beqzc $0
+
+  %cmp = icmp eq i32 0, 0
+  br i1 %cmp, label %if.then, label %if.end
+
+  if.then:
+    ret i32 1
+
+  if.end:
+    ret i32 0
+}
+
+; We silently fixup cases where the register allocator or user has given us
+; an instruction with incorrect operands that is trivially acceptable.
+; beqc and bnec have the restriction that $rs < $rt.
+
+define i32 @f2(i32 %a, i32 %b) {
+; ENCODING-LABEL: f2:
+; ENCODING-NOT:   beqc $5, $4
+; ENCODING-NOT:   bnec $5, $4
+
+  %cmp = icmp eq i32 %b, %a
+  br i1 %cmp, label %if.then, label %if.end
+
+  if.then:
+    ret i32 1
+
+  if.end:
+    ret i32 0
+}
+
+define i64 @f3() {
+; CHECK-LABEL: f3:
+; CHECK-NOT:   bnezc $0
+
+  %cmp = icmp eq i64 1, 1
+  br i1 %cmp, label %if.then, label %if.end
+
+  if.then:
+    ret i64 1
+
+  if.end:
+    ret i64 0
+}
+
+define i64 @f4() {
+; CHECK-LABEL: f4:
+; CHECK-NOT:   beqzc $0
+
+  %cmp = icmp eq i64 0, 0
+  br i1 %cmp, label %if.then, label %if.end
+
+  if.then:
+    ret i64 1
+
+  if.end:
+    ret i64 0
+}
+
+; We silently fixup cases where the register allocator or user has given us
+; an instruction with incorrect operands that is trivially acceptable.
+; beqc and bnec have the restriction that $rs < $rt.
+
+define i64 @f5(i64 %a, i64 %b) {
+; ENCODING-LABEL: f5:
+; ENCODING-NOT:   beqc $5, $4
+; ENCODING-NOT:   bnec $5, $4
+
+  %cmp = icmp eq i64 %b, %a
+  br i1 %cmp, label %if.then, label %if.end
+
+  if.then:
+    ret i64 1
+
+  if.end:
+    ret i64 0
+}
+
+define i32 @f6(i32 %a) {
+; CHECK-LABEL: f6:
+; CHECK: beqzc ${{[0-9]+}}, $BB
+
+  %cmp = icmp eq i32 %a, 0
+  br i1 %cmp, label %if.then, label %if.end
+
+  if.then:
+    ret i32 1
+
+  if.end:
+    ret i32 0
+}
+
+define i32 @f7(i32 %a) {
+; CHECK-LABEL: f7:
+; CHECK: bnezc ${{[0-9]+}}, $BB
+
+  %cmp = icmp eq i32 0, %a
+  br i1 %cmp, label %if.then, label %if.end
+
+  if.then:
+    ret i32 1
+
+  if.end:
+    ret i32 0
+}

external/llvm/test/CodeGen/Mips/compactbranches/unsafe-in-forbidden-slot.ll

@@ -0,0 +1,34 @@
+; RUN: llc -march=mips64el -O0 -mcpu=mips64r6 < %s | FileCheck %s
+; RUN: llc -march=mips64 -O0 -mcpu=mips64r6 < %s | FileCheck %s
+
+@boo = global i32 0, align 4
+
+; Function Attrs: nounwind
+define void @_Z3foov() #0 {
+entry:
+  %0 = load volatile i32, i32* @boo, align 4
+  switch i32 %0, label %sw.epilog [
+    i32 0, label %sw.bb
+    i32 1, label %sw.bb1
+    i32 2, label %sw.bb1
+  ]
+
+sw.bb:                                            ; preds = %entry
+  store volatile i32 1, i32* @boo, align 4
+  br label %sw.epilog
+; CHECK: beqzc
+; CHECK-NEXT: nop
+; CHECK-NEXT: .LBB
+; CHECK-NEXT: j
+
+sw.bb1:                                           ; preds = %entry, %entry
+  store volatile i32 2, i32* @boo, align 4
+  br label %sw.epilog
+; CHECK: bnezc
+; CHECK-NEXT: nop
+; CHECK-NEXT: .LBB
+; CHECK-NEXT: j
+
+sw.epilog:                                        ; preds = %entry, %sw.bb1, %sw.bb
+  ret void
+}