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Imported Upstream version 5.18.0.246
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153
external/llvm/test/CodeGen/ARM/apcs-vfp.ll
vendored
Normal file
153
external/llvm/test/CodeGen/ARM/apcs-vfp.ll
vendored
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; RUN: llc -mtriple=armv7k-apple-watchos2.0 < %s | FileCheck %s
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define arm_aapcs_vfpcc float @t1(float %a, float %b) {
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entry:
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; CHECK: t1
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; CHECK-NOT: vmov
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; CHECK: vadd.f32
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%a.addr = alloca float, align 4
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%b.addr = alloca float, align 4
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store float %a, float* %a.addr, align 4
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store float %b, float* %b.addr, align 4
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%0 = load float, float* %a.addr, align 4
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%1 = load float, float* %b.addr, align 4
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%add = fadd float %0, %1
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ret float %add
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}
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define arm_aapcs_vfpcc double @t2(double %a, double %b) {
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entry:
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; CHECK: t2
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; CHECK-NOT: vmov
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; CHECK: vadd.f64
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%a.addr = alloca double, align 8
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%b.addr = alloca double, align 8
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store double %a, double* %a.addr, align 8
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store double %b, double* %b.addr, align 8
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%0 = load double, double* %a.addr, align 8
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%1 = load double, double* %b.addr, align 8
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%add = fadd double %0, %1
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ret double %add
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}
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define arm_aapcs_vfpcc i64 @t3(double %ti) {
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entry:
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; CHECK-LABEL: t3:
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; CHECK-NOT: vmov
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; CHECK: bl ___fixunsdfdi
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%conv = fptoui double %ti to i64
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ret i64 %conv
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}
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define arm_aapcs_vfpcc i64 @t4(double %ti) {
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entry:
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; CHECK-LABEL: t4:
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; CHECK-NOT: vmov
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; CHECK: bl ___fixdfdi
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%conv = fptosi double %ti to i64
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ret i64 %conv
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}
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define arm_aapcs_vfpcc double @t5(i64 %ti) {
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entry:
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; CHECK-LABEL: t5:
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; CHECK: bl ___floatundidf
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; CHECK-NOT: vmov
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; CHECK: pop
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%conv = uitofp i64 %ti to double
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ret double %conv
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}
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define arm_aapcs_vfpcc double @t6(i64 %ti) {
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entry:
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; CHECK-LABEL: t6:
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; CHECK: bl ___floatdidf
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; CHECK-NOT: vmov
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; CHECK: pop
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%conv = sitofp i64 %ti to double
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ret double %conv
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}
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define arm_aapcs_vfpcc float @t7(i64 %ti) {
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entry:
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; CHECK-LABEL: t7:
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; CHECK: bl ___floatundisf
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; CHECK-NOT: vmov
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; CHECK: pop
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%conv = uitofp i64 %ti to float
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ret float %conv
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}
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define arm_aapcs_vfpcc float @t8(i64 %ti) {
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entry:
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; CHECK-LABEL: t8:
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; CHECK: bl ___floatdisf
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; CHECK-NOT: vmov
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; CHECK: pop
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%conv = sitofp i64 %ti to float
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ret float %conv
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}
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define arm_aapcs_vfpcc double @t9(double %d0, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, float %a, float %b) {
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entry:
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; CHECK-LABEL: t9:
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; CHECK-NOT: vmov
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; CHECK: vldr
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%add = fadd float %a, %b
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%conv = fpext float %add to double
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ret double %conv
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}
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define arm_aapcs_vfpcc double @t10(double %d0, double %d1, double %d2, double %d3, double %d4, double %d5, double %a, float %b, double %c) {
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entry:
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; CHECK-LABEL: t10:
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; CHECK-NOT: vmov
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; CHECK: vldr
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%add = fadd double %a, %c
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ret double %add
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}
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define arm_aapcs_vfpcc float @t11(double %d0, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, float %a, double %b, float %c) {
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entry:
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; CHECK-LABEL: t11:
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; CHECK: vldr
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%add = fadd float %a, %c
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ret float %add
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}
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define arm_aapcs_vfpcc double @t12(double %a, double %b) {
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entry:
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; CHECK-LABEL: t12:
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; CHECK: vstr
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%add = fadd double %a, %b
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%sub = fsub double %a, %b
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%call = tail call arm_aapcs_vfpcc double @x(double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double %add, float 0.000000e+00, double %sub)
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ret double %call
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}
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define arm_aapcs_vfpcc double @t13(double %x) {
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entry:
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; CHECK-LABEL: t13:
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; CHECK-NOT: vmov
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; CHECK: bl ___sincos_stret
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%call = tail call arm_aapcs_vfpcc double @cos(double %x)
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%call1 = tail call arm_aapcs_vfpcc double @sin(double %x)
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%mul = fmul double %call, %call1
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ret double %mul
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}
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define arm_aapcs_vfpcc double @t14(double %x) {
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; CHECK-LABEL: t14:
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; CHECK-NOT: vmov
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; CHECK: b ___exp10
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%__exp10 = tail call double @__exp10(double %x) #1
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ret double %__exp10
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}
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declare arm_aapcs_vfpcc double @x(double, double, double, double, double, double, double, float, double)
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declare arm_aapcs_vfpcc double @cos(double) #0
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declare arm_aapcs_vfpcc double @sin(double) #0
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declare double @__exp10(double)
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attributes #0 = { readnone }
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attributes #1 = { readonly }
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