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Imported Upstream version 5.18.0.234

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Former-commit-id: 8071ec1a8c5eaa9be24b41745add19297608001f
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Xamarin Public Jenkins (auto-signing)
2019-01-08 08:22:36 +00:00
parent f32dbaf0b2
commit 212f6bafcb
28494 changed files with 359 additions and 3867025 deletions
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26
external/llvm/test/CodeGen/X86/i486-fence-loop.ll vendored
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@@ -1,26 +0,0 @@
; RUN: llc -mtriple=i686-- -mcpu=i486 -o - %s | FileCheck %s
; Main test here was that ISelDAG could cope with a MachineNode in the chain
; from the first load to the "X86ISD::SUB". Previously it thought that meant no
; cycle could be formed so it tried to use "sub (%eax), [[RHS]]".
define void @gst_atomic_queue_push(i32* %addr) {
; CHECK-LABEL: gst_atomic_queue_push:
; CHECK: movl (%eax), [[LHS:%e[a-z]+]]
; CHECK: lock orl
; CHECK: movl (%eax), [[RHS:%e[a-z]+]]
; CHECK: cmpl [[LHS]], [[RHS]]
entry:
br label %while.body
while.body:
%0 = load volatile i32, i32* %addr, align 4
fence seq_cst
%1 = load volatile i32, i32* %addr, align 4
%cmp = icmp sgt i32 %1, %0
br i1 %cmp, label %while.body, label %if.then
if.then:
ret void
}