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Imported Upstream version 5.18.0.234

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Former-commit-id: 8071ec1a8c5eaa9be24b41745add19297608001f
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Xamarin Public Jenkins (auto-signing)
2019-01-08 08:22:36 +00:00
parent f32dbaf0b2
commit 212f6bafcb
28494 changed files with 359 additions and 3867025 deletions
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24
external/llvm/test/CodeGen/Mips/lw16-base-reg.ll vendored
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@ -1,24 +0,0 @@
; RUN: llc %s -march=mips -mcpu=mips32r3 -mattr=micromips -filetype=asm \
; RUN: -relocation-model=pic -O3 -o - | FileCheck %s
; The purpose of this test is to check whether the CodeGen selects
; LW16 instruction with the base register in a range of $2-$7, $16, $17.
%struct.T = type { i32 }
$_ZN1TaSERKS_ = comdat any
define linkonce_odr void @_ZN1TaSERKS_(%struct.T* %this, %struct.T* dereferenceable(4) %t) #0 comdat align 2 {
entry:
%this.addr = alloca %struct.T*, align 4
%t.addr = alloca %struct.T*, align 4
%this1 = load %struct.T*, %struct.T** %this.addr, align 4
%0 = load %struct.T*, %struct.T** %t.addr, align 4
%V3 = getelementptr inbounds %struct.T, %struct.T* %0, i32 0, i32 0
%1 = load i32, i32* %V3, align 4
%V4 = getelementptr inbounds %struct.T, %struct.T* %this1, i32 0, i32 0
store i32 %1, i32* %V4, align 4
ret void
}
; CHECK: lw16 ${{[0-9]+}}, 0(${{[2-7]|16|17}})