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Imported Upstream version 5.18.0.234
Former-commit-id: 8071ec1a8c5eaa9be24b41745add19297608001f
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@ -1,95 +0,0 @@
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; RUN: llc -march=mips -mcpu=mips32r6 -O1 -start-after=dwarfehprepare < %s | FileCheck %s
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; RUN: llc -march=mips64 -mcpu=mips64r6 -O1 -start-after=dwarfehprepare < %s | FileCheck %s
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; beqc/bnec have the constraint that $rs < $rt && $rs != 0 && $rt != 0
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; Cases where $rs == 0 and $rt != 0 should be transformed into beqzc/bnezc.
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; Cases where $rs > $rt can have the operands swapped as ==,!= are commutative.
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; Cases where beq & bne where $rs == $rt have to inhibited from being turned
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; into compact branches but arguably should not occur. This test covers the
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; $rs == $rt case.
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; Starting from dwarf exception handling preparation skips optimizations that
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; may simplify out the crucical bnec $4, $4 instruction.
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define internal void @_ZL14TestRemoveLastv(i32* %alist.sroa.0.4) {
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; CHECK-LABEL: _ZL14TestRemoveLastv:
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entry:
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%ascevgep = getelementptr i32, i32* %alist.sroa.0.4, i64 99
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br label %do.body121
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for.cond117:
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%alsr.iv.next = add nsw i32 %alsr.iv, -1
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%ascevgep340 = getelementptr i32, i32* %alsr.iv339, i64 -1
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%acmp118 = icmp sgt i32 %alsr.iv.next, 0
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br i1 %acmp118, label %do.body121, label %if.then143
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do.body121:
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%alsr.iv339 = phi i32* [ %ascevgep, %entry ], [ %ascevgep340, %for.cond117 ]
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%alsr.iv = phi i32 [ 100, %entry ], [ %alsr.iv.next, %for.cond117 ]
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%a9 = add i32 %alsr.iv, -1
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%alnot124 = icmp eq i32 %alsr.iv, %alsr.iv
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br i1 %alnot124, label %do.body134, label %if.then143, !prof !11
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do.body134:
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%a10 = add i32 %alsr.iv, -1
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%a11 = load i32, i32* %alsr.iv339, align 4, !tbaa !5
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; CHECK-NOT: bnec $[[R0:[0-9]+]], $[[R0]]
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; CHECK-NOT: beqc $[[R1:[0-9]+]], $[[R1]]
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%alnot137 = icmp eq i32 %a9, %a11
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br i1 %alnot137, label %do.end146, label %if.then143, !prof !11
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if.then143:
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ret void
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unreachable
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do.end146:
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%alnot151 = icmp eq i32 %a9, %a10
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br i1 %alnot151, label %for.cond117, label %if.then143, !prof !11
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}
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define internal void @_ZL14TestRemoveLastv64(i64* %alist.sroa.0.4) {
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; CHECK-LABEL: _ZL14TestRemoveLastv64:
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entry:
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%ascevgep = getelementptr i64, i64* %alist.sroa.0.4, i64 99
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br label %do.body121
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for.cond117:
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%alsr.iv.next = add nsw i64 %alsr.iv, -1
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%ascevgep340 = getelementptr i64, i64* %alsr.iv339, i64 -1
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%acmp118 = icmp sgt i64 %alsr.iv.next, 0
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br i1 %acmp118, label %do.body121, label %if.then143
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do.body121:
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%alsr.iv339 = phi i64* [ %ascevgep, %entry ], [ %ascevgep340, %for.cond117 ]
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%alsr.iv = phi i64 [ 100, %entry ], [ %alsr.iv.next, %for.cond117 ]
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%a9 = add i64 %alsr.iv, -1
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%alnot124 = icmp eq i64 %alsr.iv, %alsr.iv
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br i1 %alnot124, label %do.body134, label %if.then143, !prof !11
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do.body134:
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%a10 = add i64 %alsr.iv, -1
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%a11 = load i64, i64* %alsr.iv339, align 4, !tbaa !5
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; CHECK-NOT: bnec $[[R0:[0-9]+]], $[[R0]]
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; CHECK-NOT: beqc $[[R1:[0-9]+]], $[[R1]]
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%alnot137 = icmp eq i64 %a9, %a11
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br i1 %alnot137, label %do.end146, label %if.then143, !prof !11
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if.then143:
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ret void
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unreachable
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do.end146:
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%alnot151 = icmp eq i64 %a9, %a10
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br i1 %alnot151, label %for.cond117, label %if.then143, !prof !11
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}
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!3 = !{!"omnipotent char", !4, i64 0}
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!4 = !{!"Simple C++ TBAA"}
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!5 = !{!6, !6, i64 0}
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!6 = !{!"int", !3, i64 0}
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!11 = !{!"branch_weights", i32 2000, i32 1}
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!12 = !{!"branch_weights", i32 -388717296, i32 7818360}
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@ -1,158 +0,0 @@
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# RUN: llc -march=mips64 -mcpu=mips64r6 -start-after=block-placement -o - %s | FileCheck %s
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# Check that MipsHazardSchedule sees through basic blocks with transient instructions.
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# The mir code in this file isn't representative of the llvm-ir.
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--- |
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; ModuleID = 'test.ll'
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source_filename = "test.c"
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target datalayout = "E-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"
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target triple = "mips64-img-linux-gnu"
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; Function Attrs: nounwind
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define i32 @f(i32 signext %a) {
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entry:
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%retval = alloca i32, align 4
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%a.addr = alloca i32, align 4
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store i32 %a, i32* %a.addr, align 4
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%0 = load i32, i32* %a.addr, align 4
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%cmp = icmp sgt i32 %0, 5
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br i1 %cmp, label %if.then, label %if.else
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if.then: ; preds = %entry
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%1 = load i32, i32* %a.addr, align 4
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%2 = load i32, i32* %a.addr, align 4
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%add = add nsw i32 %1, %2
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store i32 %add, i32* %retval, align 4
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br label %return
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if.else: ; preds = %entry
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%3 = load i32, i32* %a.addr, align 4
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%call = call i32 @g(i32 signext %3)
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store i32 %call, i32* %retval, align 4
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br label %return
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return: ; preds = %if.else, %if.then
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%4 = load i32, i32* %retval, align 4
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ret i32 %4
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}
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declare i32 @g(i32 signext)
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; Function Attrs: nounwind
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declare void @llvm.stackprotector(i8*, i8**)
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!llvm.ident = !{!0}
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!0 = !{!"clang version 4.0.0 "}
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...
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---
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# CHECK-LABEL: f:
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# CHECK: bgtzc
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# CHECK-NEXT: nop
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# CHECK: bltzc
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# CHECK-NEXT: nop
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# CHECK: blezc
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name: f
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alignment: 3
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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liveins:
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- { reg: '%a0_64' }
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- { reg: '%t9_64' }
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calleeSavedRegisters: [ '%fp', '%gp', '%ra', '%d12', '%d13', '%d14', '%d15',
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'%f24', '%f25', '%f26', '%f27', '%f28', '%f29',
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'%f30', '%f31', '%fp_64', '%f_hi24', '%f_hi25',
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'%f_hi26', '%f_hi27', '%f_hi28', '%f_hi29', '%f_hi30',
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'%f_hi31', '%gp_64', '%ra_64', '%s0', '%s1', '%s2',
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'%s3', '%s4', '%s5', '%s6', '%s7', '%d24_64', '%d25_64',
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'%d26_64', '%d27_64', '%d28_64', '%d29_64', '%d30_64',
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'%d31_64', '%s0_64', '%s1_64', '%s2_64', '%s3_64',
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'%s4_64', '%s5_64', '%s6_64', '%s7_64' ]
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 32
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offsetAdjustment: 0
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maxAlignment: 8
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adjustsStack: true
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hasCalls: true
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maxCallFrameSize: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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stack:
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- { id: 0, name: retval, offset: -28, size: 4, alignment: 4 }
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- { id: 1, name: a.addr, offset: -32, size: 4, alignment: 4 }
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- { id: 2, type: spill-slot, offset: -8, size: 8, alignment: 8, callee-saved-register: '%ra_64' }
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- { id: 3, type: spill-slot, offset: -16, size: 8, alignment: 8, callee-saved-register: '%fp_64' }
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- { id: 4, type: spill-slot, offset: -24, size: 8, alignment: 8, callee-saved-register: '%gp_64' }
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body: |
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bb.0.entry:
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successors: %bb.1.if.then(0x40000000), %bb.5.if.else(0x40000000)
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liveins: %a0_64, %t9_64, %ra_64, %fp_64, %gp_64
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%sp_64 = DADDiu %sp_64, -32
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CFI_INSTRUCTION def_cfa_offset 32
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SD killed %ra_64, %sp_64, 24 :: (store 8 into %stack.2)
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SD killed %fp_64, %sp_64, 16 :: (store 8 into %stack.3)
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SD killed %gp_64, %sp_64, 8 :: (store 8 into %stack.4)
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CFI_INSTRUCTION offset %ra_64, -8
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CFI_INSTRUCTION offset %fp_64, -16
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CFI_INSTRUCTION offset %gp_64, -24
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CFI_INSTRUCTION def_cfa_register %fp_64
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%at_64 = LUi64 @f
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%v0_64 = DADDu killed %at_64, %t9_64
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SW %a0, %sp_64, 0 :: (store 4 into %ir.a.addr)
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BGTZC %a0, %bb.5.if.else, implicit-def %at
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bb.1.if.then:
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successors: %bb.6.return(0x40000000), %bb.2.if.then(0x40000000)
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liveins: %a0
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BLTZC %a0, %bb.6.return, implicit-def %at
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bb.2.if.then:
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successors: %bb.3.if.else(0x80000000)
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%t8 = IMPLICIT_DEF
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bb.3.if.else:
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successors: %bb.6.return(0x40000000), %bb.4.if.else(0x40000000)
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liveins: %t8
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BLEZC %t8, %bb.6.return, implicit-def %at
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bb.4.if.else:
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successors: %bb.6.return(0x80000000)
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liveins: %t8
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%at = LW %sp_64, 0 :: (dereferenceable load 4 from %ir.a.addr)
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%at = ADDu killed %at, %t8
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SW killed %at, %sp_64, 4 :: (store 4 into %ir.retval)
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J %bb.6.return, implicit-def dead %at
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bb.5.if.else:
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successors: %bb.6.return(0x80000000)
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liveins: %v0_64
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%gp_64 = DADDiu killed %v0_64, @f
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%a0_64 = LW64 %sp_64, 0 :: (dereferenceable load 4 from %ir.a.addr)
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%t9_64 = LD %gp_64, @g :: (load 8 from call-entry @g)
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JALR64Pseudo %t9_64, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit %gp_64, implicit-def %sp, implicit-def %v0
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SW killed %v0, %sp_64, 4 :: (store 4 into %ir.retval)
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bb.6.return:
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%v0 = LW %sp_64, 4 :: (dereferenceable load 4 from %ir.retval)
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%gp_64 = LD %sp_64, 8 :: (load 8 from %stack.4)
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%fp_64 = LD %sp_64, 16 :: (load 8 from %stack.3)
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%ra_64 = LD %sp_64, 24 :: (load 8 from %stack.2)
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%sp_64 = DADDiu %sp_64, 32
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PseudoReturn64 %ra_64
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...
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@ -1,28 +0,0 @@
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; Check that -mips-compact-branches={never,optimal,always} is accepted and honoured.
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; RUN: llc -march=mips -mcpu=mips32r6 -mips-compact-branches=never < %s | FileCheck %s -check-prefix=NEVER
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; RUN: llc -march=mips -mcpu=mips32r6 -mips-compact-branches=optimal < %s | FileCheck %s -check-prefix=OPTIMAL
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; RUN: llc -march=mips -mcpu=mips32r6 -mips-compact-branches=always < %s | FileCheck %s -check-prefix=ALWAYS
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define i32 @l(i32 signext %a, i32 signext %b) {
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entry:
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%add = add nsw i32 %b, %a
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%cmp = icmp slt i32 %add, 100
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; NEVER: beq
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; OPTIMAL: beq
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; ALWAYS: beqzc
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; This nop is required for correct as having (j|b)al as the instruction
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; immediately following beqzc would cause a forbidden slot hazard.
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; ALWAYS: nop
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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%call = tail call i32 @k()
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br label %if.end
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if.end: ; preds = %entry, %if.then
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%call.pn = phi i32 [ %call, %if.then ], [ -1, %entry ]
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%c.0 = add nsw i32 %call.pn, %add
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ret i32 %c.0
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}
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declare i32 @k() #1
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@ -1,195 +0,0 @@
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; RUN: llc -relocation-model=pic -march=mipsel -mcpu=mips64r6 \
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; RUN: -disable-mips-delay-filler -target-abi=n64 < %s | FileCheck %s
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; Function Attrs: nounwind
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define void @l() {
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entry:
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; CHECK-LABEL: l:
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; CHECK: jalrc $25
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%call = tail call i64 @k()
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; CHECK: jalrc $25
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%call1 = tail call i64 @j()
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%cmp = icmp eq i64 %call, %call1
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; CHECK: bnec
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry:
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; CHECK: jalrc $25
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tail call void @f(i64 signext -2)
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br label %if.end
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if.end: ; preds = %if.then, %entry
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; CHECK: jrc $ra
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ret void
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}
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declare i64 @k()
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declare i64 @j()
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declare void @f(i64 signext)
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; Function Attrs: define void @l2() {
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define void @l2() {
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entry:
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; CHECK-LABEL: l2:
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; CHECK: jalrc $25
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%call = tail call i64 @k()
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; CHECK: jalrc $25
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%call1 = tail call i64 @i()
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%cmp = icmp eq i64 %call, %call1
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; CHECK: beqc
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br i1 %cmp, label %if.end, label %if.then
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if.then: ; preds = %entry:
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; CHECK: jalrc $25
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tail call void @f(i64 signext -1)
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br label %if.end
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if.end: ; preds = %entry, %if.then
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; CHECK: jrc $ra
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ret void
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}
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declare i64 @i()
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; Function Attrs: nounwind
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define void @l3() {
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entry:
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; CHECK-LABEL: l3:
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; CHECK: jalrc $25
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%call = tail call i64 @k()
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%cmp = icmp slt i64 %call, 0
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; CHECK: bgez
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry:
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; CHECK: jalrc $25
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tail call void @f(i64 signext 0)
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br label %if.end
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if.end: ; preds = %if.then, %entry
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; CHECK: jrc $ra
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ret void
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}
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; Function Attrs: nounwind
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define void @l4() {
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entry:
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; CHECK-LABEL: l4:
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; CHECK: jalrc $25
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%call = tail call i64 @k()
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%cmp = icmp slt i64 %call, 1
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; CHECK: bgtzc
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry:
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tail call void @f(i64 signext 1)
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br label %if.end
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if.end: ; preds = %if.then, %entry
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; CHECK: jrc $ra
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ret void
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}
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; Function Attrs: nounwind
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define void @l5() {
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entry:
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; CHECK-LABEL: l5:
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; CHECK: jalrc $25
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%call = tail call i64 @k()
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%cmp = icmp sgt i64 %call, 0
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; CHECK: blezc
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||||
br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry:
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; CHECK: jalrc $25
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tail call void @f(i64 signext 2)
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br label %if.end
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if.end: ; preds = %if.then, %entry
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; CHECK: jrc $ra
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ret void
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}
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; Function Attrs: nounwind
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||||
define void @l6() {
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entry:
|
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; CHECK-LABEL: l6:
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; CHECK: jalrc $25
|
||||
%call = tail call i64 @k()
|
||||
%cmp = icmp sgt i64 %call, -1
|
||||
; CHECK: bltzc
|
||||
br i1 %cmp, label %if.then, label %if.end
|
||||
|
||||
if.then: ; preds = %entry:
|
||||
; CHECK: jalrc $25
|
||||
tail call void @f(i64 signext 3)
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %if.then, %entry
|
||||
; CHECK: jrc $ra
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @l7() {
|
||||
entry:
|
||||
; CHECK-LABEL: l7:
|
||||
; CHECK: jalrc $25
|
||||
%call = tail call i64 @k()
|
||||
%cmp = icmp eq i64 %call, 0
|
||||
; CHECK: bnezc
|
||||
br i1 %cmp, label %if.then, label %if.end
|
||||
|
||||
if.then: ; preds = %entry:
|
||||
; CHECK: jalrc $25
|
||||
tail call void @f(i64 signext 4)
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %if.then, %entry
|
||||
; CHECK: jrc $ra
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @l8() {
|
||||
entry:
|
||||
; CHECK-LABEL: l8:
|
||||
; CHECK: jalrc $25
|
||||
%call = tail call i64 @k()
|
||||
%cmp = icmp eq i64 %call, 0
|
||||
; CHECK: beqzc
|
||||
br i1 %cmp, label %if.end, label %if.then
|
||||
|
||||
if.then: ; preds = %entry:
|
||||
; CHECK: jalrc $25
|
||||
tail call void @f(i64 signext 5)
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %entry, %if.then
|
||||
; CHECK: jrc $ra
|
||||
ret void
|
||||
}
|
||||
|
||||
define i64 @l9(i8* ()* %i) {
|
||||
entry:
|
||||
; CHECK-LABEL: l9:
|
||||
%i.addr = alloca i8* ()*, align 4
|
||||
store i8* ()* %i, i8* ()** %i.addr, align 4
|
||||
; CHECK: jalrc $25
|
||||
%call = call i64 @k()
|
||||
%cmp = icmp ne i64 %call, 0
|
||||
; CHECK: beqzc
|
||||
br i1 %cmp, label %if.then, label %if.end
|
||||
|
||||
if.then: ; preds = %entry
|
||||
%0 = load i8* ()*, i8* ()** %i.addr, align 4
|
||||
; CHECK: jalrc $25
|
||||
%call1 = call i8* %0()
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %if.then, %entry
|
||||
; CHECK: jrc $ra
|
||||
ret i64 -1
|
||||
}
|
||||
@ -1,208 +0,0 @@
|
||||
; RUN: llc -march=mipsel -mcpu=mips32r6 -relocation-model=static \
|
||||
; RUN: -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=STATIC32
|
||||
; RUN: llc -march=mipsel -mcpu=mips64r6 -relocation-model=pic -target-abi n64 \
|
||||
; RUN: -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=PIC
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @l() {
|
||||
entry:
|
||||
; PIC: jalrc $25
|
||||
%call = tail call i32 @k()
|
||||
; PIC: jalrc $25
|
||||
%call1 = tail call i32 @j()
|
||||
%cmp = icmp eq i32 %call, %call1
|
||||
; CHECK: bnec
|
||||
br i1 %cmp, label %if.then, label %if.end
|
||||
|
||||
if.then: ; preds = %entry:
|
||||
; STATIC: nop
|
||||
; STATIC: jal
|
||||
; PIC: jalrc $25
|
||||
tail call void @f(i32 signext -2)
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %if.then, %entry
|
||||
; CHECK: jrc $ra
|
||||
ret void
|
||||
}
|
||||
|
||||
declare i32 @k()
|
||||
|
||||
declare i32 @j()
|
||||
|
||||
declare void @f(i32 signext)
|
||||
|
||||
; Function Attrs: define void @l2() {
|
||||
define void @l2() {
|
||||
entry:
|
||||
; PIC: jalrc $25
|
||||
%call = tail call i32 @k()
|
||||
; PIC: jalrc $25
|
||||
%call1 = tail call i32 @i()
|
||||
%cmp = icmp eq i32 %call, %call1
|
||||
; CHECK: beqc
|
||||
br i1 %cmp, label %if.end, label %if.then
|
||||
|
||||
if.then: ; preds = %entry:
|
||||
; STATIC: nop
|
||||
; STATIC: jal
|
||||
; PIC: jalrc $25
|
||||
tail call void @f(i32 signext -1)
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %entry, %if.then
|
||||
; CHECK: jrc $ra
|
||||
ret void
|
||||
}
|
||||
|
||||
declare i32 @i()
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @l3() {
|
||||
entry:
|
||||
; PIC: jalrc $25
|
||||
%call = tail call i32 @k()
|
||||
%cmp = icmp slt i32 %call, 0
|
||||
; CHECK: bgez
|
||||
br i1 %cmp, label %if.then, label %if.end
|
||||
|
||||
if.then: ; preds = %entry:
|
||||
; STATIC: nop
|
||||
; STATIC: jal
|
||||
; PIC: jalrc $25
|
||||
tail call void @f(i32 signext 0)
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %if.then, %entry
|
||||
; CHECK: jrc $ra
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @l4() {
|
||||
entry:
|
||||
%call = tail call i32 @k()
|
||||
%cmp = icmp slt i32 %call, 1
|
||||
; CHECK: bgtzc
|
||||
br i1 %cmp, label %if.then, label %if.end
|
||||
|
||||
if.then: ; preds = %entry:
|
||||
; STATIC: nop
|
||||
; STATIC: jal
|
||||
tail call void @f(i32 signext 1)
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %if.then, %entry
|
||||
; CHECK: jrc $ra
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @l5() {
|
||||
entry:
|
||||
; PIC: jalrc $25
|
||||
%call = tail call i32 @k()
|
||||
; PIC: jalrc $25
|
||||
%cmp = icmp sgt i32 %call, 0
|
||||
; CHECK: blezc
|
||||
br i1 %cmp, label %if.then, label %if.end
|
||||
|
||||
if.then: ; preds = %entry:
|
||||
; STATIC: nop
|
||||
; STATIC: jal
|
||||
; PIC: jalrc $25
|
||||
tail call void @f(i32 signext 2)
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %if.then, %entry
|
||||
; CHECK: jrc $ra
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @l6() {
|
||||
entry:
|
||||
; PIC: jalrc $25
|
||||
%call = tail call i32 @k()
|
||||
; PIC: jalrc $25
|
||||
%cmp = icmp sgt i32 %call, -1
|
||||
; CHECK: bltzc
|
||||
br i1 %cmp, label %if.then, label %if.end
|
||||
|
||||
if.then: ; preds = %entry:
|
||||
; STATIC: nop
|
||||
; STATIC: jal
|
||||
; PIC: jalrc $25
|
||||
tail call void @f(i32 signext 3)
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %if.then, %entry
|
||||
; CHECK: jrc $ra
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @l7() {
|
||||
entry:
|
||||
; PIC: jalrc $25
|
||||
%call = tail call i32 @k()
|
||||
%cmp = icmp eq i32 %call, 0
|
||||
; CHECK: bnezc
|
||||
br i1 %cmp, label %if.then, label %if.end
|
||||
|
||||
if.then: ; preds = %entry:
|
||||
; STATIC: nop
|
||||
; STATIC: jal
|
||||
; PIC: jalrc $25
|
||||
tail call void @f(i32 signext 4)
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %if.then, %entry
|
||||
; CHECK: jrc $ra
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @l8() {
|
||||
entry:
|
||||
; PIC: jalrc $25
|
||||
%call = tail call i32 @k()
|
||||
%cmp = icmp eq i32 %call, 0
|
||||
; CHECK: beqzc
|
||||
br i1 %cmp, label %if.end, label %if.then
|
||||
|
||||
if.then: ; preds = %entry:
|
||||
; STATIC: nop
|
||||
; STATIC: jal
|
||||
; PIC: jalrc $25
|
||||
tail call void @f(i32 signext 5)
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %entry, %if.then
|
||||
; CHECK: jrc $ra
|
||||
ret void
|
||||
}
|
||||
|
||||
define i32 @l9(i8* ()* %i) #0 {
|
||||
entry:
|
||||
%i.addr = alloca i8* ()*, align 4
|
||||
store i8* ()* %i, i8* ()** %i.addr, align 4
|
||||
; STATIC32: jal
|
||||
; STATIC32: nop
|
||||
; PIC: jalrc $25
|
||||
%call = call i32 @k()
|
||||
; PIC: jalrc $25
|
||||
%cmp = icmp ne i32 %call, 0
|
||||
; CHECK: beqzc
|
||||
br i1 %cmp, label %if.then, label %if.end
|
||||
|
||||
if.then: ; preds = %entry
|
||||
%0 = load i8* ()*, i8* ()** %i.addr, align 4
|
||||
; CHECK: jalrc $25
|
||||
%call1 = call i8* %0()
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %if.then, %entry
|
||||
; CHECK: jrc $ra
|
||||
ret i32 -1
|
||||
}
|
||||
@ -1,91 +0,0 @@
|
||||
# RUN: llc -march=mipsel -mcpu=mips32r6 -start-after=block-placement %s -o - | FileCheck %s
|
||||
|
||||
# Check that empty blocks in the cfg don't cause the mips hazard scheduler to
|
||||
# crash and that the nop is inserted correctly.
|
||||
|
||||
# CHECK: blezc
|
||||
# CHECK: nop
|
||||
# CHECK: # %bb.1:
|
||||
# CHECK: .insn
|
||||
# CHECK: # %bb.2:
|
||||
# CHECK: .insn
|
||||
# CHECK: # %bb.3:
|
||||
# CHECK: jal
|
||||
|
||||
--- |
|
||||
; ModuleID = '<stdin>'
|
||||
source_filename = "<stdin>"
|
||||
target datalayout = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"
|
||||
|
||||
declare i32 @k()
|
||||
|
||||
declare void @f(i32)
|
||||
|
||||
define void @l5() {
|
||||
entry:
|
||||
%call = tail call i32 @k()
|
||||
%cmp = icmp sgt i32 %call, 0
|
||||
br i1 %cmp, label %if.then, label %if.end
|
||||
|
||||
if.then: ; preds = %entry
|
||||
tail call void @f(i32 signext 2)
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %if.then, %entry
|
||||
ret void
|
||||
}
|
||||
|
||||
---
|
||||
name: l5
|
||||
alignment: 2
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
tracksRegLiveness: true
|
||||
frameInfo:
|
||||
isFrameAddressTaken: false
|
||||
isReturnAddressTaken: false
|
||||
hasStackMap: false
|
||||
hasPatchPoint: false
|
||||
stackSize: 24
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 4
|
||||
adjustsStack: true
|
||||
hasCalls: true
|
||||
maxCallFrameSize: 16
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
stack:
|
||||
- { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '%ra' }
|
||||
body: |
|
||||
bb.0.entry:
|
||||
successors: %bb.1.if.then(0x50000000), %bb.4.if.end(0x30000000)
|
||||
liveins: %ra
|
||||
|
||||
%sp = ADDiu %sp, -24
|
||||
CFI_INSTRUCTION def_cfa_offset 24
|
||||
SW killed %ra, %sp, 20 :: (store 4 into %stack.0)
|
||||
CFI_INSTRUCTION offset %ra_64, -4
|
||||
JAL @k, csr_o32_fp64, implicit-def dead %ra, implicit-def %sp, implicit-def %v0
|
||||
BLEZ %v0, %bb.4.if.end, implicit-def %at
|
||||
|
||||
bb.1.if.then:
|
||||
successors: %bb.2.if.then(0x80000000)
|
||||
|
||||
bb.2.if.then:
|
||||
successors: %bb.3.if.then(0x80000000)
|
||||
|
||||
bb.3.if.then:
|
||||
successors: %bb.4.if.end(0x80000000)
|
||||
|
||||
%a0 = ADDiu %zero, 2
|
||||
JAL @f, csr_o32_fp64, implicit-def dead %ra, implicit killed %a0, implicit-def %sp
|
||||
|
||||
bb.4.if.end:
|
||||
%ra = LW %sp, 20 :: (load 4 from %stack.0)
|
||||
%sp = ADDiu %sp, 24
|
||||
PseudoReturn undef %ra
|
||||
|
||||
...
|
||||
@ -1,130 +0,0 @@
|
||||
; RUN: llc -march=mipsel -mcpu=mips32r6 -disable-mips-delay-filler < %s | FileCheck %s
|
||||
; RUN: llc -march=mips -mcpu=mips32r6 -disable-mips-delay-filler < %s -filetype=obj \
|
||||
; RUN: -o - | llvm-objdump -d - | FileCheck %s -check-prefix=ENCODING
|
||||
; RUN: llc -march=mipsel -mcpu=mips64r6 -disable-mips-delay-filler -target-abi=n64 < %s | FileCheck %s
|
||||
; RUN: llc -march=mips -mcpu=mips64r6 -disable-mips-delay-filler -target-abi=n64 < %s -filetype=obj \
|
||||
; RUN: -o - | llvm-objdump -d - | FileCheck %s -check-prefix=ENCODING
|
||||
|
||||
; bnezc and beqzc have restriction that $rt != 0
|
||||
|
||||
define i32 @f() {
|
||||
; CHECK-LABEL: f:
|
||||
; CHECK-NOT: bnezc $0
|
||||
|
||||
%cmp = icmp eq i32 1, 1
|
||||
br i1 %cmp, label %if.then, label %if.end
|
||||
|
||||
if.then:
|
||||
ret i32 1
|
||||
|
||||
if.end:
|
||||
ret i32 0
|
||||
}
|
||||
|
||||
define i32 @f1() {
|
||||
; CHECK-LABEL: f1:
|
||||
; CHECK-NOT: beqzc $0
|
||||
|
||||
%cmp = icmp eq i32 0, 0
|
||||
br i1 %cmp, label %if.then, label %if.end
|
||||
|
||||
if.then:
|
||||
ret i32 1
|
||||
|
||||
if.end:
|
||||
ret i32 0
|
||||
}
|
||||
|
||||
; We silently fixup cases where the register allocator or user has given us
|
||||
; an instruction with incorrect operands that is trivially acceptable.
|
||||
; beqc and bnec have the restriction that $rs < $rt.
|
||||
|
||||
define i32 @f2(i32 %a, i32 %b) {
|
||||
; ENCODING-LABEL: f2:
|
||||
; ENCODING-NOT: beqc $5, $4
|
||||
; ENCODING-NOT: bnec $5, $4
|
||||
|
||||
%cmp = icmp eq i32 %b, %a
|
||||
br i1 %cmp, label %if.then, label %if.end
|
||||
|
||||
if.then:
|
||||
ret i32 1
|
||||
|
||||
if.end:
|
||||
ret i32 0
|
||||
}
|
||||
|
||||
define i64 @f3() {
|
||||
; CHECK-LABEL: f3:
|
||||
; CHECK-NOT: bnezc $0
|
||||
|
||||
%cmp = icmp eq i64 1, 1
|
||||
br i1 %cmp, label %if.then, label %if.end
|
||||
|
||||
if.then:
|
||||
ret i64 1
|
||||
|
||||
if.end:
|
||||
ret i64 0
|
||||
}
|
||||
|
||||
define i64 @f4() {
|
||||
; CHECK-LABEL: f4:
|
||||
; CHECK-NOT: beqzc $0
|
||||
|
||||
%cmp = icmp eq i64 0, 0
|
||||
br i1 %cmp, label %if.then, label %if.end
|
||||
|
||||
if.then:
|
||||
ret i64 1
|
||||
|
||||
if.end:
|
||||
ret i64 0
|
||||
}
|
||||
|
||||
; We silently fixup cases where the register allocator or user has given us
|
||||
; an instruction with incorrect operands that is trivially acceptable.
|
||||
; beqc and bnec have the restriction that $rs < $rt.
|
||||
|
||||
define i64 @f5(i64 %a, i64 %b) {
|
||||
; ENCODING-LABEL: f5:
|
||||
; ENCODING-NOT: beqc $5, $4
|
||||
; ENCODING-NOT: bnec $5, $4
|
||||
|
||||
%cmp = icmp eq i64 %b, %a
|
||||
br i1 %cmp, label %if.then, label %if.end
|
||||
|
||||
if.then:
|
||||
ret i64 1
|
||||
|
||||
if.end:
|
||||
ret i64 0
|
||||
}
|
||||
|
||||
define i32 @f6(i32 %a) {
|
||||
; CHECK-LABEL: f6:
|
||||
; CHECK: beqzc ${{[0-9]+}}, $BB
|
||||
|
||||
%cmp = icmp eq i32 %a, 0
|
||||
br i1 %cmp, label %if.then, label %if.end
|
||||
|
||||
if.then:
|
||||
ret i32 1
|
||||
|
||||
if.end:
|
||||
ret i32 0
|
||||
}
|
||||
|
||||
define i32 @f7(i32 %a) {
|
||||
; CHECK-LABEL: f7:
|
||||
; CHECK: bnezc ${{[0-9]+}}, $BB
|
||||
|
||||
%cmp = icmp eq i32 0, %a
|
||||
br i1 %cmp, label %if.then, label %if.end
|
||||
|
||||
if.then:
|
||||
ret i32 1
|
||||
|
||||
if.end:
|
||||
ret i32 0
|
||||
}
|
||||
@ -1,34 +0,0 @@
|
||||
; RUN: llc -march=mips64el -O0 -mcpu=mips64r6 < %s | FileCheck %s
|
||||
; RUN: llc -march=mips64 -O0 -mcpu=mips64r6 < %s | FileCheck %s
|
||||
|
||||
@boo = global i32 0, align 4
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @_Z3foov() #0 {
|
||||
entry:
|
||||
%0 = load volatile i32, i32* @boo, align 4
|
||||
switch i32 %0, label %sw.epilog [
|
||||
i32 0, label %sw.bb
|
||||
i32 1, label %sw.bb1
|
||||
i32 2, label %sw.bb1
|
||||
]
|
||||
|
||||
sw.bb: ; preds = %entry
|
||||
store volatile i32 1, i32* @boo, align 4
|
||||
br label %sw.epilog
|
||||
; CHECK: beqzc
|
||||
; CHECK-NEXT: nop
|
||||
; CHECK-NEXT: .LBB
|
||||
; CHECK-NEXT: j
|
||||
|
||||
sw.bb1: ; preds = %entry, %entry
|
||||
store volatile i32 2, i32* @boo, align 4
|
||||
br label %sw.epilog
|
||||
; CHECK: bnezc
|
||||
; CHECK-NEXT: nop
|
||||
; CHECK-NEXT: .LBB
|
||||
; CHECK-NEXT: j
|
||||
|
||||
sw.epilog: ; preds = %entry, %sw.bb1, %sw.bb
|
||||
ret void
|
||||
}
|
||||
Reference in New Issue
Block a user