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172 lines
4.5 KiB
C++
172 lines
4.5 KiB
C++
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//===-- AVRInstPrinter.cpp - Convert AVR MCInst to assembly syntax --------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This class prints an AVR MCInst to a .s file.
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//
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//===----------------------------------------------------------------------===//
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#include "AVRInstPrinter.h"
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#include "MCTargetDesc/AVRMCTargetDesc.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/FormattedStream.h"
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#include <cstring>
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#define DEBUG_TYPE "asm-printer"
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namespace llvm {
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// Include the auto-generated portion of the assembly writer.
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#define PRINT_ALIAS_INSTR
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#include "AVRGenAsmWriter.inc"
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void AVRInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
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StringRef Annot, const MCSubtargetInfo &STI) {
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unsigned Opcode = MI->getOpcode();
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// First handle load and store instructions with postinc or predec
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// of the form "ld reg, X+".
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// TODO: We should be able to rewrite this using TableGen data.
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switch (Opcode) {
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case AVR::LDRdPtr:
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case AVR::LDRdPtrPi:
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case AVR::LDRdPtrPd:
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O << "\tld\t";
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printOperand(MI, 0, O);
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O << ", ";
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if (Opcode == AVR::LDRdPtrPd)
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O << '-';
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printOperand(MI, 1, O);
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if (Opcode == AVR::LDRdPtrPi)
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O << '+';
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break;
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case AVR::STPtrRr:
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O << "\tst\t";
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printOperand(MI, 0, O);
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O << ", ";
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printOperand(MI, 1, O);
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break;
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case AVR::STPtrPiRr:
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case AVR::STPtrPdRr:
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O << "\tst\t";
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if (Opcode == AVR::STPtrPdRr)
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O << '-';
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printOperand(MI, 1, O);
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if (Opcode == AVR::STPtrPiRr)
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O << '+';
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O << ", ";
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printOperand(MI, 2, O);
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break;
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default:
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if (!printAliasInstr(MI, O))
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printInstruction(MI, O);
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printAnnotation(O, Annot);
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break;
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}
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}
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const char *AVRInstPrinter::getPrettyRegisterName(unsigned RegNum,
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MCRegisterInfo const &MRI) {
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// GCC prints register pairs by just printing the lower register
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// If the register contains a subregister, print it instead
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if (MRI.getNumSubRegIndices() > 0) {
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unsigned RegLoNum = MRI.getSubReg(RegNum, AVR::sub_lo);
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RegNum = (RegLoNum != AVR::NoRegister) ? RegLoNum : RegNum;
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}
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return getRegisterName(RegNum);
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}
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void AVRInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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const MCOperand &Op = MI->getOperand(OpNo);
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const MCOperandInfo &MOI = this->MII.get(MI->getOpcode()).OpInfo[OpNo];
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if (Op.isReg()) {
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bool isPtrReg = (MOI.RegClass == AVR::PTRREGSRegClassID) ||
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(MOI.RegClass == AVR::PTRDISPREGSRegClassID) ||
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(MOI.RegClass == AVR::ZREGRegClassID);
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if (isPtrReg) {
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O << getRegisterName(Op.getReg(), AVR::ptr);
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} else {
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O << getPrettyRegisterName(Op.getReg(), MRI);
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}
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} else if (Op.isImm()) {
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O << Op.getImm();
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} else {
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assert(Op.isExpr() && "Unknown operand kind in printOperand");
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O << *Op.getExpr();
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}
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}
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/// This is used to print an immediate value that ends up
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/// being encoded as a pc-relative value.
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void AVRInstPrinter::printPCRelImm(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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const MCOperand &Op = MI->getOperand(OpNo);
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if (Op.isImm()) {
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int64_t Imm = Op.getImm();
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O << '.';
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// Print a position sign if needed.
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// Negative values have their sign printed automatically.
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if (Imm >= 0)
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O << '+';
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O << Imm;
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} else {
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assert(Op.isExpr() && "Unknown pcrel immediate operand");
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O << *Op.getExpr();
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}
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}
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void AVRInstPrinter::printMemri(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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assert(MI->getOperand(OpNo).isReg() && "Expected a register for the first operand");
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const MCOperand &OffsetOp = MI->getOperand(OpNo + 1);
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// Print the register.
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printOperand(MI, OpNo, O);
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// Print the {+,-}offset.
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if (OffsetOp.isImm()) {
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int64_t Offset = OffsetOp.getImm();
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if (Offset >= 0)
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O << '+';
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O << Offset;
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} else if (OffsetOp.isExpr()) {
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O << *OffsetOp.getExpr();
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} else {
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llvm_unreachable("unknown type for offset");
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}
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}
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} // end of namespace llvm
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