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cmp-promote.ll
cmp-to-genreg.ll
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cmp.ll
cmp_pred.ll
cmp_pred2.ll
cmp_pred_reg.ll
cmpb-dec-imm.ll
cmpb-eq.ll
cmpb_pred.ll
cmph-gtu.ll
combine.ll
combine_ir.ll
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compound.ll
const-pool-tf.ll
const64.ll
constp-clb.ll
constp-combine-neg.ll
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convert_const_i1_to_i8.ll
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convertsptoint.ll
convertsptoll.ll
copy-to-combine-dbg.ll
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ctor.ll
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dead-store-stack.ll
dmul.ll
double.ll
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dsub.ll
dualstore.ll
duplex-addi-global-imm.mir
duplex.ll
early-if-conversion-bug1.ll
early-if-debug.mir
early-if-merge-loop.ll
early-if-phi-i1.ll
early-if-spare.ll
early-if-vecpi.ll
early-if-vecpred.ll
early-if.ll
eh_return.ll
eliminate-pred-spill.ll
expand-condsets-basic.ll
expand-condsets-dead-bad.ll
expand-condsets-dead-pred.ll
expand-condsets-def-undef.mir
expand-condsets-extend.ll
expand-condsets-imm.mir
expand-condsets-impuse.mir
expand-condsets-pred-undef.ll
expand-condsets-rm-reg.mir
expand-condsets-rm-segment.ll
expand-condsets-same-inputs.mir
expand-condsets-undef.ll
expand-condsets-undef2.ll
expand-condsets-undefvni.ll
expand-vselect-kill.ll
expand-vstorerw-undef.ll
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extload-combine.ll
extract-basic.ll
fadd.ll
fcmp.ll
find-loop-instr.ll
fixed-spill-mutable.ll
float-amode.ll
float.ll
floatconvert-ieee-rnd-near.ll
fminmax.ll
fmul.ll
fpelim-basic.ll
frame-offset-overflow.ll
fsel.ll
fsub.ll
fusedandshift.ll
gp-plus-offset-load.ll
gp-plus-offset-store.ll
gp-rel.ll
hasfp-crash1.ll
hasfp-crash2.ll
hexagon_vector_loop_carried_reuse.ll
hexagon_vector_loop_carried_reuse_constant.ll
hvx-nontemporal.ll
hwloop-cleanup.ll
hwloop-const.ll
hwloop-crit-edge.ll
hwloop-dbg.ll
hwloop-le.ll
hwloop-loop1.ll
hwloop-lt.ll
hwloop-lt1.ll
hwloop-missed.ll
hwloop-ne.ll
hwloop-noreturn-call.ll
hwloop-ph-deadcode.ll
hwloop-pos-ivbump1.ll
hwloop-preh.ll
hwloop-preheader.ll
hwloop-range.ll
hwloop-recursion.ll
hwloop-redef-imm.mir
hwloop-wrap.ll
hwloop-wrap2.ll
hwloop1.ll
hwloop2.ll
hwloop3.ll
hwloop4.ll
hwloop5.ll
i16_VarArg.ll
i1_VarArg.ll
i8_VarArg.ll
idxload-with-zero-offset.ll
ifcvt-common-kill.mir
ifcvt-diamond-bad.ll
ifcvt-diamond-bug-2016-08-26.ll
ifcvt-diamond-ret.mir
ifcvt-edge-weight.ll
ifcvt-impuse-livein.mir
ifcvt-live-subreg.mir
ifcvt-simple-bprob.ll
indirect-br.ll
inline-asm-a.ll
inline-asm-bad-constraint.ll
inline-asm-hexagon.ll
inline-asm-i1.ll
inline-asm-qv.ll
inline-asm-vecpred128.ll
insert-basic.ll
insert4.ll
invalid-dotnew-attempt.mir
is-legal-void.ll
isel-combine-half.ll
isel-exti1.ll
isel-i1arg-crash.ll
isel-op-zext-i1.ll
isel-prefer.ll
jt-in-text.ll
lit.local.cfg
livephysregs-add-pristines.mir
livephysregs-lane-masks.mir
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loadi1-G0.ll
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mem-fi-add.ll
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mind.ll
minu-zext-16.ll
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misaligned-access.ll
misaligned_double_vector_store_not_fast.ll
misched-top-rptracker-sync.ll
mpy.ll
mul64-sext.ll
mulh.ll
mulhs.ll
multi-cycle.ll
mux-basic.ll
mux-kill1.mir
mux-kill2.mir
mux-kill3.mir
mux-undef.ll
newify-crash.ll
newvalueSameReg.ll
newvaluejump-c4.mir
newvaluejump-kill.ll
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newvaluejump.ll
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packetize-return-arg.ll
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propagate-vcombine.ll
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rdf-copy.ll
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rdf-dead-loop.ll
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rdf-extra-livein.ll
rdf-filter-defs.ll
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rdf-inline-asm-fixed.ll
rdf-inline-asm.ll
rdf-multiple-phis-up.ll
rdf-phi-shadows.ll
rdf-phi-up.ll
rdf-reset-kills.ll
readcyclecounter.ll
reg-scavengebug-3.ll
reg-scavenger-valid-slot.ll
regalloc-bad-undef.mir
regalloc-block-overlap.ll
regalloc-liveout-undef.mir
relax.ll
remove-endloop.ll
remove_lsr.ll
restore-single-reg.ll
ret-struct-by-val.ll
runtime-stkchk.ll
sdata-array.ll
sdata-basic.ll
sdr-basic.ll
sdr-shr32.ll
section_7275.ll
select-instr-align.ll
sf-min-max.ll
sffms.ll
shrink-frame-basic.ll
signed_immediates.ll
simple_addend.ll
simpletailcall.ll
split-const32-const64.ll
stack-align-reset.ll
stack-align1.ll
stack-align2.ll
stack-alloca1.ll
stack-alloca2.ll
static.ll
store-imm-amode.ll
store-imm-large-stack.ll
store-imm-stack-object.ll
store-shift.ll
store-widen-aliased-load.ll
store-widen-negv.ll
store-widen-negv2.ll
store-widen.ll
storerd-io-over-rr.ll
storerinewabs.ll
struct_args.ll
struct_args_large.ll
sube.ll
subi-asl.ll
switch-lut-explicit-section.ll
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switch-lut-multiple-functions.ll
switch-lut-text-section.ll
swp-const-tc.ll
swp-dag-phi.ll
swp-epilog-phi10.ll
swp-epilog-reuse-1.ll
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swp-matmul-bitext.ll
swp-max.ll
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vector-align.ll
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vpack_eo.ll
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zextloadi1.ll
Inputs
Lanai
MIR
MSP430
Mips
NVPTX
Nios2
PowerPC
RISCV
SPARC
SystemZ
Thumb
Thumb2
WebAssembly
WinEH
X86
XCore
DebugInfo
Examples
ExecutionEngine
Feature
FileCheck
Instrumentation
Integer
JitListener
LTO
Linker
MC
Object
ObjectYAML
Other
SafepointIRVerifier
SymbolRewriter
TableGen
ThinLTO
Transforms
Unit
Verifier
YAMLParser
tools
.clang-format
CMakeLists.txt
TestRunner.sh
lit.cfg.py
lit.site.cfg.py.in
tools
unittests
utils
.arcconfig
.clang-format
.clang-tidy
.gitattributes
.gitignore
CMakeLists.txt
CODE_OWNERS.TXT
CREDITS.TXT
LICENSE.TXT
LLVMBuild.txt
README.txt
RELEASE_TESTERS.TXT
configure
llvm.spec.in
version.txt.in
nuget
openmp
polly
Directory.Build.props
Directory.Build.targets
NuGet.config
azure-pipelines.yml
build.cmd
build.sh
dir.common.props
global.json
llvm.proj
mxe-Win64.cmake.in
nuget-buildtasks
nunit-lite
roslyn-binaries
rx
xunit-binaries
how-to-bump-roslyn-binaries.md
ikvm-native
llvm
m4
man
mcs
mono
msvc
netcore
po
runtime
samples
scripts
support
tools
COPYING.LIB
LICENSE
Makefile.am
Makefile.in
NEWS
README.md
acinclude.m4
aclocal.m4
autogen.sh
code_of_conduct.md
compile
config.guess
config.h.in
config.rpath
config.sub
configure.REMOVED.git-id
configure.ac.REMOVED.git-id
depcomp
install-sh
ltmain.sh.REMOVED.git-id
missing
mkinstalldirs
mono-uninstalled.pc.in
test-driver
winconfig.h
30 lines
905 B
LLVM
30 lines
905 B
LLVM
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; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s
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;
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; Check that the testcase compiles successfully. Expect that if-conversion
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; took place.
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; CHECK-LABEL: fred:
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; CHECK: if (!p0) r1 = memw(r0+#0)
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target triple = "hexagon"
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define void @fred(i32 %p0) local_unnamed_addr align 2 {
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b0:
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br i1 undef, label %b1, label %b2
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b1: ; preds = %b0
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%t0 = load i8*, i8** undef, align 4
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br label %b2
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b2: ; preds = %b1, %b0
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%t1 = phi i8* [ %t0, %b1 ], [ undef, %b0 ]
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%t2 = getelementptr inbounds i8, i8* %t1, i32 %p0
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tail call void @llvm.memmove.p0i8.p0i8.i32(i8* undef, i8* %t2, i32 undef, i32 1, i1 false) #1
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unreachable
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}
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declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i32, i1) #0
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attributes #0 = { argmemonly nounwind }
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attributes #1 = { nounwind }
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